···106106#define CS4270_MUTE_DAC_A 0x01107107#define CS4270_MUTE_DAC_B 0x02108108109109+/* Power-on default values for the registers110110+ *111111+ * This array contains the power-on default values of the registers, with the112112+ * exception of the "CHIPID" register (01h). The lower four bits of that113113+ * register contain the hardware revision, so it is treated as volatile.114114+ *115115+ * Also note that on the CS4270, the first readable register is 1, but ASoC116116+ * assumes the first register is 0. Therfore, the array must have an entry for117117+ * register 0, but we use cs4270_reg_is_readable() to tell ASoC that it can't118118+ * be read.119119+ */120120+static const u8 cs4270_default_reg_cache[CS4270_LASTREG + 1] = {121121+ 0x00, 0x00, 0x00, 0x30, 0x00, 0x60, 0x20, 0x00, 0x00122122+};123123+109124static const char *supply_names[] = {110125 "va", "vd", "vlc"111126};···192177193178/* The number of MCLK/LRCK ratios supported by the CS4270 */194179#define NUM_MCLK_RATIOS ARRAY_SIZE(cs4270_mode_ratios)180180+181181+static int cs4270_reg_is_readable(unsigned int reg)182182+{183183+ return (reg >= CS4270_FIRSTREG) && (reg <= CS4270_LASTREG);184184+}185185+186186+static int cs4270_reg_is_volatile(unsigned int reg)187187+{188188+ /* Unreadable registers are considered volatile */189189+ if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))190190+ return 1;191191+192192+ return reg == CS4270_CHIPID;193193+}195194196195/**197196 * cs4270_set_dai_sysclk - determine the CS4270 samples rates.···289260 }290261291262 return ret;292292-}293293-294294-/**295295- * cs4270_fill_cache - pre-fill the CS4270 register cache.296296- * @codec: the codec for this CS4270297297- *298298- * This function fills in the CS4270 register cache by reading the register299299- * values from the hardware.300300- *301301- * This CS4270 registers are cached to avoid excessive I2C I/O operations.302302- * After the initial read to pre-fill the cache, the CS4270 never updates303303- * the register values, so we won't have a cache coherency problem.304304- *305305- * We use the auto-increment feature of the CS4270 to read all registers in306306- * one shot.307307- */308308-static int cs4270_fill_cache(struct snd_soc_codec *codec)309309-{310310- u8 *cache = codec->reg_cache;311311- struct i2c_client *i2c_client = codec->control_data;312312- s32 length;313313-314314- length = i2c_smbus_read_i2c_block_data(i2c_client,315315- CS4270_FIRSTREG | CS4270_I2C_INCR, CS4270_NUMREGS, cache);316316-317317- if (length != CS4270_NUMREGS) {318318- dev_err(codec->dev, "i2c read failure, addr=0x%x\n",319319- i2c_client->addr);320320- return -EIO;321321- }322322-323323- return 0;324324-}325325-326326-/**327327- * cs4270_read_reg_cache - read from the CS4270 register cache.328328- * @codec: the codec for this CS4270329329- * @reg: the register to read330330- *331331- * This function returns the value for a given register. It reads only from332332- * the register cache, not the hardware itself.333333- *334334- * This CS4270 registers are cached to avoid excessive I2C I/O operations.335335- * After the initial read to pre-fill the cache, the CS4270 never updates336336- * the register values, so we won't have a cache coherency problem.337337- */338338-static unsigned int cs4270_read_reg_cache(struct snd_soc_codec *codec,339339- unsigned int reg)340340-{341341- u8 *cache = codec->reg_cache;342342-343343- if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))344344- return -EIO;345345-346346- return cache[reg - CS4270_FIRSTREG];347347-}348348-349349-/**350350- * cs4270_i2c_write - write to a CS4270 register via the I2C bus.351351- * @codec: the codec for this CS4270352352- * @reg: the register to write353353- * @value: the value to write to the register354354- *355355- * This function writes the given value to the given CS4270 register, and356356- * also updates the register cache.357357- *358358- * Note that we don't use the hw_write function pointer of snd_soc_codec.359359- * That's because it's too clunky: the hw_write_t prototype does not match360360- * i2c_smbus_write_byte_data(), and it's just another layer of overhead.361361- */362362-static int cs4270_i2c_write(struct snd_soc_codec *codec, unsigned int reg,363363- unsigned int value)364364-{365365- u8 *cache = codec->reg_cache;366366-367367- if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))368368- return -EIO;369369-370370- /* Only perform an I2C operation if the new value is different */371371- if (cache[reg - CS4270_FIRSTREG] != value) {372372- struct i2c_client *client = codec->control_data;373373- if (i2c_smbus_write_byte_data(client, reg, value)) {374374- dev_err(codec->dev, "i2c write failed\n");375375- return -EIO;376376- }377377-378378- /* We've written to the hardware, so update the cache */379379- cache[reg - CS4270_FIRSTREG] = value;380380- }381381-382382- return 0;383263}384264385265/**···488550static int cs4270_probe(struct snd_soc_codec *codec)489551{490552 struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);491491- int i, ret, reg;553553+ int i, ret;492554493555 codec->control_data = cs4270->control_data;494556495495- /* The I2C interface is set up, so pre-fill our register cache */496496-497497- ret = cs4270_fill_cache(codec);557557+ /* Tell ASoC what kind of I/O to use to read the registers. ASoC will558558+ * then do the I2C transactions itself.559559+ */560560+ ret = snd_soc_codec_set_cache_io(codec, 8, 8, cs4270->control_type);498561 if (ret < 0) {499499- dev_err(codec->dev, "failed to fill register cache\n");562562+ dev_err(codec->dev, "failed to set cache I/O (ret=%i)\n", ret);500563 return ret;501564 }502565···506567 * this feature disabled by default. An application (e.g. alsactl) can507568 * re-enabled it by using the controls.508569 */509509-510510- reg = cs4270_read_reg_cache(codec, CS4270_MUTE);511511- reg &= ~CS4270_MUTE_AUTO;512512- ret = cs4270_i2c_write(codec, CS4270_MUTE, reg);570570+ ret = snd_soc_update_bits(codec, CS4270_MUTE, CS4270_MUTE_AUTO, 0);513571 if (ret < 0) {514572 dev_err(codec->dev, "i2c write failed\n");515573 return ret;···517581 * playback has started. An application (e.g. alsactl) can518582 * re-enabled it by using the controls.519583 */520520-521521- reg = cs4270_read_reg_cache(codec, CS4270_TRANS);522522- reg &= ~(CS4270_TRANS_SOFT | CS4270_TRANS_ZERO);523523- ret = cs4270_i2c_write(codec, CS4270_TRANS, reg);584584+ ret = snd_soc_update_bits(codec, CS4270_TRANS,585585+ CS4270_TRANS_SOFT | CS4270_TRANS_ZERO, 0);524586 if (ret < 0) {525587 dev_err(codec->dev, "i2c write failed\n");526588 return ret;···641707 * Assign this variable to the codec_dev field of the machine driver's642708 * snd_soc_device structure.643709 */644644-static struct snd_soc_codec_driver soc_codec_device_cs4270 = {645645- .probe = cs4270_probe,646646- .remove = cs4270_remove,647647- .suspend = cs4270_soc_suspend,648648- .resume = cs4270_soc_resume,649649- .read = cs4270_read_reg_cache,650650- .write = cs4270_i2c_write,651651- .reg_cache_size = CS4270_NUMREGS,652652- .reg_word_size = sizeof(u8),710710+static const struct snd_soc_codec_driver soc_codec_device_cs4270 = {711711+ .probe = cs4270_probe,712712+ .remove = cs4270_remove,713713+ .suspend = cs4270_soc_suspend,714714+ .resume = cs4270_soc_resume,715715+ .volatile_register = cs4270_reg_is_volatile,716716+ .readable_register = cs4270_reg_is_readable,717717+ .reg_cache_size = CS4270_LASTREG + 1,718718+ .reg_word_size = sizeof(u8),719719+ .reg_cache_default = cs4270_default_reg_cache,653720};654721655722/**
···88 * published by the Free Software Foundation.99 */10101111+#include <linux/clkdev.h>1112#include <linux/device.h>1213#include <linux/firmware.h>1314#include <linux/module.h>14151515-#include <asm/clkdev.h>1616#include <asm/clock.h>17171818#include <cpu/sh7722.h>
+1-1
sound/soc/soc-cache.c
···13611361 goto err;13621362 }13631363 lzo_blocks[i]->sync_bmp = sync_bmp;13641364- lzo_blocks[i]->sync_bmp_nbits = reg_size;13641364+ lzo_blocks[i]->sync_bmp_nbits = bmp_size;13651365 /* alloc the working space for the compressed block */13661366 ret = snd_soc_lzo_prepare(lzo_blocks[i]);13671367 if (ret < 0)