dt-bindings: clk: meson8b-clkc: expose all clock ids

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every meson8b-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-11-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

authored by

Neil Armstrong and committed by

Jerome Brunet 2 years ago 165a1941 6655744d

+97 -108

2 changed files

expand all

drivers

clk

meson

meson8b.h

include

dt-bindings

clock

meson8b-clkc.h

-108

drivers/clk/meson/meson8b.h

··· 78 78 #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ 79 79 80 80 /* 81 - * CLKID index values 82 - * 83 - * These indices are entirely contrived and do not map onto the hardware. 84 - * It has now been decided to expose everything by default in the DT header: 85 - * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want 86 - * to expose, such as the internal muxes and dividers of composite clocks, 87 - * will remain defined here. 88 - */ 89 - 90 - #define CLKID_MPLL0_DIV 96 91 - #define CLKID_MPLL1_DIV 97 92 - #define CLKID_MPLL2_DIV 98 93 - #define CLKID_CPU_IN_SEL 99 94 - #define CLKID_CPU_IN_DIV2 100 95 - #define CLKID_CPU_IN_DIV3 101 96 - #define CLKID_CPU_SCALE_DIV 102 97 - #define CLKID_CPU_SCALE_OUT_SEL 103 98 - #define CLKID_MPLL_PREDIV 104 99 - #define CLKID_FCLK_DIV2_DIV 105 100 - #define CLKID_FCLK_DIV3_DIV 106 101 - #define CLKID_FCLK_DIV4_DIV 107 102 - #define CLKID_FCLK_DIV5_DIV 108 103 - #define CLKID_FCLK_DIV7_DIV 109 104 - #define CLKID_NAND_SEL 110 105 - #define CLKID_NAND_DIV 111 106 - #define CLKID_PLL_FIXED_DCO 113 107 - #define CLKID_HDMI_PLL_DCO 114 108 - #define CLKID_PLL_SYS_DCO 115 109 - #define CLKID_CPU_CLK_DIV2 116 110 - #define CLKID_CPU_CLK_DIV3 117 111 - #define CLKID_CPU_CLK_DIV4 118 112 - #define CLKID_CPU_CLK_DIV5 119 113 - #define CLKID_CPU_CLK_DIV6 120 114 - #define CLKID_CPU_CLK_DIV7 121 115 - #define CLKID_CPU_CLK_DIV8 122 116 - #define CLKID_APB_SEL 123 117 - #define CLKID_PERIPH_SEL 125 118 - #define CLKID_AXI_SEL 127 119 - #define CLKID_L2_DRAM_SEL 129 120 - #define CLKID_HDMI_PLL_LVDS_OUT 131 121 - #define CLKID_VID_PLL_IN_SEL 133 122 - #define CLKID_VID_PLL_IN_EN 134 123 - #define CLKID_VID_PLL_PRE_DIV 135 124 - #define CLKID_VID_PLL_POST_DIV 136 125 - #define CLKID_VCLK_IN_EN 139 126 - #define CLKID_VCLK_DIV1 140 127 - #define CLKID_VCLK_DIV2_DIV 141 128 - #define CLKID_VCLK_DIV2 142 129 - #define CLKID_VCLK_DIV4_DIV 143 130 - #define CLKID_VCLK_DIV4 144 131 - #define CLKID_VCLK_DIV6_DIV 145 132 - #define CLKID_VCLK_DIV6 146 133 - #define CLKID_VCLK_DIV12_DIV 147 134 - #define CLKID_VCLK_DIV12 148 135 - #define CLKID_VCLK2_IN_EN 150 136 - #define CLKID_VCLK2_DIV1 151 137 - #define CLKID_VCLK2_DIV2_DIV 152 138 - #define CLKID_VCLK2_DIV2 153 139 - #define CLKID_VCLK2_DIV4_DIV 154 140 - #define CLKID_VCLK2_DIV4 155 141 - #define CLKID_VCLK2_DIV6_DIV 156 142 - #define CLKID_VCLK2_DIV6 157 143 - #define CLKID_VCLK2_DIV12_DIV 158 144 - #define CLKID_VCLK2_DIV12 159 145 - #define CLKID_CTS_ENCT_SEL 160 146 - #define CLKID_CTS_ENCP_SEL 162 147 - #define CLKID_CTS_ENCI_SEL 164 148 - #define CLKID_HDMI_TX_PIXEL_SEL 166 149 - #define CLKID_CTS_ENCL_SEL 168 150 - #define CLKID_CTS_VDAC0_SEL 170 151 - #define CLKID_HDMI_SYS_SEL 172 152 - #define CLKID_HDMI_SYS_DIV 173 153 - #define CLKID_MALI_0_SEL 175 154 - #define CLKID_MALI_0_DIV 176 155 - #define CLKID_MALI_0 177 156 - #define CLKID_MALI_1_SEL 178 157 - #define CLKID_MALI_1_DIV 179 158 - #define CLKID_MALI_1 180 159 - #define CLKID_GP_PLL_DCO 181 160 - #define CLKID_GP_PLL 182 161 - #define CLKID_VPU_0_SEL 183 162 - #define CLKID_VPU_0_DIV 184 163 - #define CLKID_VPU_0 185 164 - #define CLKID_VPU_1_SEL 186 165 - #define CLKID_VPU_1_DIV 187 166 - #define CLKID_VPU_1 189 167 - #define CLKID_VDEC_1_SEL 191 168 - #define CLKID_VDEC_1_1_DIV 192 169 - #define CLKID_VDEC_1_1 193 170 - #define CLKID_VDEC_1_2_DIV 194 171 - #define CLKID_VDEC_1_2 195 172 - #define CLKID_VDEC_HCODEC_SEL 197 173 - #define CLKID_VDEC_HCODEC_DIV 198 174 - #define CLKID_VDEC_2_SEL 200 175 - #define CLKID_VDEC_2_DIV 201 176 - #define CLKID_VDEC_HEVC_SEL 203 177 - #define CLKID_VDEC_HEVC_DIV 204 178 - #define CLKID_VDEC_HEVC_EN 205 179 - #define CLKID_CTS_AMCLK_SEL 207 180 - #define CLKID_CTS_AMCLK_DIV 208 181 - #define CLKID_CTS_MCLK_I958_SEL 210 182 - #define CLKID_CTS_MCLK_I958_DIV 211 183 - #define CLKID_VCLK_EN 214 184 - #define CLKID_VCLK2_EN 215 185 - #define CLKID_VID_PLL_LVDS_EN 216 186 - #define CLKID_HDMI_PLL_DCO_IN 217 187 - 188 - /* 189 81 * include the CLKID and RESETID that have 190 82 * been made part of the stable DT binding 191 83 */

+97

include/dt-bindings/clock/meson8b-clkc.h

··· 100 100 #define CLKID_MPLL0 93 101 101 #define CLKID_MPLL1 94 102 102 #define CLKID_MPLL2 95 103 + #define CLKID_MPLL0_DIV 96 104 + #define CLKID_MPLL1_DIV 97 105 + #define CLKID_MPLL2_DIV 98 106 + #define CLKID_CPU_IN_SEL 99 107 + #define CLKID_CPU_IN_DIV2 100 108 + #define CLKID_CPU_IN_DIV3 101 109 + #define CLKID_CPU_SCALE_DIV 102 110 + #define CLKID_CPU_SCALE_OUT_SEL 103 111 + #define CLKID_MPLL_PREDIV 104 112 + #define CLKID_FCLK_DIV2_DIV 105 113 + #define CLKID_FCLK_DIV3_DIV 106 114 + #define CLKID_FCLK_DIV4_DIV 107 115 + #define CLKID_FCLK_DIV5_DIV 108 116 + #define CLKID_FCLK_DIV7_DIV 109 117 + #define CLKID_NAND_SEL 110 118 + #define CLKID_NAND_DIV 111 103 119 #define CLKID_NAND_CLK 112 120 + #define CLKID_PLL_FIXED_DCO 113 121 + #define CLKID_HDMI_PLL_DCO 114 122 + #define CLKID_PLL_SYS_DCO 115 123 + #define CLKID_CPU_CLK_DIV2 116 124 + #define CLKID_CPU_CLK_DIV3 117 125 + #define CLKID_CPU_CLK_DIV4 118 126 + #define CLKID_CPU_CLK_DIV5 119 127 + #define CLKID_CPU_CLK_DIV6 120 128 + #define CLKID_CPU_CLK_DIV7 121 129 + #define CLKID_CPU_CLK_DIV8 122 130 + #define CLKID_APB_SEL 123 104 131 #define CLKID_APB 124 132 + #define CLKID_PERIPH_SEL 125 105 133 #define CLKID_PERIPH 126 134 + #define CLKID_AXI_SEL 127 106 135 #define CLKID_AXI 128 107 136 #define CLKID_L2_DRAM 130 137 + #define CLKID_L2_DRAM_SEL 129 138 + #define CLKID_HDMI_PLL_LVDS_OUT 131 108 139 #define CLKID_HDMI_PLL_HDMI_OUT 132 140 + #define CLKID_VID_PLL_IN_SEL 133 141 + #define CLKID_VID_PLL_IN_EN 134 142 + #define CLKID_VID_PLL_PRE_DIV 135 143 + #define CLKID_VID_PLL_POST_DIV 136 109 144 #define CLKID_VID_PLL_FINAL_DIV 137 110 145 #define CLKID_VCLK_IN_SEL 138 146 + #define CLKID_VCLK_IN_EN 139 147 + #define CLKID_VCLK_DIV1 140 148 + #define CLKID_VCLK_DIV2_DIV 141 149 + #define CLKID_VCLK_DIV2 142 150 + #define CLKID_VCLK_DIV4_DIV 143 151 + #define CLKID_VCLK_DIV4 144 152 + #define CLKID_VCLK_DIV6_DIV 145 153 + #define CLKID_VCLK_DIV6 146 154 + #define CLKID_VCLK_DIV12_DIV 147 155 + #define CLKID_VCLK_DIV12 148 111 156 #define CLKID_VCLK2_IN_SEL 149 157 + #define CLKID_VCLK2_IN_EN 150 158 + #define CLKID_VCLK2_DIV1 151 159 + #define CLKID_VCLK2_DIV2_DIV 152 160 + #define CLKID_VCLK2_DIV2 153 161 + #define CLKID_VCLK2_DIV4_DIV 154 162 + #define CLKID_VCLK2_DIV4 155 163 + #define CLKID_VCLK2_DIV6_DIV 156 164 + #define CLKID_VCLK2_DIV6 157 165 + #define CLKID_VCLK2_DIV12_DIV 158 166 + #define CLKID_VCLK2_DIV12 159 167 + #define CLKID_CTS_ENCT_SEL 160 112 168 #define CLKID_CTS_ENCT 161 169 + #define CLKID_CTS_ENCP_SEL 162 113 170 #define CLKID_CTS_ENCP 163 171 + #define CLKID_CTS_ENCI_SEL 164 114 172 #define CLKID_CTS_ENCI 165 173 + #define CLKID_HDMI_TX_PIXEL_SEL 166 115 174 #define CLKID_HDMI_TX_PIXEL 167 175 + #define CLKID_CTS_ENCL_SEL 168 116 176 #define CLKID_CTS_ENCL 169 177 + #define CLKID_CTS_VDAC0_SEL 170 117 178 #define CLKID_CTS_VDAC0 171 179 + #define CLKID_HDMI_SYS_SEL 172 180 + #define CLKID_HDMI_SYS_DIV 173 118 181 #define CLKID_HDMI_SYS 174 182 + #define CLKID_MALI_0_SEL 175 183 + #define CLKID_MALI_0_DIV 176 184 + #define CLKID_MALI_0 177 185 + #define CLKID_MALI_1_SEL 178 186 + #define CLKID_MALI_1_DIV 179 187 + #define CLKID_MALI_1 180 188 + #define CLKID_GP_PLL_DCO 181 189 + #define CLKID_GP_PLL 182 190 + #define CLKID_VPU_0_SEL 183 191 + #define CLKID_VPU_0_DIV 184 192 + #define CLKID_VPU_0 185 193 + #define CLKID_VPU_1_SEL 186 194 + #define CLKID_VPU_1_DIV 187 195 + #define CLKID_VPU_1 189 119 196 #define CLKID_VPU 190 197 + #define CLKID_VDEC_1_SEL 191 198 + #define CLKID_VDEC_1_1_DIV 192 199 + #define CLKID_VDEC_1_1 193 200 + #define CLKID_VDEC_1_2_DIV 194 201 + #define CLKID_VDEC_1_2 195 120 202 #define CLKID_VDEC_1 196 203 + #define CLKID_VDEC_HCODEC_SEL 197 204 + #define CLKID_VDEC_HCODEC_DIV 198 121 205 #define CLKID_VDEC_HCODEC 199 206 + #define CLKID_VDEC_2_SEL 200 207 + #define CLKID_VDEC_2_DIV 201 122 208 #define CLKID_VDEC_2 202 209 + #define CLKID_VDEC_HEVC_SEL 203 210 + #define CLKID_VDEC_HEVC_DIV 204 211 + #define CLKID_VDEC_HEVC_EN 205 123 212 #define CLKID_VDEC_HEVC 206 213 + #define CLKID_CTS_AMCLK_SEL 207 214 + #define CLKID_CTS_AMCLK_DIV 208 124 215 #define CLKID_CTS_AMCLK 209 216 + #define CLKID_CTS_MCLK_I958_SEL 210 217 + #define CLKID_CTS_MCLK_I958_DIV 211 125 218 #define CLKID_CTS_MCLK_I958 212 126 219 #define CLKID_CTS_I958 213 220 + #define CLKID_VCLK_EN 214 221 + #define CLKID_VCLK2_EN 215 222 + #define CLKID_VID_PLL_LVDS_EN 216 223 + #define CLKID_HDMI_PLL_DCO_IN 217 127 224 128 225 #endif /* __MESON8B_CLKC_H */