tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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net: ethernet: mtk_wed: add wed 3.0 reset support

Introduce support for resetting Wireless Ethernet Dispatcher 3.0
available on MT988 SoC.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

authored by

Sujuan Chen and committed by
Paolo Abeni 1543b8ff 3f3de094

+339 -10
+279 -10
drivers/net/ethernet/mediatek/mtk_wed.c
··· 149 149 return wdma_r32(dev, MTK_WDMA_GLO_CFG); 150 150 } 151 151 152 + static void 153 + mtk_wdma_v3_rx_reset(struct mtk_wed_device *dev) 154 + { 155 + u32 status; 156 + 157 + if (!mtk_wed_is_v3_or_greater(dev->hw)) 158 + return; 159 + 160 + wdma_clr(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN); 161 + wdma_clr(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN); 162 + 163 + if (read_poll_timeout(wdma_r32, status, 164 + !(status & MTK_WDMA_PREF_TX_CFG_PREF_BUSY), 165 + 0, 10000, false, dev, MTK_WDMA_PREF_TX_CFG)) 166 + dev_err(dev->hw->dev, "rx reset failed\n"); 167 + 168 + if (read_poll_timeout(wdma_r32, status, 169 + !(status & MTK_WDMA_PREF_RX_CFG_PREF_BUSY), 170 + 0, 10000, false, dev, MTK_WDMA_PREF_RX_CFG)) 171 + dev_err(dev->hw->dev, "rx reset failed\n"); 172 + 173 + wdma_clr(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN); 174 + wdma_clr(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN); 175 + 176 + if (read_poll_timeout(wdma_r32, status, 177 + !(status & MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY), 178 + 0, 10000, false, dev, MTK_WDMA_WRBK_TX_CFG)) 179 + dev_err(dev->hw->dev, "rx reset failed\n"); 180 + 181 + if (read_poll_timeout(wdma_r32, status, 182 + !(status & MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY), 183 + 0, 10000, false, dev, MTK_WDMA_WRBK_RX_CFG)) 184 + dev_err(dev->hw->dev, "rx reset failed\n"); 185 + 186 + /* prefetch FIFO */ 187 + wdma_w32(dev, MTK_WDMA_PREF_RX_FIFO_CFG, 188 + MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR | 189 + MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR); 190 + wdma_clr(dev, MTK_WDMA_PREF_RX_FIFO_CFG, 191 + MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR | 192 + MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR); 193 + 194 + /* core FIFO */ 195 + wdma_w32(dev, MTK_WDMA_XDMA_RX_FIFO_CFG, 196 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR | 197 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR | 198 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR | 199 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR | 200 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR | 201 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR | 202 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR); 203 + wdma_clr(dev, MTK_WDMA_XDMA_RX_FIFO_CFG, 204 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR | 205 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR | 206 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR | 207 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR | 208 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR | 209 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR | 210 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR); 211 + 212 + /* writeback FIFO */ 213 + wdma_w32(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(0), 214 + MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR); 215 + wdma_w32(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(1), 216 + MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR); 217 + 218 + wdma_clr(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(0), 219 + MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR); 220 + wdma_clr(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(1), 221 + MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR); 222 + 223 + /* prefetch ring status */ 224 + wdma_w32(dev, MTK_WDMA_PREF_SIDX_CFG, 225 + MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR); 226 + wdma_clr(dev, MTK_WDMA_PREF_SIDX_CFG, 227 + MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR); 228 + 229 + /* writeback ring status */ 230 + wdma_w32(dev, MTK_WDMA_WRBK_SIDX_CFG, 231 + MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR); 232 + wdma_clr(dev, MTK_WDMA_WRBK_SIDX_CFG, 233 + MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR); 234 + } 235 + 152 236 static int 153 237 mtk_wdma_rx_reset(struct mtk_wed_device *dev) 154 238 { ··· 245 161 if (ret) 246 162 dev_err(dev->hw->dev, "rx reset failed\n"); 247 163 164 + mtk_wdma_v3_rx_reset(dev); 248 165 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX); 249 166 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0); 250 167 ··· 278 193 } 279 194 280 195 static void 196 + mtk_wdma_v3_tx_reset(struct mtk_wed_device *dev) 197 + { 198 + u32 status; 199 + 200 + if (!mtk_wed_is_v3_or_greater(dev->hw)) 201 + return; 202 + 203 + wdma_clr(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN); 204 + wdma_clr(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN); 205 + 206 + if (read_poll_timeout(wdma_r32, status, 207 + !(status & MTK_WDMA_PREF_TX_CFG_PREF_BUSY), 208 + 0, 10000, false, dev, MTK_WDMA_PREF_TX_CFG)) 209 + dev_err(dev->hw->dev, "tx reset failed\n"); 210 + 211 + if (read_poll_timeout(wdma_r32, status, 212 + !(status & MTK_WDMA_PREF_RX_CFG_PREF_BUSY), 213 + 0, 10000, false, dev, MTK_WDMA_PREF_RX_CFG)) 214 + dev_err(dev->hw->dev, "tx reset failed\n"); 215 + 216 + wdma_clr(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN); 217 + wdma_clr(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN); 218 + 219 + if (read_poll_timeout(wdma_r32, status, 220 + !(status & MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY), 221 + 0, 10000, false, dev, MTK_WDMA_WRBK_TX_CFG)) 222 + dev_err(dev->hw->dev, "tx reset failed\n"); 223 + 224 + if (read_poll_timeout(wdma_r32, status, 225 + !(status & MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY), 226 + 0, 10000, false, dev, MTK_WDMA_WRBK_RX_CFG)) 227 + dev_err(dev->hw->dev, "tx reset failed\n"); 228 + 229 + /* prefetch FIFO */ 230 + wdma_w32(dev, MTK_WDMA_PREF_TX_FIFO_CFG, 231 + MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR | 232 + MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR); 233 + wdma_clr(dev, MTK_WDMA_PREF_TX_FIFO_CFG, 234 + MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR | 235 + MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR); 236 + 237 + /* core FIFO */ 238 + wdma_w32(dev, MTK_WDMA_XDMA_TX_FIFO_CFG, 239 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR | 240 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR | 241 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR | 242 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR); 243 + wdma_clr(dev, MTK_WDMA_XDMA_TX_FIFO_CFG, 244 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR | 245 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR | 246 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR | 247 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR); 248 + 249 + /* writeback FIFO */ 250 + wdma_w32(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(0), 251 + MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR); 252 + wdma_w32(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(1), 253 + MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR); 254 + 255 + wdma_clr(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(0), 256 + MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR); 257 + wdma_clr(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(1), 258 + MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR); 259 + 260 + /* prefetch ring status */ 261 + wdma_w32(dev, MTK_WDMA_PREF_SIDX_CFG, 262 + MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR); 263 + wdma_clr(dev, MTK_WDMA_PREF_SIDX_CFG, 264 + MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR); 265 + 266 + /* writeback ring status */ 267 + wdma_w32(dev, MTK_WDMA_WRBK_SIDX_CFG, 268 + MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR); 269 + wdma_clr(dev, MTK_WDMA_WRBK_SIDX_CFG, 270 + MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR); 271 + } 272 + 273 + static void 281 274 mtk_wdma_tx_reset(struct mtk_wed_device *dev) 282 275 { 283 276 u32 status, mask = MTK_WDMA_GLO_CFG_TX_DMA_BUSY; ··· 366 203 !(status & mask), 0, 10000)) 367 204 dev_err(dev->hw->dev, "tx reset failed\n"); 368 205 206 + mtk_wdma_v3_tx_reset(dev); 369 207 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX); 370 208 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0); 371 209 ··· 1570 1406 if (ret) 1571 1407 return ret; 1572 1408 1409 + if (dev->wlan.hw_rro) { 1410 + wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_IND_CMD_EN); 1411 + mtk_wed_poll_busy(dev, MTK_WED_RRO_RX_HW_STS, 1412 + MTK_WED_RX_IND_CMD_BUSY); 1413 + mtk_wed_reset(dev, MTK_WED_RESET_RRO_RX_TO_PG); 1414 + } 1415 + 1573 1416 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RX_DRV_EN); 1574 1417 ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, 1575 1418 MTK_WED_WPDMA_RX_D_RX_DRV_BUSY); 1419 + if (!ret && mtk_wed_is_v3_or_greater(dev->hw)) 1420 + ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_PREF_CFG, 1421 + MTK_WED_WPDMA_RX_D_PREF_BUSY); 1576 1422 if (ret) { 1577 1423 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT); 1578 1424 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_D_DRV); 1579 1425 } else { 1426 + if (mtk_wed_is_v3_or_greater(dev->hw)) { 1427 + /* 1.a. disable prefetch HW */ 1428 + wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_CFG, 1429 + MTK_WED_WPDMA_RX_D_PREF_EN); 1430 + mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_PREF_CFG, 1431 + MTK_WED_WPDMA_RX_D_PREF_BUSY); 1432 + wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 1433 + MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL); 1434 + } 1435 + 1580 1436 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 1581 1437 MTK_WED_WPDMA_RX_D_RST_CRX_IDX | 1582 1438 MTK_WED_WPDMA_RX_D_RST_DRV_IDX); ··· 1624 1440 wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0); 1625 1441 } 1626 1442 1443 + if (dev->wlan.hw_rro) { 1444 + /* disable rro msdu page drv */ 1445 + wed_clr(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG, 1446 + MTK_WED_RRO_MSDU_PG_DRV_EN); 1447 + 1448 + /* disable rro data drv */ 1449 + wed_clr(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_RX_D_DRV_EN); 1450 + 1451 + /* rro msdu page drv reset */ 1452 + wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG, 1453 + MTK_WED_RRO_MSDU_PG_DRV_CLR); 1454 + mtk_wed_poll_busy(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG, 1455 + MTK_WED_RRO_MSDU_PG_DRV_CLR); 1456 + 1457 + /* rro data drv reset */ 1458 + wed_w32(dev, MTK_WED_RRO_RX_D_CFG(2), 1459 + MTK_WED_RRO_RX_D_DRV_CLR); 1460 + mtk_wed_poll_busy(dev, MTK_WED_RRO_RX_D_CFG(2), 1461 + MTK_WED_RRO_RX_D_DRV_CLR); 1462 + } 1463 + 1627 1464 /* reset route qm */ 1628 1465 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN); 1629 1466 ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL, 1630 1467 MTK_WED_CTRL_RX_ROUTE_QM_BUSY); 1631 - if (ret) 1468 + if (ret) { 1632 1469 mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM); 1633 - else 1634 - wed_set(dev, MTK_WED_RTQM_GLO_CFG, 1635 - MTK_WED_RTQM_Q_RST); 1470 + } else if (mtk_wed_is_v3_or_greater(dev->hw)) { 1471 + wed_set(dev, MTK_WED_RTQM_RST, BIT(0)); 1472 + wed_clr(dev, MTK_WED_RTQM_RST, BIT(0)); 1473 + mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM); 1474 + } else { 1475 + wed_set(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST); 1476 + } 1636 1477 1637 1478 /* reset tx wdma */ 1638 1479 mtk_wdma_tx_reset(dev); 1639 1480 1640 1481 /* reset tx wdma drv */ 1641 1482 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_TX_DRV_EN); 1642 - mtk_wed_poll_busy(dev, MTK_WED_CTRL, 1643 - MTK_WED_CTRL_WDMA_INT_AGENT_BUSY); 1483 + if (mtk_wed_is_v3_or_greater(dev->hw)) 1484 + mtk_wed_poll_busy(dev, MTK_WED_WPDMA_STATUS, 1485 + MTK_WED_WPDMA_STATUS_TX_DRV); 1486 + else 1487 + mtk_wed_poll_busy(dev, MTK_WED_CTRL, 1488 + MTK_WED_CTRL_WDMA_INT_AGENT_BUSY); 1644 1489 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV); 1645 1490 1646 1491 /* reset wed rx dma */ ··· 1690 1477 MTK_WED_CTRL_WED_RX_BM_BUSY); 1691 1478 mtk_wed_reset(dev, MTK_WED_RESET_RX_BM); 1692 1479 1480 + if (dev->wlan.hw_rro) { 1481 + wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_PG_BM_EN); 1482 + mtk_wed_poll_busy(dev, MTK_WED_CTRL, 1483 + MTK_WED_CTRL_WED_RX_PG_BM_BUSY); 1484 + wed_set(dev, MTK_WED_RESET, MTK_WED_RESET_RX_PG_BM); 1485 + wed_clr(dev, MTK_WED_RESET, MTK_WED_RESET_RX_PG_BM); 1486 + } 1487 + 1693 1488 /* wo change to enable state */ 1694 1489 val = MTK_WED_WO_STATE_ENABLE; 1695 1490 ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO, ··· 1715 1494 false); 1716 1495 } 1717 1496 mtk_wed_free_rx_buffer(dev); 1497 + mtk_wed_hwrro_free_buffer(dev); 1718 1498 1719 1499 return 0; 1720 1500 } ··· 1749 1527 1750 1528 /* 2. reset WDMA rx DMA */ 1751 1529 busy = !!mtk_wdma_rx_reset(dev); 1752 - wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); 1530 + if (mtk_wed_is_v3_or_greater(dev->hw)) { 1531 + val = MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE | 1532 + wed_r32(dev, MTK_WED_WDMA_GLO_CFG); 1533 + val &= ~MTK_WED_WDMA_GLO_CFG_RX_DRV_EN; 1534 + wed_w32(dev, MTK_WED_WDMA_GLO_CFG, val); 1535 + } else { 1536 + wed_clr(dev, MTK_WED_WDMA_GLO_CFG, 1537 + MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); 1538 + } 1539 + 1753 1540 if (!busy) 1754 1541 busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_GLO_CFG, 1755 1542 MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY); 1543 + if (!busy && mtk_wed_is_v3_or_greater(dev->hw)) 1544 + busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_RX_PREF_CFG, 1545 + MTK_WED_WDMA_RX_PREF_BUSY); 1756 1546 1757 1547 if (busy) { 1758 1548 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT); 1759 1549 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV); 1760 1550 } else { 1551 + if (mtk_wed_is_v3_or_greater(dev->hw)) { 1552 + /* 1.a. disable prefetch HW */ 1553 + wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG, 1554 + MTK_WED_WDMA_RX_PREF_EN); 1555 + mtk_wed_poll_busy(dev, MTK_WED_WDMA_RX_PREF_CFG, 1556 + MTK_WED_WDMA_RX_PREF_BUSY); 1557 + wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG, 1558 + MTK_WED_WDMA_RX_PREF_DDONE2_EN); 1559 + 1560 + /* 2. Reset dma index */ 1561 + wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 1562 + MTK_WED_WDMA_RESET_IDX_RX_ALL); 1563 + } 1564 + 1761 1565 wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 1762 1566 MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV); 1763 1567 wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0); ··· 1799 1551 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); 1800 1552 1801 1553 for (i = 0; i < 100; i++) { 1802 - val = wed_r32(dev, MTK_WED_TX_BM_INTF); 1803 - if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40) 1554 + if (mtk_wed_is_v1(dev->hw)) 1555 + val = FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, 1556 + wed_r32(dev, MTK_WED_TX_BM_INTF)); 1557 + else 1558 + val = FIELD_GET(MTK_WED_TX_TKID_INTF_TKFIFO_FDEP, 1559 + wed_r32(dev, MTK_WED_TX_TKID_INTF)); 1560 + if (val == 0x40) 1804 1561 break; 1805 1562 } 1806 1563 ··· 1827 1574 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT); 1828 1575 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV); 1829 1576 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV); 1577 + if (mtk_wed_is_v3_or_greater(dev->hw)) 1578 + wed_w32(dev, MTK_WED_RX1_CTRL2, 0); 1830 1579 } else { 1831 1580 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 1832 1581 MTK_WED_WPDMA_RESET_IDX_TX | ··· 1845 1590 wed_w32(dev, MTK_WED_RESET_IDX, 0); 1846 1591 } 1847 1592 1848 - mtk_wed_rx_reset(dev); 1593 + if (mtk_wed_is_v3_or_greater(dev->hw)) { 1594 + /* reset amsdu engine */ 1595 + wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN); 1596 + mtk_wed_reset(dev, MTK_WED_RESET_TX_AMSDU); 1597 + } 1598 + 1599 + if (mtk_wed_get_rx_capa(dev)) 1600 + mtk_wed_rx_reset(dev); 1849 1601 } 1850 1602 1851 1603 static int ··· 2104 1842 MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4); 2105 1843 2106 1844 wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN); 1845 + wdma_set(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN); 2107 1846 } 2108 1847 2109 1848 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, ··· 2167 1904 2168 1905 if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro) 2169 1906 return; 1907 + 1908 + if (reset) { 1909 + wed_set(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG, 1910 + MTK_WED_RRO_MSDU_PG_DRV_EN); 1911 + return; 1912 + } 2170 1913 2171 1914 wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_MSDU_PG_DRV_CLR); 2172 1915 wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
+60
drivers/net/ethernet/mediatek/mtk_wed_regs.h
··· 28 28 #define MTK_WED_RESET 0x008 29 29 #define MTK_WED_RESET_TX_BM BIT(0) 30 30 #define MTK_WED_RESET_RX_BM BIT(1) 31 + #define MTK_WED_RESET_RX_PG_BM BIT(2) 32 + #define MTK_WED_RESET_RRO_RX_TO_PG BIT(3) 31 33 #define MTK_WED_RESET_TX_FREE_AGENT BIT(4) 32 34 #define MTK_WED_RESET_WPDMA_TX_DRV BIT(8) 33 35 #define MTK_WED_RESET_WPDMA_RX_DRV BIT(9) ··· 108 106 #define MTK_WED_STATUS 0x060 109 107 #define MTK_WED_STATUS_TX GENMASK(15, 8) 110 108 109 + #define MTK_WED_WPDMA_STATUS 0x068 110 + #define MTK_WED_WPDMA_STATUS_TX_DRV GENMASK(15, 8) 111 + 111 112 #define MTK_WED_TX_BM_CTRL 0x080 112 113 #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0) 113 114 #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16) ··· 144 139 #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0) 145 140 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16) 146 141 #define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28) 142 + 143 + #define MTK_WED_TX_TKID_INTF 0x0dc 144 + #define MTK_WED_TX_TKID_INTF_TKFIFO_FDEP GENMASK(25, 16) 147 145 148 146 #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3 GENMASK(7, 0) 149 147 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3 GENMASK(23, 16) ··· 198 190 #define MTK_WED_RING_RX_DATA(_n) (0x420 + (_n) * 0x10) 199 191 200 192 #define MTK_WED_SCR0 0x3c0 193 + #define MTK_WED_RX1_CTRL2 0x418 201 194 #define MTK_WED_WPDMA_INT_TRIGGER 0x504 202 195 #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1) 203 196 #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE GENMASK(5, 4) ··· 312 303 313 304 #define MTK_WED_WPDMA_RX_D_RST_IDX 0x760 314 305 #define MTK_WED_WPDMA_RX_D_RST_CRX_IDX GENMASK(17, 16) 306 + #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL BIT(20) 315 307 #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX GENMASK(25, 24) 316 308 317 309 #define MTK_WED_WPDMA_RX_GLO_CFG 0x76c ··· 323 313 324 314 #define MTK_WED_WPDMA_RX_D_PREF_CFG 0x7b4 325 315 #define MTK_WED_WPDMA_RX_D_PREF_EN BIT(0) 316 + #define MTK_WED_WPDMA_RX_D_PREF_BUSY BIT(1) 326 317 #define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE GENMASK(12, 8) 327 318 #define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES GENMASK(21, 16) 328 319 ··· 345 334 346 335 #define MTK_WED_WDMA_RX_PREF_CFG 0x950 347 336 #define MTK_WED_WDMA_RX_PREF_EN BIT(0) 337 + #define MTK_WED_WDMA_RX_PREF_BUSY BIT(1) 348 338 #define MTK_WED_WDMA_RX_PREF_BURST_SIZE GENMASK(12, 8) 349 339 #define MTK_WED_WDMA_RX_PREF_LOW_THRES GENMASK(21, 16) 350 340 #define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR BIT(24) 351 341 #define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR BIT(25) 352 342 #define MTK_WED_WDMA_RX_PREF_DDONE2_EN BIT(26) 343 + #define MTK_WED_WDMA_RX_PREF_DDONE2_BUSY BIT(27) 353 344 354 345 #define MTK_WED_WDMA_RX_PREF_FIFO_CFG 0x95C 355 346 #define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR BIT(0) ··· 380 367 381 368 #define MTK_WED_WDMA_RESET_IDX 0xa08 382 369 #define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16) 370 + #define MTK_WED_WDMA_RESET_IDX_RX_ALL BIT(20) 383 371 #define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24) 384 372 385 373 #define MTK_WED_WDMA_INT_CLR 0xa24 ··· 451 437 #define MTK_WDMA_INT_MASK_RX_DELAY BIT(30) 452 438 #define MTK_WDMA_INT_MASK_RX_COHERENT BIT(31) 453 439 440 + #define MTK_WDMA_XDMA_TX_FIFO_CFG 0x238 441 + #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR BIT(0) 442 + #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR BIT(4) 443 + #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR BIT(8) 444 + #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR BIT(12) 445 + 446 + #define MTK_WDMA_XDMA_RX_FIFO_CFG 0x23c 447 + #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR BIT(0) 448 + #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR BIT(4) 449 + #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR BIT(8) 450 + #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR BIT(12) 451 + #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR BIT(15) 452 + #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR BIT(18) 453 + #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR BIT(21) 454 + 454 455 #define MTK_WDMA_INT_GRP1 0x250 455 456 #define MTK_WDMA_INT_GRP2 0x254 456 457 457 458 #define MTK_WDMA_PREF_TX_CFG 0x2d0 458 459 #define MTK_WDMA_PREF_TX_CFG_PREF_EN BIT(0) 460 + #define MTK_WDMA_PREF_TX_CFG_PREF_BUSY BIT(1) 459 461 460 462 #define MTK_WDMA_PREF_RX_CFG 0x2dc 461 463 #define MTK_WDMA_PREF_RX_CFG_PREF_EN BIT(0) 464 + #define MTK_WDMA_PREF_RX_CFG_PREF_BUSY BIT(1) 465 + 466 + #define MTK_WDMA_PREF_RX_FIFO_CFG 0x2e0 467 + #define MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR BIT(0) 468 + #define MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR BIT(16) 469 + 470 + #define MTK_WDMA_PREF_TX_FIFO_CFG 0x2d4 471 + #define MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR BIT(0) 472 + #define MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR BIT(16) 473 + 474 + #define MTK_WDMA_PREF_SIDX_CFG 0x2e4 475 + #define MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0) 476 + #define MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR GENMASK(5, 4) 462 477 463 478 #define MTK_WDMA_WRBK_TX_CFG 0x300 479 + #define MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY BIT(0) 464 480 #define MTK_WDMA_WRBK_TX_CFG_WRBK_EN BIT(30) 465 481 482 + #define MTK_WDMA_WRBK_TX_FIFO_CFG(_n) (0x304 + (_n) * 0x4) 483 + #define MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR BIT(0) 484 + 466 485 #define MTK_WDMA_WRBK_RX_CFG 0x344 486 + #define MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY BIT(0) 467 487 #define MTK_WDMA_WRBK_RX_CFG_WRBK_EN BIT(30) 488 + 489 + #define MTK_WDMA_WRBK_RX_FIFO_CFG(_n) (0x348 + (_n) * 0x4) 490 + #define MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR BIT(0) 491 + 492 + #define MTK_WDMA_WRBK_SIDX_CFG 0x388 493 + #define MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0) 494 + #define MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR GENMASK(5, 4) 468 495 469 496 #define MTK_PCIE_MIRROR_MAP(n) ((n) ? 0x4 : 0x0) 470 497 #define MTK_PCIE_MIRROR_MAP_EN BIT(0) ··· 519 464 #define MTK_WED_RTQM_Q_RST BIT(2) 520 465 #define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5) 521 466 #define MTK_WED_RTQM_TXDMAD_FPORT GENMASK(23, 20) 467 + 468 + #define MTK_WED_RTQM_RST 0xb04 522 469 523 470 #define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT 0xb1c 524 471 #define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n) (0xb20 + (_n) * 0x4) ··· 709 652 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN BIT(16) 710 653 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR BIT(17) 711 654 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG GENMASK(22, 18) 655 + 656 + #define MTK_WED_RRO_RX_HW_STS 0xf00 657 + #define MTK_WED_RX_IND_CMD_BUSY GENMASK(31, 0) 712 658 713 659 #define MTK_WED_RX_IND_CMD_CNT0 0xf20 714 660 #define MTK_WED_RX_IND_CMD_DBG_CNT_EN BIT(31)