phy: qcom-qmp: move QSERDES V5 registers to separate headers

+65

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_ 7 + #define QCOM_PHY_QMP_QSERDES_COM_V5_H_ 8 + 9 + /* Only for QMP V5 PHY - QSERDES COM registers */ 10 + #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 11 + #define QSERDES_V5_COM_SSC_PER1 0x01c 12 + #define QSERDES_V5_COM_SSC_PER2 0x020 13 + #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 14 + #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 15 + #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 16 + #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 17 + #define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 18 + #define QSERDES_V5_COM_CLK_ENABLE1 0x048 19 + #define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 20 + #define QSERDES_V5_COM_PLL_IVCO 0x058 21 + #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 22 + #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 23 + #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 24 + #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 25 + #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 26 + #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 27 + #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 28 + #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 29 + #define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 30 + #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 31 + #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 32 + #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 33 + #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 34 + #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 35 + #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 36 + #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc 37 + #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 38 + #define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 39 + #define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 40 + #define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc 41 + #define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 42 + #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 43 + #define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 44 + #define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 45 + #define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 46 + #define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c 47 + #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 48 + #define QSERDES_V5_COM_CLK_SELECT 0x154 49 + #define QSERDES_V5_COM_HSCLK_SEL 0x158 50 + #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 51 + #define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 52 + #define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c 53 + #define QSERDES_V5_COM_CORE_CLK_EN 0x174 54 + #define QSERDES_V5_COM_CMN_CONFIG 0x17c 55 + #define QSERDES_V5_COM_CMN_MISC1 0x19c 56 + #define QSERDES_V5_COM_CMN_MODE 0x1a0 57 + #define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 58 + #define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 59 + #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 60 + #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 61 + #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 62 + #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 63 + #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 64 + 65 + #endif

+84

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h

··· 1 + 2 + /* SPDX-License-Identifier: GPL-2.0 */ 3 + /* 4 + * Copyright (c) 2017, The Linux Foundation. All rights reserved. 5 + */ 6 + 7 + #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ 8 + #define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ 9 + 10 + /* Only for QMP V5 PHY - TX registers */ 11 + #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034 12 + #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038 13 + #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c 14 + #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040 15 + #define QSERDES_V5_TX_LANE_MODE_1 0x084 16 + #define QSERDES_V5_TX_LANE_MODE_2 0x088 17 + #define QSERDES_V5_TX_LANE_MODE_3 0x08c 18 + #define QSERDES_V5_TX_LANE_MODE_4 0x090 19 + #define QSERDES_V5_TX_LANE_MODE_5 0x094 20 + #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4 21 + #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0 22 + #define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4 23 + #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 24 + #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 25 + #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 26 + #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 27 + 28 + /* Only for QMP V5 PHY - RX registers */ 29 + #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 30 + #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 31 + #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 32 + #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 33 + #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 34 + #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 35 + #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 36 + #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 37 + #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 38 + #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 39 + #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 40 + #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 41 + #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 42 + #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 43 + #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 44 + #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 45 + #define QSERDES_V5_RX_RX_TERM_BW 0x080 46 + #define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc 47 + #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 48 + #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 49 + #define QSERDES_V5_RX_GM_CAL 0x0dc 50 + #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 51 + #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 52 + #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 53 + #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 54 + #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 55 + #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 56 + #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 57 + #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 58 + #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 59 + #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 60 + #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 61 + #define QSERDES_V5_RX_SIGDET_LVL 0x120 62 + #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 63 + #define QSERDES_V5_RX_RX_BAND 0x128 64 + #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 65 + #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 66 + #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 67 + #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 68 + #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 69 + #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 70 + #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 71 + #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 72 + #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 73 + #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 74 + #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 75 + #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 76 + #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 77 + #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 78 + #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 79 + #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 80 + #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 81 + #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 82 + #define QSERDES_V5_RX_VTH_CODE 0x1b0 83 + 84 + #endif

+3 -130

drivers/phy/qualcomm/phy-qcom-qmp.h

··· 15 15 #include "phy-qcom-qmp-qserdes-com-v4.h" 16 16 #include "phy-qcom-qmp-qserdes-txrx-v4.h" 17 17 18 + #include "phy-qcom-qmp-qserdes-com-v5.h" 19 + #include "phy-qcom-qmp-qserdes-txrx-v5.h" 20 + 18 21 /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 19 22 20 23 #define QSERDES_PLL_BG_TIMER 0x00c ··· 615 612 #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 616 613 #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 617 614 618 - /* Only for QMP V5 PHY - QSERDES COM registers */ 619 - #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 620 - #define QSERDES_V5_COM_SSC_PER1 0x01c 621 - #define QSERDES_V5_COM_SSC_PER2 0x020 622 - #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 623 - #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 624 - #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 625 - #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 626 - #define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 627 - #define QSERDES_V5_COM_CLK_ENABLE1 0x048 628 - #define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 629 - #define QSERDES_V5_COM_PLL_IVCO 0x058 630 - #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 631 - #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 632 - #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 633 - #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 634 - #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 635 - #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 636 - #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 637 - #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 638 - #define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 639 - #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 640 - #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 641 - #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 642 - #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 643 - #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 644 - #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 645 - #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc 646 - #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 647 - #define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 648 - #define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 649 - #define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc 650 - #define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 651 - #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 652 - #define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 653 - #define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 654 - #define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 655 - #define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c 656 - #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 657 - #define QSERDES_V5_COM_CLK_SELECT 0x154 658 - #define QSERDES_V5_COM_HSCLK_SEL 0x158 659 - #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 660 - #define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 661 - #define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c 662 - #define QSERDES_V5_COM_CORE_CLK_EN 0x174 663 - #define QSERDES_V5_COM_CMN_CONFIG 0x17c 664 - #define QSERDES_V5_COM_CMN_MISC1 0x19c 665 - #define QSERDES_V5_COM_CMN_MODE 0x1a0 666 - #define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 667 - #define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 668 - #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 669 - #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 670 - #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 671 - #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 672 - #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 673 - 674 - /* Only for QMP V5 PHY - TX registers */ 675 - #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 676 - #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 677 - #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 678 - #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 679 - #define QSERDES_V5_TX_LANE_MODE_1 0x84 680 - #define QSERDES_V5_TX_LANE_MODE_2 0x88 681 - #define QSERDES_V5_TX_LANE_MODE_3 0x8c 682 - #define QSERDES_V5_TX_LANE_MODE_4 0x90 683 - #define QSERDES_V5_TX_LANE_MODE_5 0x94 684 - #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 685 - #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 686 - #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 687 - #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 688 - #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 689 - #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 690 - #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 691 - 692 615 /* Only for QMP V5_20 PHY - TX registers */ 693 616 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 694 617 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 695 618 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 696 619 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 697 - 698 - /* Only for QMP V5 PHY - RX registers */ 699 - #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 700 - #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 701 - #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 702 - #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 703 - #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 704 - #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 705 - #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 706 - #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 707 - #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 708 - #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 709 - #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 710 - #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 711 - #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 712 - #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 713 - #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 714 - #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 715 - #define QSERDES_V5_RX_RX_TERM_BW 0x080 716 - #define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc 717 - #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 718 - #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 719 - #define QSERDES_V5_RX_GM_CAL 0x0dc 720 - #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 721 - #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 722 - #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 723 - #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 724 - #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 725 - #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 726 - #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 727 - #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 728 - #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 729 - #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 730 - #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 731 - #define QSERDES_V5_RX_SIGDET_LVL 0x120 732 - #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 733 - #define QSERDES_V5_RX_RX_BAND 0x128 734 - #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 735 - #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 736 - #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 737 - #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 738 - #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 739 - #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 740 - #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 741 - #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 742 - #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 743 - #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 744 - #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 745 - #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 746 - #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 747 - #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 748 - #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 749 - #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 750 - #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 751 - #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 752 - #define QSERDES_V5_RX_VTH_CODE 0x1b0 753 620 754 621 /* Only for QMP V5_20 PHY - RX registers */ 755 622 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008