Merge tag 'samsung-dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Merge "Samsung 3rd DT updates for v3.20" from Kukjin Kim:

- add DISP1 power domain for support HDMI support on exynos5420/5422/5800
and the power domain node including FIMD1, MIXER and HDMI modules
(tested on exynos5420 Peach Pit and exynos5800 Peach Pi Chromebooks
and exynos5422 Odroid XU3 by Javier Martinez Canillas)

Note this is including a patch for adding clock IDs for the DISP1 power
domain with Mike and Sylwester's acks so that could be handled together
to avoid non-working.

* tag 'samsung-dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Add DISP1 power domain for exynos5420
clk: exynos5420: Add IDs for clocks used in DISP1 power domain

Signed-off-by: Olof Johansson <olof@lixom.net>

Olof Johansson 11 years ago 1215c3e6 a35306d3

+35 -11

3 changed files

expand all

arch

arm

boot

dts

exynos5420.dtsi

drivers

clk

samsung

clk-exynos5420.c

include

dt-bindings

clock

exynos5420.h

+17

arch/arm/boot/dts/exynos5420.dtsi

··· 274 274 #power-domain-cells = <0>; 275 275 }; 276 276 277 + disp_pd: power-domain@100440C0 { 278 + compatible = "samsung,exynos4210-pd"; 279 + reg = <0x100440C0 0x20>; 280 + #power-domain-cells = <0>; 281 + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>, 282 + <&clock CLK_MOUT_USER_ACLK200_DISP1>, 283 + <&clock CLK_MOUT_SW_ACLK300>, 284 + <&clock CLK_MOUT_USER_ACLK300_DISP1>, 285 + <&clock CLK_MOUT_SW_ACLK400>, 286 + <&clock CLK_MOUT_USER_ACLK400_DISP1>; 287 + clock-names = "oscclk", "pclk0", "clk0", 288 + "pclk1", "clk1", "pclk2", "clk2"; 289 + }; 290 + 277 291 pinctrl_0: pinctrl@13400000 { 278 292 compatible = "samsung,exynos5420-pinctrl"; 279 293 reg = <0x13400000 0x1000>; ··· 555 541 fimd: fimd@14400000 { 556 542 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 557 543 clock-names = "sclk_fimd", "fimd"; 544 + power-domains = <&disp_pd>; 558 545 }; 559 546 560 547 adc: adc@12D10000 { ··· 729 714 phy = <&hdmiphy>; 730 715 samsung,syscon-phandle = <&pmu_system_controller>; 731 716 status = "disabled"; 717 + power-domains = <&disp_pd>; 732 718 }; 733 719 734 720 hdmiphy: hdmiphy@145D0000 { ··· 742 726 interrupts = <0 94 0>; 743 727 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; 744 728 clock-names = "mixer", "sclk_hdmi"; 729 + power-domains = <&disp_pd>; 745 730 }; 746 731 747 732 gsc_0: video-scaler@13e00000 {

+12 -11

drivers/clk/samsung/clk-exynos5420.c

··· 635 635 SRC_TOP3, 0, 1), 636 636 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 637 637 SRC_TOP3, 4, 1), 638 - MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p, 639 - SRC_TOP3, 8, 1), 638 + MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 639 + mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 640 640 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 641 641 SRC_TOP3, 12, 1), 642 642 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, ··· 663 663 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 664 664 SRC_TOP4, 28, 1), 665 665 666 - MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p, 667 - SRC_TOP5, 0, 1), 666 + MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 667 + mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 668 668 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 669 669 SRC_TOP5, 4, 1), 670 670 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, ··· 675 675 SRC_TOP5, 16, 1), 676 676 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 677 677 SRC_TOP5, 20, 1), 678 - MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p, 679 - SRC_TOP5, 24, 1), 678 + MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 679 + mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 680 680 MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, 681 681 SRC_TOP5, 28, 1), 682 682 ··· 693 693 SRC_TOP10, 0, 1), 694 694 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 695 695 SRC_TOP10, 4, 1), 696 - MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1), 696 + MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 697 + SRC_TOP10, 8, 1), 697 698 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 698 699 SRC_TOP10, 12, 1), 699 700 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, ··· 718 717 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 719 718 SRC_TOP11, 28, 1), 720 719 721 - MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p, 722 - SRC_TOP12, 4, 1), 720 + MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 721 + mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 723 722 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 724 723 SRC_TOP12, 8, 1), 725 724 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, ··· 727 726 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 728 727 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 729 728 SRC_TOP12, 20, 1), 730 - MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p, 731 - SRC_TOP12, 24, 1), 729 + MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 730 + mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 732 731 MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, 733 732 SRC_TOP12, 28, 1), 734 733

include/dt-bindings/clock/exynos5420.h

··· 204 204 #define CLK_MOUT_MAUDIO0 643 205 205 #define CLK_MOUT_USER_ACLK333 644 206 206 #define CLK_MOUT_SW_ACLK333 645 207 + #define CLK_MOUT_USER_ACLK200_DISP1 646 208 + #define CLK_MOUT_SW_ACLK200 647 209 + #define CLK_MOUT_USER_ACLK300_DISP1 648 210 + #define CLK_MOUT_SW_ACLK300 649 211 + #define CLK_MOUT_USER_ACLK400_DISP1 650 212 + #define CLK_MOUT_SW_ACLK400 651 207 213 208 214 /* divider clocks */ 209 215 #define CLK_DOUT_PIXEL 768