tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt

Merge "Samsung 2nd DT updates for v3.20" from Kukjin Kim:

- for all of Samsung SoCs
: use generic power domain bindings
: add 'dr_mode' property for hsotg/dwc2 devices

- exynos3250-rinato and exynos3250-monk
: add regulator-haptic

- exynos5422-odroidxu3
: reduce total RAM by 22 MiB because last 22 MiB
for secure monitor cannot be accessed by kernel
: add on-board INA231 sensors and LDO26 of PMIC
for the sensors

* tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: reduce total RAM by 22 MiB for exynos5422-odroidxu3
ARM: dts: add on-board INA231 sensors for exynos5422-odroidxu3
ARM: dts: Add regulator-haptic node for exynos3250-monk
ARM: dts: Add regulator-haptic node for exynos3250-rinato
ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
ARM: dts: convert to generic power domain bindings for exynos DT

Signed-off-by: Olof Johansson <olof@lixom.net>

Olof Johansson a35306d3 1e4cd7e5

+123 -34
+1 -1
Documentation/devicetree/bindings/arm/exynos/power_domain.txt
··· 23 23 devices in this power domain. Maximum of 4 pairs (N = 0 to 3) 24 24 are supported currently. 25 25 26 - Node of a device using power domains must have a samsung,power-domain property 26 + Node of a device using power domains must have a power-domains property 27 27 defined with a phandle to respective power domain. 28 28 29 29 Example:
+3 -3
Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt
··· 45 45 Exynos4 SoCs, there needs no "master" clock. 46 46 Exynos5 SoCs, some System MMUs must have "master" clocks. 47 47 - clocks: Required if the System MMU is needed to gate its clock. 48 - - samsung,power-domain: Required if the System MMU is needed to gate its power. 48 + - power-domains: Required if the System MMU is needed to gate its power. 49 49 Please refer to the following document: 50 50 Documentation/devicetree/bindings/arm/exynos/power_domain.txt 51 51 ··· 54 54 compatible = "samsung,exynos5-gsc"; 55 55 reg = <0x13e00000 0x1000>; 56 56 interrupts = <0 85 0>; 57 - samsung,power-domain = <&pd_gsc>; 57 + power-domains = <&pd_gsc>; 58 58 clocks = <&clock CLK_GSCL0>; 59 59 clock-names = "gscl"; 60 60 }; ··· 66 66 interrupts = <2 0>; 67 67 clock-names = "sysmmu", "master"; 68 68 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 69 - samsung,power-domain = <&pd_gsc>; 69 + power-domains = <&pd_gsc>; 70 70 };
+2 -2
Documentation/devicetree/bindings/media/s5p-mfc.txt
··· 28 28 for DMA contiguous memory allocation and its size. 29 29 30 30 Optional properties: 31 - - samsung,power-domain : power-domain property defined with a phandle 31 + - power-domains : power-domain property defined with a phandle 32 32 to respective power domain. 33 33 34 34 Example: ··· 38 38 compatible = "samsung,mfc-v5"; 39 39 reg = <0x13400000 0x10000>; 40 40 interrupts = <0 94 0>; 41 - samsung,power-domain = <&pd_mfc>; 41 + power-domains = <&pd_mfc>; 42 42 clocks = <&clock 273>; 43 43 clock-names = "mfc"; 44 44 };
+2 -2
Documentation/devicetree/bindings/video/exynos_dsim.txt
··· 21 21 according to DSI host bindings (see MIPI DSI bindings [1]) 22 22 23 23 Optional properties: 24 - - samsung,power-domain: a phandle to DSIM power domain node 24 + - power-domains: a phandle to DSIM power domain node 25 25 26 26 Child nodes: 27 27 Should contain DSI peripheral nodes (see MIPI DSI bindings [1]). ··· 53 53 phy-names = "dsim"; 54 54 vddcore-supply = <&vusb_reg>; 55 55 vddio-supply = <&vmipi_reg>; 56 - samsung,power-domain = <&pd_lcd0>; 56 + power-domains = <&pd_lcd0>; 57 57 #address-cells = <1>; 58 58 #size-cells = <0>; 59 59 samsung,pll-clock-frequency = <24000000>;
+2 -2
Documentation/devicetree/bindings/video/samsung-fimd.txt
··· 38 38 property. Must contain "sclk_fimd" and "fimd". 39 39 40 40 Optional Properties: 41 - - samsung,power-domain: a phandle to FIMD power domain node. 41 + - power-domains: a phandle to FIMD power domain node. 42 42 - samsung,invert-vden: video enable signal is inverted 43 43 - samsung,invert-vclk: video clock signal is inverted 44 44 - display-timings: timing settings for FIMD, as described in document [1]. ··· 97 97 interrupts = <11 0>, <11 1>, <11 2>; 98 98 clocks = <&clock 140>, <&clock 283>; 99 99 clock-names = "sclk_fimd", "fimd"; 100 - samsung,power-domain = <&pd_lcd0>; 100 + power-domains = <&pd_lcd0>; 101 101 status = "disabled"; 102 102 }; 103 103
+8
arch/arm/boot/dts/exynos3250-monk.dts
··· 108 108 }; 109 109 }; 110 110 }; 111 + 112 + haptics { 113 + compatible = "regulator-haptic"; 114 + haptic-supply = <&motor_reg>; 115 + min-microvolt = <1100000>; 116 + max-microvolt = <2700000>; 117 + }; 111 118 }; 112 119 113 120 &adc { ··· 147 140 &hsotg { 148 141 vusb_d-supply = <&ldo15_reg>; 149 142 vusb_a-supply = <&ldo12_reg>; 143 + dr_mode = "peripheral"; 150 144 status = "okay"; 151 145 }; 152 146
+8
arch/arm/boot/dts/exynos3250-rinato.dts
··· 99 99 }; 100 100 }; 101 101 }; 102 + 103 + haptics { 104 + compatible = "regulator-haptic"; 105 + haptic-supply = <&motor_reg>; 106 + min-microvolt = <1100000>; 107 + max-microvolt = <2700000>; 108 + }; 102 109 }; 103 110 104 111 &adc { ··· 138 131 &hsotg { 139 132 vusb_d-supply = <&ldo15_reg>; 140 133 vusb_a-supply = <&ldo12_reg>; 134 + dr_mode = "peripheral"; 141 135 status = "okay"; 142 136 }; 143 137
+8 -3
arch/arm/boot/dts/exynos3250.dtsi
··· 141 141 pd_cam: cam-power-domain@10023C00 { 142 142 compatible = "samsung,exynos4210-pd"; 143 143 reg = <0x10023C00 0x20>; 144 + #power-domain-cells = <0>; 144 145 }; 145 146 146 147 pd_mfc: mfc-power-domain@10023C40 { 147 148 compatible = "samsung,exynos4210-pd"; 148 149 reg = <0x10023C40 0x20>; 150 + #power-domain-cells = <0>; 149 151 }; 150 152 151 153 pd_g3d: g3d-power-domain@10023C60 { 152 154 compatible = "samsung,exynos4210-pd"; 153 155 reg = <0x10023C60 0x20>; 156 + #power-domain-cells = <0>; 154 157 }; 155 158 156 159 pd_lcd0: lcd0-power-domain@10023C80 { 157 160 compatible = "samsung,exynos4210-pd"; 158 161 reg = <0x10023C80 0x20>; 162 + #power-domain-cells = <0>; 159 163 }; 160 164 161 165 pd_isp: isp-power-domain@10023CA0 { 162 166 compatible = "samsung,exynos4210-pd"; 163 167 reg = <0x10023CA0 0x20>; 168 + #power-domain-cells = <0>; 164 169 }; 165 170 166 171 cmu: clock-controller@10030000 { ··· 240 235 interrupts = <0 84 0>, <0 85 0>, <0 86 0>; 241 236 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 242 237 clock-names = "sclk_fimd", "fimd"; 243 - samsung,power-domain = <&pd_lcd0>; 238 + power-domains = <&pd_lcd0>; 244 239 samsung,sysreg = <&sys_reg>; 245 240 status = "disabled"; 246 241 }; ··· 250 245 reg = <0x11C80000 0x10000>; 251 246 interrupts = <0 83 0>; 252 247 samsung,phy-type = <0>; 253 - samsung,power-domain = <&pd_lcd0>; 248 + power-domains = <&pd_lcd0>; 254 249 phys = <&mipi_phy 1>; 255 250 phy-names = "dsim"; 256 251 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; ··· 353 348 interrupts = <0 102 0>; 354 349 clock-names = "mfc", "sclk_mfc"; 355 350 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; 356 - samsung,power-domain = <&pd_mfc>; 351 + power-domains = <&pd_mfc>; 357 352 status = "disabled"; 358 353 }; 359 354
+16 -9
arch/arm/boot/dts/exynos4.dtsi
··· 81 81 pd_mfc: mfc-power-domain@10023C40 { 82 82 compatible = "samsung,exynos4210-pd"; 83 83 reg = <0x10023C40 0x20>; 84 + #power-domain-cells = <0>; 84 85 }; 85 86 86 87 pd_g3d: g3d-power-domain@10023C60 { 87 88 compatible = "samsung,exynos4210-pd"; 88 89 reg = <0x10023C60 0x20>; 90 + #power-domain-cells = <0>; 89 91 }; 90 92 91 93 pd_lcd0: lcd0-power-domain@10023C80 { 92 94 compatible = "samsung,exynos4210-pd"; 93 95 reg = <0x10023C80 0x20>; 96 + #power-domain-cells = <0>; 94 97 }; 95 98 96 99 pd_tv: tv-power-domain@10023C20 { 97 100 compatible = "samsung,exynos4210-pd"; 98 101 reg = <0x10023C20 0x20>; 102 + #power-domain-cells = <0>; 99 103 }; 100 104 101 105 pd_cam: cam-power-domain@10023C00 { 102 106 compatible = "samsung,exynos4210-pd"; 103 107 reg = <0x10023C00 0x20>; 108 + #power-domain-cells = <0>; 104 109 }; 105 110 106 111 pd_gps: gps-power-domain@10023CE0 { 107 112 compatible = "samsung,exynos4210-pd"; 108 113 reg = <0x10023CE0 0x20>; 114 + #power-domain-cells = <0>; 109 115 }; 110 116 111 117 pd_gps_alive: gps-alive-power-domain@10023D00 { 112 118 compatible = "samsung,exynos4210-pd"; 113 119 reg = <0x10023D00 0x20>; 120 + #power-domain-cells = <0>; 114 121 }; 115 122 116 123 gic: interrupt-controller@10490000 { ··· 154 147 compatible = "samsung,exynos4210-mipi-dsi"; 155 148 reg = <0x11C80000 0x10000>; 156 149 interrupts = <0 79 0>; 157 - samsung,power-domain = <&pd_lcd0>; 150 + power-domains = <&pd_lcd0>; 158 151 phys = <&mipi_phy 1>; 159 152 phy-names = "dsim"; 160 153 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; ··· 179 172 interrupts = <0 84 0>; 180 173 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; 181 174 clock-names = "fimc", "sclk_fimc"; 182 - samsung,power-domain = <&pd_cam>; 175 + power-domains = <&pd_cam>; 183 176 samsung,sysreg = <&sys_reg>; 184 177 status = "disabled"; 185 178 }; ··· 190 183 interrupts = <0 85 0>; 191 184 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; 192 185 clock-names = "fimc", "sclk_fimc"; 193 - samsung,power-domain = <&pd_cam>; 186 + power-domains = <&pd_cam>; 194 187 samsung,sysreg = <&sys_reg>; 195 188 status = "disabled"; 196 189 }; ··· 201 194 interrupts = <0 86 0>; 202 195 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; 203 196 clock-names = "fimc", "sclk_fimc"; 204 - samsung,power-domain = <&pd_cam>; 197 + power-domains = <&pd_cam>; 205 198 samsung,sysreg = <&sys_reg>; 206 199 status = "disabled"; 207 200 }; ··· 212 205 interrupts = <0 87 0>; 213 206 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; 214 207 clock-names = "fimc", "sclk_fimc"; 215 - samsung,power-domain = <&pd_cam>; 208 + power-domains = <&pd_cam>; 216 209 samsung,sysreg = <&sys_reg>; 217 210 status = "disabled"; 218 211 }; ··· 224 217 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; 225 218 clock-names = "csis", "sclk_csis"; 226 219 bus-width = <4>; 227 - samsung,power-domain = <&pd_cam>; 220 + power-domains = <&pd_cam>; 228 221 phys = <&mipi_phy 0>; 229 222 phy-names = "csis"; 230 223 status = "disabled"; ··· 239 232 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; 240 233 clock-names = "csis", "sclk_csis"; 241 234 bus-width = <2>; 242 - samsung,power-domain = <&pd_cam>; 235 + power-domains = <&pd_cam>; 243 236 phys = <&mipi_phy 2>; 244 237 phy-names = "csis"; 245 238 status = "disabled"; ··· 398 391 compatible = "samsung,mfc-v5"; 399 392 reg = <0x13400000 0x10000>; 400 393 interrupts = <0 94 0>; 401 - samsung,power-domain = <&pd_mfc>; 394 + power-domains = <&pd_mfc>; 402 395 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; 403 396 clock-names = "mfc", "sclk_mfc"; 404 397 status = "disabled"; ··· 648 641 interrupts = <11 0>, <11 1>, <11 2>; 649 642 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; 650 643 clock-names = "sclk_fimd", "fimd"; 651 - samsung,power-domain = <&pd_lcd0>; 644 + power-domains = <&pd_lcd0>; 652 645 samsung,sysreg = <&sys_reg>; 653 646 status = "disabled"; 654 647 };
+1
arch/arm/boot/dts/exynos4210-trats.dts
··· 91 91 hsotg@12480000 { 92 92 vusb_d-supply = <&vusb_reg>; 93 93 vusb_a-supply = <&vusbdac_reg>; 94 + dr_mode = "peripheral"; 94 95 status = "okay"; 95 96 }; 96 97
+1
arch/arm/boot/dts/exynos4210-universal_c210.dts
··· 71 71 hsotg@12480000 { 72 72 vusb_d-supply = <&ldo3_reg>; 73 73 vusb_a-supply = <&ldo8_reg>; 74 + dr_mode = "peripheral"; 74 75 status = "okay"; 75 76 }; 76 77
+1
arch/arm/boot/dts/exynos4210.dtsi
··· 79 79 pd_lcd1: lcd1-power-domain@10023CA0 { 80 80 compatible = "samsung,exynos4210-pd"; 81 81 reg = <0x10023CA0 0x20>; 82 + #power-domain-cells = <0>; 82 83 }; 83 84 84 85 gic: interrupt-controller@10490000 {
+1
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
··· 381 381 }; 382 382 383 383 hsotg@12480000 { 384 + dr_mode = "peripheral"; 384 385 status = "okay"; 385 386 vusb_d-supply = <&ldo15_reg>; 386 387 vusb_a-supply = <&ldo12_reg>;
+1
arch/arm/boot/dts/exynos4412-trats2.dts
··· 845 845 hsotg@12480000 { 846 846 vusb_d-supply = <&ldo15_reg>; 847 847 vusb_a-supply = <&ldo12_reg>; 848 + dr_mode = "peripheral"; 848 849 status = "okay"; 849 850 }; 850 851
+7
arch/arm/boot/dts/exynos4415.dtsi
··· 131 131 pd_cam: cam-power-domain@10024000 { 132 132 compatible = "samsung,exynos4210-pd"; 133 133 reg = <0x10024000 0x20>; 134 + #power-domain-cells = <0>; 134 135 }; 135 136 136 137 pd_tv: tv-power-domain@10024020 { 137 138 compatible = "samsung,exynos4210-pd"; 138 139 reg = <0x10024020 0x20>; 140 + #power-domain-cells = <0>; 139 141 }; 140 142 141 143 pd_mfc: mfc-power-domain@10024040 { 142 144 compatible = "samsung,exynos4210-pd"; 143 145 reg = <0x10024040 0x20>; 146 + #power-domain-cells = <0>; 144 147 }; 145 148 146 149 pd_g3d: g3d-power-domain@10024060 { 147 150 compatible = "samsung,exynos4210-pd"; 148 151 reg = <0x10024060 0x20>; 152 + #power-domain-cells = <0>; 149 153 }; 150 154 151 155 pd_lcd0: lcd0-power-domain@10024080 { 152 156 compatible = "samsung,exynos4210-pd"; 153 157 reg = <0x10024080 0x20>; 158 + #power-domain-cells = <0>; 154 159 }; 155 160 156 161 pd_isp0: isp0-power-domain@100240A0 { 157 162 compatible = "samsung,exynos4210-pd"; 158 163 reg = <0x100240A0 0x20>; 164 + #power-domain-cells = <0>; 159 165 }; 160 166 161 167 pd_isp1: isp1-power-domain@100240E0 { 162 168 compatible = "samsung,exynos4210-pd"; 163 169 reg = <0x100240E0 0x20>; 170 + #power-domain-cells = <0>; 164 171 }; 165 172 166 173 cmu: clock-controller@10030000 {
+4 -3
arch/arm/boot/dts/exynos4x12.dtsi
··· 52 52 pd_isp: isp-power-domain@10023CA0 { 53 53 compatible = "samsung,exynos4210-pd"; 54 54 reg = <0x10023CA0 0x20>; 55 + #power-domain-cells = <0>; 55 56 }; 56 57 57 58 clock: clock-controller@10030000 { ··· 196 195 compatible = "samsung,exynos4212-fimc-lite"; 197 196 reg = <0x12390000 0x1000>; 198 197 interrupts = <0 105 0>; 199 - samsung,power-domain = <&pd_isp>; 198 + power-domains = <&pd_isp>; 200 199 clocks = <&clock CLK_FIMC_LITE0>; 201 200 clock-names = "flite"; 202 201 status = "disabled"; ··· 206 205 compatible = "samsung,exynos4212-fimc-lite"; 207 206 reg = <0x123A0000 0x1000>; 208 207 interrupts = <0 106 0>; 209 - samsung,power-domain = <&pd_isp>; 208 + power-domains = <&pd_isp>; 210 209 clocks = <&clock CLK_FIMC_LITE1>; 211 210 clock-names = "flite"; 212 211 status = "disabled"; ··· 216 215 compatible = "samsung,exynos4212-fimc-is", "simple-bus"; 217 216 reg = <0x12000000 0x260000>; 218 217 interrupts = <0 90 0>, <0 95 0>; 219 - samsung,power-domain = <&pd_isp>; 218 + power-domains = <&pd_isp>; 220 219 clocks = <&clock CLK_FIMC_LITE0>, 221 220 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, 222 221 <&clock CLK_PPMUISPMX>,
+7 -5
arch/arm/boot/dts/exynos5250.dtsi
··· 93 93 pd_gsc: gsc-power-domain@10044000 { 94 94 compatible = "samsung,exynos4210-pd"; 95 95 reg = <0x10044000 0x20>; 96 + #power-domain-cells = <0>; 96 97 }; 97 98 98 99 pd_mfc: mfc-power-domain@10044040 { 99 100 compatible = "samsung,exynos4210-pd"; 100 101 reg = <0x10044040 0x20>; 102 + #power-domain-cells = <0>; 101 103 }; 102 104 103 105 clock: clock-controller@10010000 { ··· 224 222 compatible = "samsung,mfc-v6"; 225 223 reg = <0x11000000 0x10000>; 226 224 interrupts = <0 96 0>; 227 - samsung,power-domain = <&pd_mfc>; 225 + power-domains = <&pd_mfc>; 228 226 clocks = <&clock CLK_MFC>; 229 227 clock-names = "mfc"; 230 228 }; ··· 684 682 compatible = "samsung,exynos5-gsc"; 685 683 reg = <0x13e00000 0x1000>; 686 684 interrupts = <0 85 0>; 687 - samsung,power-domain = <&pd_gsc>; 685 + power-domains = <&pd_gsc>; 688 686 clocks = <&clock CLK_GSCL0>; 689 687 clock-names = "gscl"; 690 688 }; ··· 693 691 compatible = "samsung,exynos5-gsc"; 694 692 reg = <0x13e10000 0x1000>; 695 693 interrupts = <0 86 0>; 696 - samsung,power-domain = <&pd_gsc>; 694 + power-domains = <&pd_gsc>; 697 695 clocks = <&clock CLK_GSCL1>; 698 696 clock-names = "gscl"; 699 697 }; ··· 702 700 compatible = "samsung,exynos5-gsc"; 703 701 reg = <0x13e20000 0x1000>; 704 702 interrupts = <0 87 0>; 705 - samsung,power-domain = <&pd_gsc>; 703 + power-domains = <&pd_gsc>; 706 704 clocks = <&clock CLK_GSCL2>; 707 705 clock-names = "gscl"; 708 706 }; ··· 711 709 compatible = "samsung,exynos5-gsc"; 712 710 reg = <0x13e30000 0x1000>; 713 711 interrupts = <0 88 0>; 714 - samsung,power-domain = <&pd_gsc>; 712 + power-domains = <&pd_gsc>; 715 713 clocks = <&clock CLK_GSCL3>; 716 714 clock-names = "gscl"; 717 715 };
+7 -3
arch/arm/boot/dts/exynos5420.dtsi
··· 178 178 interrupts = <0 96 0>; 179 179 clocks = <&clock CLK_MFC>; 180 180 clock-names = "mfc"; 181 - samsung,power-domain = <&mfc_pd>; 181 + power-domains = <&mfc_pd>; 182 182 }; 183 183 184 184 mmc_0: mmc@12200000 { ··· 250 250 gsc_pd: power-domain@10044000 { 251 251 compatible = "samsung,exynos4210-pd"; 252 252 reg = <0x10044000 0x20>; 253 + #power-domain-cells = <0>; 253 254 }; 254 255 255 256 isp_pd: power-domain@10044020 { 256 257 compatible = "samsung,exynos4210-pd"; 257 258 reg = <0x10044020 0x20>; 259 + #power-domain-cells = <0>; 258 260 }; 259 261 260 262 mfc_pd: power-domain@10044060 { ··· 265 263 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, 266 264 <&clock CLK_MOUT_USER_ACLK333>; 267 265 clock-names = "oscclk", "pclk0", "clk0"; 266 + #power-domain-cells = <0>; 268 267 }; 269 268 270 269 msc_pd: power-domain@10044120 { 271 270 compatible = "samsung,exynos4210-pd"; 272 271 reg = <0x10044120 0x20>; 272 + #power-domain-cells = <0>; 273 273 }; 274 274 275 275 pinctrl_0: pinctrl@13400000 { ··· 734 730 interrupts = <0 85 0>; 735 731 clocks = <&clock CLK_GSCL0>; 736 732 clock-names = "gscl"; 737 - samsung,power-domain = <&gsc_pd>; 733 + power-domains = <&gsc_pd>; 738 734 }; 739 735 740 736 gsc_1: video-scaler@13e10000 { ··· 743 739 interrupts = <0 86 0>; 744 740 clocks = <&clock CLK_GSCL1>; 745 741 clock-names = "gscl"; 746 - samsung,power-domain = <&gsc_pd>; 742 + power-domains = <&gsc_pd>; 747 743 }; 748 744 749 745 pmu_system_controller: system-controller@10040000 {
+40 -1
arch/arm/boot/dts/exynos5422-odroidxu3.dts
··· 18 18 compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; 19 19 20 20 memory { 21 - reg = <0x40000000 0x80000000>; 21 + reg = <0x40000000 0x7EA00000>; 22 22 }; 23 23 24 24 chosen { ··· 171 171 regulator-name = "tsp_io"; 172 172 regulator-min-microvolt = <2800000>; 173 173 regulator-max-microvolt = <2800000>; 174 + regulator-always-on; 175 + }; 176 + 177 + ldo26_reg: LDO26 { 178 + regulator-name = "vdd_ldo26"; 179 + regulator-min-microvolt = <3000000>; 180 + regulator-max-microvolt = <3000000>; 174 181 regulator-always-on; 175 182 }; 176 183 ··· 336 329 337 330 &usbdrd_dwc3_1 { 338 331 dr_mode = "otg"; 332 + }; 333 + 334 + &i2c_0 { 335 + status = "okay"; 336 + 337 + /* A15 cluster: VDD_ARM */ 338 + ina231@40 { 339 + compatible = "ti,ina231"; 340 + reg = <0x40>; 341 + shunt-resistor = <10000>; 342 + }; 343 + 344 + /* memory: VDD_MEM */ 345 + ina231@41 { 346 + compatible = "ti,ina231"; 347 + reg = <0x41>; 348 + shunt-resistor = <10000>; 349 + }; 350 + 351 + /* GPU: VDD_G3D */ 352 + ina231@44 { 353 + compatible = "ti,ina231"; 354 + reg = <0x44>; 355 + shunt-resistor = <10000>; 356 + }; 357 + 358 + /* A7 cluster: VDD_KFC */ 359 + ina231@45 { 360 + compatible = "ti,ina231"; 361 + reg = <0x45>; 362 + shunt-resistor = <10000>; 363 + }; 339 364 };
+1
arch/arm/boot/dts/s5pv210-aquila.dts
··· 355 355 &hsotg { 356 356 vusb_a-supply = <&ldo3_reg>; 357 357 vusb_d-supply = <&ldo8_reg>; 358 + dr_mode = "peripheral"; 358 359 status = "okay"; 359 360 }; 360 361
+1
arch/arm/boot/dts/s5pv210-goni.dts
··· 333 333 &hsotg { 334 334 vusb_a-supply = <&ldo3_reg>; 335 335 vusb_d-supply = <&ldo8_reg>; 336 + dr_mode = "peripheral"; 336 337 status = "okay"; 337 338 }; 338 339
+1
arch/arm/boot/dts/s5pv210-smdkv210.dts
··· 181 181 }; 182 182 183 183 &hsotg { 184 + dr_mode = "peripheral"; 184 185 status = "okay"; 185 186 }; 186 187