tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: dev_priv cleanup in i915_gem_tiling.c
And a little bit of cascaded function prototype changes.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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drivers/gpu/drm/i915/i915_gem_tiling.c
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drivers/gpu/drm/i915/i915_gem_tiling.c
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/* Check pitch constriants for all chips & tiling formats */
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static bool
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-
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
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i915_tiling_ok(struct drm_i915_private *dev_priv,
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int stride, int size, int tiling_mode)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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int tile_width;
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/* Linear is always fine */
···
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/* check maximum stride & object size */
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/* i965+ stores the end address of the gtt mapping in the fence
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* reg, so dont bother to check the size */
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if (INTEL_INFO(dev)->gen >= 7) {
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if (INTEL_GEN(dev_priv) >= 7) {
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if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
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return false;
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} else if (INTEL_INFO(dev)->gen >= 4) {
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} else if (INTEL_GEN(dev_priv) >= 4) {
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if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
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return false;
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} else {
···
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return false;
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/* 965+ just needs multiples of tile width */
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if (INTEL_INFO(dev)->gen >= 4) {
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if (INTEL_GEN(dev_priv) >= 4) {
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if (stride & (tile_width - 1))
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return false;
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return true;
···
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if (!obj)
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return -ENOENT;
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if (!i915_tiling_ok(dev,
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if (!i915_tiling_ok(dev_priv,
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args->stride, obj->base.size, args->tiling_mode)) {
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i915_gem_object_put(obj);
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return -EINVAL;