tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: add mmhub v3_0_1 ip block
This adds mmhub v3_0_1 ip block support
v2: rebase (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Huang Rui
and committed by
Alex Deucher
10c4ad3a
d5771670
+589
-1
+2
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+2
-1
drivers/gpu/drm/amd/amdgpu/Makefile
···
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gmc_v8_0.o \
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gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
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gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \
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-
mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o
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mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o \
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mmhub_v3_0_1.o
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# add UMC block
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amdgpu-y += \
+4
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+4
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
···
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#include "nbio_v4_3.h"
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#include "gfxhub_v3_0.h"
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#include "mmhub_v3_0.h"
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+
#include "mmhub_v3_0_1.h"
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#include "mmhub_v3_0_2.h"
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#include "athub_v3_0.h"
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43
···
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static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev)
550
549
{
551
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switch (adev->ip_versions[MMHUB_HWIP][0]) {
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case IP_VERSION(3, 0, 1):
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adev->mmhub.funcs = &mmhub_v3_0_1_funcs;
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break;
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case IP_VERSION(3, 0, 2):
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555
adev->mmhub.funcs = &mmhub_v3_0_2_funcs;
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break;
+555
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
+555
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
···
1
+
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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+
*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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+
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#include "amdgpu.h"
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#include "mmhub_v3_0_1.h"
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+
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#include "mmhub/mmhub_3_0_1_offset.h"
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#include "mmhub/mmhub_3_0_1_sh_mask.h"
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#include "navi10_enum.h"
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+
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#include "soc15_common.h"
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+
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#define regMMVM_L2_CNTL3_DEFAULT 0x80100007
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#define regMMVM_L2_CNTL4_DEFAULT 0x000000c1
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#define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0
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+
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static const char *mmhub_client_ids_v3_0_1[][2] = {
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[0][0] = "VMC",
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[4][0] = "DCEDMC",
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[5][0] = "DCEVGA",
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[6][0] = "MP0",
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[7][0] = "MP1",
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[8][0] = "MPIO",
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[16][0] = "HDP",
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[17][0] = "LSDMA",
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[18][0] = "JPEG",
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[19][0] = "VCNU0",
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[21][0] = "VSCH",
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[22][0] = "VCNU1",
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[23][0] = "VCN1",
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[32+20][0] = "VCN0",
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[2][1] = "DBGUNBIO",
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[3][1] = "DCEDWB",
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[4][1] = "DCEDMC",
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[5][1] = "DCEVGA",
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[6][1] = "MP0",
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[7][1] = "MP1",
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[8][1] = "MPIO",
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[10][1] = "DBGU0",
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[11][1] = "DBGU1",
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[12][1] = "DBGU2",
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[13][1] = "DBGU3",
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[14][1] = "XDP",
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[15][1] = "OSSSYS",
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[16][1] = "HDP",
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[17][1] = "LSDMA",
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[18][1] = "JPEG",
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[19][1] = "VCNU0",
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[20][1] = "VCN0",
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[21][1] = "VSCH",
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[22][1] = "VCNU1",
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[23][1] = "VCN1",
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};
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+
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static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,
76
+
uint32_t flush_type)
77
+
{
78
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u32 req = 0;
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+
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/* invalidate using legacy mode on vmid*/
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
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PER_VMID_INVALIDATE_REQ, 1 << vmid);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
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CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
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+
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return req;
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}
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+
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static void
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mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
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uint32_t status)
98
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{
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uint32_t cid, rw;
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const char *mmhub_cid = NULL;
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cid = REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, CID);
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rw = REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, RW);
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dev_err(adev->dev,
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"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
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status);
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switch (adev->ip_versions[MMHUB_HWIP][0]) {
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case IP_VERSION(3, 0, 1):
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mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw];
114
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break;
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default:
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mmhub_cid = NULL;
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break;
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}
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+
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dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
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mmhub_cid ? mmhub_cid : "unknown", cid);
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dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
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REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
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dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
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REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
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dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
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REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
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dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
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REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
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dev_err(adev->dev, "\t RW: 0x%x\n", rw);
135
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}
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+
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static void mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device *adev,
138
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uint32_t vmid,
139
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uint64_t page_table_base)
140
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{
141
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
142
+
143
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WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
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hub->ctx_addr_distance * vmid,
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lower_32_bits(page_table_base));
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+
147
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WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
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hub->ctx_addr_distance * vmid,
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upper_32_bits(page_table_base));
150
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}
151
+
152
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static void mmhub_v3_0_1_init_gart_aperture_regs(struct amdgpu_device *adev)
153
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{
154
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uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
155
+
156
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mmhub_v3_0_1_setup_vm_pt_regs(adev, 0, pt_base);
157
+
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WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
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(u32)(adev->gmc.gart_start >> 12));
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WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
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(u32)(adev->gmc.gart_start >> 44));
162
+
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WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
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(u32)(adev->gmc.gart_end >> 12));
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WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
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(u32)(adev->gmc.gart_end >> 44));
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}
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+
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static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev)
170
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{
171
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uint64_t value;
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uint32_t tmp;
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+
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/* Program the AGP BAR */
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
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+
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/*
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* the new L1 policy will block SRIOV guest from writing
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* these regs, and they will be programed at host.
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* so skip programing these regs.
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*/
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/* Program the system aperture low logical page number. */
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
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adev->gmc.vram_start >> 18);
187
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
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adev->gmc.vram_end >> 18);
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+
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/* Set default page address. */
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value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
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adev->vm_manager.vram_base_offset;
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
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(u32)(value >> 12));
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
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(u32)(value >> 44));
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+
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/* Program "protection fault". */
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
200
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(u32)(adev->dummy_page_addr >> 12));
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
202
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(u32)((u64)adev->dummy_page_addr >> 44));
203
+
204
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tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
205
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
206
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ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
207
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
208
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}
209
+
210
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static void mmhub_v3_0_1_init_tlb_regs(struct amdgpu_device *adev)
211
+
{
212
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uint32_t tmp;
213
+
214
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/* Setup TLB control */
215
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tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
216
+
217
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
218
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
219
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
220
+
ENABLE_ADVANCED_DRIVER_MODEL, 1);
221
+
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
222
+
SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
223
+
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
224
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
225
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MTYPE, MTYPE_UC); /* UC, uncached */
226
+
227
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
228
+
}
229
+
230
+
static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)
231
+
{
232
+
uint32_t tmp;
233
+
234
+
/* Setup L2 cache */
235
+
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
236
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
237
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
238
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
239
+
ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
240
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/* XXX for emulation, Refer to closed source code.*/
241
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
242
+
0);
243
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
244
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
245
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
246
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
247
+
248
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tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
249
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
250
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
251
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
252
+
253
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tmp = regMMVM_L2_CNTL3_DEFAULT;
254
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if (adev->gmc.translate_further) {
255
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
256
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
257
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L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
258
+
} else {
259
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
260
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
261
+
L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
262
+
}
263
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
264
+
265
+
tmp = regMMVM_L2_CNTL4_DEFAULT;
266
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
267
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
268
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
269
+
270
+
tmp = regMMVM_L2_CNTL5_DEFAULT;
271
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
272
+
WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
273
+
}
274
+
275
+
static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)
276
+
{
277
+
uint32_t tmp;
278
+
279
+
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
280
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
281
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
282
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
283
+
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
284
+
WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
285
+
}
286
+
287
+
static void mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device *adev)
288
+
{
289
+
WREG32_SOC15(MMHUB, 0,
290
+
regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
291
+
0xFFFFFFFF);
292
+
WREG32_SOC15(MMHUB, 0,
293
+
regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
294
+
0x0000000F);
295
+
296
+
WREG32_SOC15(MMHUB, 0,
297
+
regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
298
+
WREG32_SOC15(MMHUB, 0,
299
+
regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
300
+
301
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
302
+
0);
303
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
304
+
0);
305
+
}
306
+
307
+
static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
308
+
{
309
+
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
310
+
int i;
311
+
uint32_t tmp;
312
+
313
+
for (i = 0; i <= 14; i++) {
314
+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
315
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
316
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
317
+
adev->vm_manager.num_level);
318
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
319
+
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
320
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
321
+
DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
322
+
1);
323
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
324
+
PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
325
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
326
+
VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
327
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
328
+
READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
329
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
330
+
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
331
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
332
+
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
333
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
334
+
PAGE_TABLE_BLOCK_SIZE,
335
+
adev->vm_manager.block_size - 9);
336
+
/* Send no-retry XNACK on fault to suppress VM fault storm. */
337
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
338
+
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
339
+
!amdgpu_noretry);
340
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
341
+
i * hub->ctx_distance, tmp);
342
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
343
+
i * hub->ctx_addr_distance, 0);
344
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
345
+
i * hub->ctx_addr_distance, 0);
346
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
347
+
i * hub->ctx_addr_distance,
348
+
lower_32_bits(adev->vm_manager.max_pfn - 1));
349
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
350
+
i * hub->ctx_addr_distance,
351
+
upper_32_bits(adev->vm_manager.max_pfn - 1));
352
+
}
353
+
354
+
hub->vm_cntx_cntl = tmp;
355
+
}
356
+
357
+
static void mmhub_v3_0_1_program_invalidation(struct amdgpu_device *adev)
358
+
{
359
+
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
360
+
unsigned i;
361
+
362
+
for (i = 0; i < 18; ++i) {
363
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
364
+
i * hub->eng_addr_distance, 0xffffffff);
365
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
366
+
i * hub->eng_addr_distance, 0x1f);
367
+
}
368
+
}
369
+
370
+
static int mmhub_v3_0_1_gart_enable(struct amdgpu_device *adev)
371
+
{
372
+
/* GART Enable. */
373
+
mmhub_v3_0_1_init_gart_aperture_regs(adev);
374
+
mmhub_v3_0_1_init_system_aperture_regs(adev);
375
+
mmhub_v3_0_1_init_tlb_regs(adev);
376
+
mmhub_v3_0_1_init_cache_regs(adev);
377
+
378
+
mmhub_v3_0_1_enable_system_domain(adev);
379
+
mmhub_v3_0_1_disable_identity_aperture(adev);
380
+
mmhub_v3_0_1_setup_vmid_config(adev);
381
+
mmhub_v3_0_1_program_invalidation(adev);
382
+
383
+
return 0;
384
+
}
385
+
386
+
static void mmhub_v3_0_1_gart_disable(struct amdgpu_device *adev)
387
+
{
388
+
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
389
+
u32 tmp;
390
+
u32 i;
391
+
392
+
/* Disable all tables */
393
+
for (i = 0; i < 16; i++)
394
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
395
+
i * hub->ctx_distance, 0);
396
+
397
+
/* Setup TLB control */
398
+
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
399
+
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
400
+
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
401
+
ENABLE_ADVANCED_DRIVER_MODEL, 0);
402
+
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
403
+
404
+
/* Setup L2 cache */
405
+
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
406
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
407
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
408
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
409
+
}
410
+
411
+
/**
412
+
* mmhub_v3_0_1_set_fault_enable_default - update GART/VM fault handling
413
+
*
414
+
* @adev: amdgpu_device pointer
415
+
* @value: true redirects VM faults to the default page
416
+
*/
417
+
static void mmhub_v3_0_1_set_fault_enable_default(struct amdgpu_device *adev,
418
+
bool value)
419
+
{
420
+
u32 tmp;
421
+
422
+
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
423
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
424
+
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
425
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
426
+
PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
427
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
428
+
PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
429
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
430
+
PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
431
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
432
+
TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
433
+
value);
434
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
435
+
NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
436
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
437
+
DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
438
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
439
+
VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
440
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
441
+
READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
442
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
443
+
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
444
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
445
+
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
446
+
if (!value) {
447
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
448
+
CRASH_ON_NO_RETRY_FAULT, 1);
449
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
450
+
CRASH_ON_RETRY_FAULT, 1);
451
+
}
452
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
453
+
}
454
+
455
+
static const struct amdgpu_vmhub_funcs mmhub_v3_0_1_vmhub_funcs = {
456
+
.print_l2_protection_fault_status = mmhub_v3_0_1_print_l2_protection_fault_status,
457
+
.get_invalidate_req = mmhub_v3_0_1_get_invalidate_req,
458
+
};
459
+
460
+
static void mmhub_v3_0_1_init(struct amdgpu_device *adev)
461
+
{
462
+
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
463
+
464
+
hub->ctx0_ptb_addr_lo32 =
465
+
SOC15_REG_OFFSET(MMHUB, 0,
466
+
regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
467
+
hub->ctx0_ptb_addr_hi32 =
468
+
SOC15_REG_OFFSET(MMHUB, 0,
469
+
regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
470
+
hub->vm_inv_eng0_sem =
471
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
472
+
hub->vm_inv_eng0_req =
473
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
474
+
hub->vm_inv_eng0_ack =
475
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
476
+
hub->vm_context0_cntl =
477
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
478
+
hub->vm_l2_pro_fault_status =
479
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
480
+
hub->vm_l2_pro_fault_cntl =
481
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
482
+
483
+
hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
484
+
hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
485
+
regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
486
+
hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
487
+
regMMVM_INVALIDATE_ENG0_REQ;
488
+
hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
489
+
regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
490
+
491
+
hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
492
+
MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
493
+
MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
494
+
MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
495
+
MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
496
+
MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
497
+
MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
498
+
499
+
hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs;
500
+
}
501
+
502
+
static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev)
503
+
{
504
+
u64 base;
505
+
506
+
base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
507
+
base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
508
+
base <<= 24;
509
+
510
+
return base;
511
+
}
512
+
513
+
static u64 mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device *adev)
514
+
{
515
+
return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
516
+
}
517
+
518
+
static void mmhub_v3_0_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
519
+
bool enable)
520
+
{
521
+
//TODO
522
+
}
523
+
524
+
static void mmhub_v3_0_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
525
+
bool enable)
526
+
{
527
+
//TODO
528
+
}
529
+
530
+
static int mmhub_v3_0_1_set_clockgating(struct amdgpu_device *adev,
531
+
enum amd_clockgating_state state)
532
+
{
533
+
mmhub_v3_0_1_update_medium_grain_clock_gating(adev,
534
+
state == AMD_CG_STATE_GATE);
535
+
mmhub_v3_0_1_update_medium_grain_light_sleep(adev,
536
+
state == AMD_CG_STATE_GATE);
537
+
return 0;
538
+
}
539
+
540
+
static void mmhub_v3_0_1_get_clockgating(struct amdgpu_device *adev, u64 *flags)
541
+
{
542
+
//TODO
543
+
}
544
+
545
+
const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs = {
546
+
.init = mmhub_v3_0_1_init,
547
+
.get_fb_location = mmhub_v3_0_1_get_fb_location,
548
+
.get_mc_fb_offset = mmhub_v3_0_1_get_mc_fb_offset,
549
+
.gart_enable = mmhub_v3_0_1_gart_enable,
550
+
.set_fault_enable_default = mmhub_v3_0_1_set_fault_enable_default,
551
+
.gart_disable = mmhub_v3_0_1_gart_disable,
552
+
.set_clockgating = mmhub_v3_0_1_set_clockgating,
553
+
.get_clockgating = mmhub_v3_0_1_get_clockgating,
554
+
.setup_vm_pt_regs = mmhub_v3_0_1_setup_vm_pt_regs,
555
+
};
+28
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h
+28
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h
···
1
+
/*
2
+
* Copyright 2022 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#ifndef __MMHUB_V3_0_1_H__
24
+
#define __MMHUB_V3_0_1_H__
25
+
26
+
extern const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs;
27
+
28
+
#endif