tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: mediatek: hdmi: mt8173: use common helper to access registers

Use MediaTek phy's common helper to access registers, then we can remove
hdmi's I/O helpers.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220920090038.15133-12-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Chunfeng Yun and committed by
Vinod Koul 0fb5e57e 309b4fec

+65 -75
+65 -75
drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
··· 5 5 */ 6 6 7 7 #include "phy-mtk-hdmi.h" 8 + #include "phy-mtk-io.h" 8 9 9 10 #define HDMI_CON0 0x00 10 11 #define RG_HDMITX_PLL_EN BIT(31) ··· 87 86 static int mtk_hdmi_pll_prepare(struct clk_hw *hw) 88 87 { 89 88 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 89 + void __iomem *base = hdmi_phy->regs; 90 90 91 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); 92 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); 93 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN); 94 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); 91 + mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); 92 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); 93 + mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_MHLCK_EN); 94 + mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); 95 95 usleep_range(100, 150); 96 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); 96 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN); 97 97 usleep_range(100, 150); 98 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); 99 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); 98 + mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); 99 + mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); 100 100 101 101 return 0; 102 102 } ··· 105 103 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) 106 104 { 107 105 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 106 + void __iomem *base = hdmi_phy->regs; 108 107 109 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); 110 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); 108 + mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); 109 + mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); 111 110 usleep_range(100, 150); 112 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); 111 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN); 113 112 usleep_range(100, 150); 114 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); 115 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); 116 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); 113 + mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); 114 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); 115 + mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); 117 116 usleep_range(100, 150); 118 117 } 119 118 ··· 136 133 unsigned long parent_rate) 137 134 { 138 135 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 136 + void __iomem *base = hdmi_phy->regs; 139 137 unsigned int pre_div; 140 138 unsigned int div; 141 139 unsigned int pre_ibias; ··· 157 153 div = 1; 158 154 } 159 155 160 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 161 - FIELD_PREP(RG_HDMITX_PLL_PREDIV, pre_div), 162 - RG_HDMITX_PLL_PREDIV); 163 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); 164 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 165 - FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) | 166 - FIELD_PREP(RG_HDMITX_PLL_IR, 0x1), 167 - RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR); 168 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, 169 - FIELD_PREP(RG_HDMITX_PLL_TXDIV, div), 170 - RG_HDMITX_PLL_TXDIV); 171 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 172 - FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) | 173 - FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19), 174 - RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV); 175 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, 176 - FIELD_PREP(RG_HDMITX_PLL_DIVEN, 0x2), 177 - RG_HDMITX_PLL_DIVEN); 178 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 179 - FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) | 180 - FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) | 181 - FIELD_PREP(RG_HDMITX_PLL_BR, 0x1), 182 - RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | 183 - RG_HDMITX_PLL_BR); 156 + mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div); 157 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); 158 + mtk_phy_update_bits(base + HDMI_CON0, 159 + RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR, 160 + FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) | 161 + FIELD_PREP(RG_HDMITX_PLL_IR, 0x1)); 162 + mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV, div); 163 + mtk_phy_update_bits(base + HDMI_CON0, 164 + RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV, 165 + FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) | 166 + FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19)); 167 + mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_DIVEN, 0x2); 168 + mtk_phy_update_bits(base + HDMI_CON0, 169 + RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | 170 + RG_HDMITX_PLL_BR, 171 + FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) | 172 + FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) | 173 + FIELD_PREP(RG_HDMITX_PLL_BR, 0x1)); 184 174 if (rate < 165000000) { 185 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, 186 - RG_HDMITX_PRD_IMP_EN); 175 + mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN); 187 176 pre_ibias = 0x3; 188 177 imp_en = 0x0; 189 178 hdmi_ibias = hdmi_phy->ibias; 190 179 } else { 191 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, 192 - RG_HDMITX_PRD_IMP_EN); 180 + mtk_phy_set_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN); 193 181 pre_ibias = 0x6; 194 182 imp_en = 0xf; 195 183 hdmi_ibias = hdmi_phy->ibias_up; 196 184 } 197 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 198 - FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) | 199 - FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) | 200 - FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) | 201 - FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias), 202 - RG_HDMITX_PRD_IBIAS_CLK | 203 - RG_HDMITX_PRD_IBIAS_D2 | 204 - RG_HDMITX_PRD_IBIAS_D1 | 205 - RG_HDMITX_PRD_IBIAS_D0); 206 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, 207 - FIELD_PREP(RG_HDMITX_DRV_IMP_EN, imp_en), 208 - RG_HDMITX_DRV_IMP_EN); 209 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, 210 - FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) | 211 - FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) | 212 - FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) | 213 - FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0), 214 - RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | 215 - RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); 216 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, 217 - FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) | 218 - FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) | 219 - FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) | 220 - FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias), 221 - RG_HDMITX_DRV_IBIAS_CLK | 222 - RG_HDMITX_DRV_IBIAS_D2 | 223 - RG_HDMITX_DRV_IBIAS_D1 | 224 - RG_HDMITX_DRV_IBIAS_D0); 185 + mtk_phy_update_bits(base + HDMI_CON4, 186 + RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 | 187 + RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0, 188 + FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) | 189 + FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) | 190 + FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) | 191 + FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias)); 192 + mtk_phy_update_field(base + HDMI_CON3, RG_HDMITX_DRV_IMP_EN, imp_en); 193 + mtk_phy_update_bits(base + HDMI_CON6, 194 + RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | 195 + RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0, 196 + FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) | 197 + FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) | 198 + FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) | 199 + FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0)); 200 + mtk_phy_update_bits(base + HDMI_CON5, 201 + RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 | 202 + RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0, 203 + FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) | 204 + FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) | 205 + FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) | 206 + FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias)); 225 207 return 0; 226 208 } 227 209 ··· 229 239 230 240 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) 231 241 { 232 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, 233 - RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN | 234 - RG_HDMITX_DRV_EN); 242 + mtk_phy_set_bits(hdmi_phy->regs + HDMI_CON3, 243 + RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN | 244 + RG_HDMITX_DRV_EN); 235 245 usleep_range(100, 150); 236 246 } 237 247 238 248 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) 239 249 { 240 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, 241 - RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN | 242 - RG_HDMITX_SER_EN); 250 + mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CON3, 251 + RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN | 252 + RG_HDMITX_SER_EN); 243 253 } 244 254 245 255 struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {