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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field
Use FIELD_PREP() macro to prepare bits field value, then no need define
macros of bits offset.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220920090038.15133-11-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Chunfeng Yun
and committed by
Vinod Koul
309b4fec
a8a78274
+26
-44
+26
-44
drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
+26
-44
drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
···
9
9
#define HDMI_CON0 0x00
10
10
#define RG_HDMITX_PLL_EN BIT(31)
11
11
#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24)
12
-
#define PLL_FBKDIV_SHIFT 24
13
12
#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22)
14
-
#define PLL_FBKSEL_SHIFT 22
15
13
#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20)
16
-
#define PREDIV_SHIFT 20
17
14
#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18)
18
-
#define POSDIV_SHIFT 18
19
15
#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16)
20
16
#define RG_HDMITX_PLL_IR GENMASK(15, 12)
21
-
#define PLL_IR_SHIFT 12
22
17
#define RG_HDMITX_PLL_IC GENMASK(11, 8)
23
-
#define PLL_IC_SHIFT 8
24
18
#define RG_HDMITX_PLL_BP GENMASK(7, 4)
25
-
#define PLL_BP_SHIFT 4
26
19
#define RG_HDMITX_PLL_BR GENMASK(3, 2)
27
-
#define PLL_BR_SHIFT 2
28
20
#define RG_HDMITX_PLL_BC GENMASK(1, 0)
29
-
#define PLL_BC_SHIFT 0
30
21
#define HDMI_CON1 0x04
31
22
#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29)
32
-
#define PLL_DIVEN_SHIFT 29
33
23
#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
34
24
#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26)
35
25
#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24)
···
30
40
#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
31
41
#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
32
42
#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10)
33
-
#define PLL_TXDIV_SHIFT 10
34
43
#define RG_HDMITX_PLL_LVROD_EN BIT(9)
35
44
#define RG_HDMITX_PLL_MONVC_EN BIT(8)
36
45
#define RG_HDMITX_PLL_MONCK_EN BIT(7)
···
47
58
#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20)
48
59
#define RG_HDMITX_DRV_EN GENMASK(19, 16)
49
60
#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12)
50
-
#define DRV_IMP_EN_SHIFT 12
51
61
#define RG_HDMITX_MHLCK_FORCE BIT(10)
52
62
#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
53
63
#define RG_HDMITX_MHLCK_EN BIT(8)
···
60
72
#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16)
61
73
#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8)
62
74
#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0)
63
-
#define PRD_IBIAS_CLK_SHIFT 24
64
-
#define PRD_IBIAS_D2_SHIFT 16
65
-
#define PRD_IBIAS_D1_SHIFT 8
66
-
#define PRD_IBIAS_D0_SHIFT 0
67
75
#define HDMI_CON5 0x14
68
76
#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24)
69
77
#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16)
70
78
#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8)
71
79
#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0)
72
-
#define DRV_IBIAS_CLK_SHIFT 24
73
-
#define DRV_IBIAS_D2_SHIFT 16
74
-
#define DRV_IBIAS_D1_SHIFT 8
75
-
#define DRV_IBIAS_D0_SHIFT 0
76
80
#define HDMI_CON6 0x18
77
81
#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24)
78
82
#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16)
79
83
#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8)
80
84
#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0)
81
-
#define DRV_IMP_CLK_SHIFT 24
82
-
#define DRV_IMP_D2_SHIFT 16
83
-
#define DRV_IMP_D1_SHIFT 8
84
-
#define DRV_IMP_D0_SHIFT 0
85
85
#define HDMI_CON7 0x1c
86
86
#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27)
87
87
#define RG_HDMITX_SER_DIN GENMASK(25, 16)
···
154
178
}
155
179
156
180
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
157
-
(pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
181
+
FIELD_PREP(RG_HDMITX_PLL_PREDIV, pre_div),
182
+
RG_HDMITX_PLL_PREDIV);
158
183
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
159
184
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
160
-
(0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
185
+
FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) |
186
+
FIELD_PREP(RG_HDMITX_PLL_IR, 0x1),
161
187
RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
162
188
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
163
-
(div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
189
+
FIELD_PREP(RG_HDMITX_PLL_TXDIV, div),
190
+
RG_HDMITX_PLL_TXDIV);
164
191
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
165
-
(0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
192
+
FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) |
193
+
FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19),
166
194
RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
167
195
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
168
-
(0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
196
+
FIELD_PREP(RG_HDMITX_PLL_DIVEN, 0x2),
197
+
RG_HDMITX_PLL_DIVEN);
169
198
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
170
-
(0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
171
-
(0x1 << PLL_BR_SHIFT),
199
+
FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) |
200
+
FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) |
201
+
FIELD_PREP(RG_HDMITX_PLL_BR, 0x1),
172
202
RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
173
203
RG_HDMITX_PLL_BR);
174
204
if (rate < 165000000) {
···
191
209
hdmi_ibias = hdmi_phy->ibias_up;
192
210
}
193
211
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
194
-
(pre_ibias << PRD_IBIAS_CLK_SHIFT) |
195
-
(pre_ibias << PRD_IBIAS_D2_SHIFT) |
196
-
(pre_ibias << PRD_IBIAS_D1_SHIFT) |
197
-
(pre_ibias << PRD_IBIAS_D0_SHIFT),
212
+
FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) |
213
+
FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) |
214
+
FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) |
215
+
FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias),
198
216
RG_HDMITX_PRD_IBIAS_CLK |
199
217
RG_HDMITX_PRD_IBIAS_D2 |
200
218
RG_HDMITX_PRD_IBIAS_D1 |
201
219
RG_HDMITX_PRD_IBIAS_D0);
202
220
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
203
-
(imp_en << DRV_IMP_EN_SHIFT),
221
+
FIELD_PREP(RG_HDMITX_DRV_IMP_EN, imp_en),
204
222
RG_HDMITX_DRV_IMP_EN);
205
223
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
206
-
(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
207
-
(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
208
-
(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
209
-
(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
224
+
FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) |
225
+
FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) |
226
+
FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) |
227
+
FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0),
210
228
RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
211
229
RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
212
230
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
213
-
(hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
214
-
(hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
215
-
(hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
216
-
(hdmi_ibias << DRV_IBIAS_D0_SHIFT),
231
+
FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) |
232
+
FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) |
233
+
FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) |
234
+
FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias),
217
235
RG_HDMITX_DRV_IBIAS_CLK |
218
236
RG_HDMITX_DRV_IBIAS_D2 |
219
237
RG_HDMITX_DRV_IBIAS_D1 |