perf tools: Bail out at "--sort dcacheline" and cacheline_size not known

There are cases where further work would be needed to overcome the fact
that neither sysconf(_SC_LEVEL1_DCACHE_LINESIZE) nor
/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size are
available in some systems (Android, for instance), so bail out when such
a situation takes place.

Cc: Adrian Hunter <[e-mail]>
Cc: David Ahern <[e-mail]>
Cc: Jiri Olsa <[e-mail]>
Cc: Namhyung Kim <[e-mail]>
Cc: Wang Nan <[e-mail]>
Link: http://lkml.kernel.org/n/[e-mail]
Signed-off-by: Arnaldo Carvalho de Melo <[e-mail]>

tools/perf/util/sort.c

···
 		if (sort__mode != SORT_MODE__MEMORY)
 			return -EINVAL;
 
+		if (sd->entry == &sort_mem_dcacheline && cacheline_size == 0)
+			return -EINVAL;
+
 		if (sd->entry == &sort_mem_daddr_sym)
 			list->sym = 1;
 
···
 		if (*tok) {
 			ret = sort_dimension__add(list, tok, evlist, level);
 			if (ret == -EINVAL) {
-				error("Invalid --sort key: `%s'", tok);
+				if (!cacheline_size && !strncasecmp(tok, "dcacheline", strlen(tok)))
+					error("The \"dcacheline\" --sort key needs to know the cacheline size and it couldn't be determined on this system");
+				else
+					error("Invalid --sort key: `%s'", tok);
 				break;
 			} else if (ret == -ESRCH) {
 				error("Unknown --sort key: `%s'", tok);