tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: drop navi reg init functions
No longer used since IP enumeration is driven by the IP
discovery table now.
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+2
-433
+2
-4
drivers/gpu/drm/amd/amdgpu/Makefile
+2
-4
drivers/gpu/drm/amd/amdgpu/Makefile
···
73
73
74
74
amdgpu-y += \
75
75
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
76
-
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
77
-
arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \
78
-
nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o \
79
-
beige_goby_reg_init.o yellow_carp_reg_init.o cyan_skillfish_reg_init.o
76
+
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \
77
+
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o
80
78
81
79
# add DF block
82
80
amdgpu-y += \
-54
drivers/gpu/drm/amd/amdgpu/beige_goby_reg_init.c
-54
drivers/gpu/drm/amd/amdgpu/beige_goby_reg_init.c
···
1
-
/*
2
-
* Copyright 2020 Advanced Micro Devices, Inc.
3
-
*
4
-
* Permission is hereby granted, free of charge, to any person obtaining a
5
-
* copy of this software and associated documentation files (the "Software"),
6
-
* to deal in the Software without restriction, including without limitation
7
-
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
-
* and/or sell copies of the Software, and to permit persons to whom the
9
-
* Software is furnished to do so, subject to the following conditions:
10
-
*
11
-
* The above copyright notice and this permission notice shall be included in
12
-
* all copies or substantial portions of the Software.
13
-
*
14
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
-
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
-
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
-
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
-
* OTHER DEALINGS IN THE SOFTWARE.
21
-
*
22
-
*/
23
-
#include "amdgpu.h"
24
-
#include "nv.h"
25
-
26
-
#include "soc15_common.h"
27
-
#include "soc15_hw_ip.h"
28
-
#include "beige_goby_ip_offset.h"
29
-
30
-
int beige_goby_reg_base_init(struct amdgpu_device *adev)
31
-
{
32
-
/* HW has more IP blocks, only initialize the block needed by driver */
33
-
uint32_t i;
34
-
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
35
-
adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
36
-
adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
37
-
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
38
-
adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
39
-
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
40
-
adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
41
-
adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
42
-
adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));
43
-
adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
44
-
adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
45
-
adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
46
-
adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
47
-
adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
48
-
adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
49
-
adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
50
-
adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
51
-
adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
52
-
}
53
-
return 0;
54
-
}
-51
drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c
-51
drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c
···
1
-
/*
2
-
* Copyright 2018 Advanced Micro Devices, Inc.
3
-
*
4
-
* Permission is hereby granted, free of charge, to any person obtaining a
5
-
* copy of this software and associated documentation files (the "Software"),
6
-
* to deal in the Software without restriction, including without limitation
7
-
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
-
* and/or sell copies of the Software, and to permit persons to whom the
9
-
* Software is furnished to do so, subject to the following conditions:
10
-
*
11
-
* The above copyright notice and this permission notice shall be included in
12
-
* all copies or substantial portions of the Software.
13
-
*
14
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
-
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
-
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
-
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
-
* OTHER DEALINGS IN THE SOFTWARE.
21
-
*
22
-
*/
23
-
#include "amdgpu.h"
24
-
#include "nv.h"
25
-
26
-
#include "soc15_common.h"
27
-
#include "soc15_hw_ip.h"
28
-
#include "cyan_skillfish_ip_offset.h"
29
-
30
-
int cyan_skillfish_reg_base_init(struct amdgpu_device *adev)
31
-
{
32
-
/* HW has more IP blocks, only initialized the blocke needed by driver */
33
-
uint32_t i;
34
-
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
35
-
adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
36
-
adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
37
-
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
38
-
adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
39
-
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
40
-
adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
41
-
adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
42
-
adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
43
-
adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
44
-
adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
45
-
adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
46
-
adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
47
-
adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
48
-
adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
49
-
}
50
-
return 0;
51
-
}
-9
drivers/gpu/drm/amd/amdgpu/nv.h
-9
drivers/gpu/drm/amd/amdgpu/nv.h
···
31
31
void nv_grbm_select(struct amdgpu_device *adev,
32
32
u32 me, u32 pipe, u32 queue, u32 vmid);
33
33
void nv_set_virt_ops(struct amdgpu_device *adev);
34
-
int navi10_reg_base_init(struct amdgpu_device *adev);
35
-
int navi14_reg_base_init(struct amdgpu_device *adev);
36
-
int navi12_reg_base_init(struct amdgpu_device *adev);
37
-
int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
38
-
void vangogh_reg_base_init(struct amdgpu_device *adev);
39
-
int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev);
40
-
int beige_goby_reg_base_init(struct amdgpu_device *adev);
41
-
int yellow_carp_reg_base_init(struct amdgpu_device *adev);
42
-
int cyan_skillfish_reg_base_init(struct amdgpu_device *adev);
43
34
44
35
#endif
-54
drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c
-54
drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c
···
1
-
/*
2
-
* Copyright 2019 Advanced Micro Devices, Inc.
3
-
*
4
-
* Permission is hereby granted, free of charge, to any person obtaining a
5
-
* copy of this software and associated documentation files (the "Software"),
6
-
* to deal in the Software without restriction, including without limitation
7
-
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
-
* and/or sell copies of the Software, and to permit persons to whom the
9
-
* Software is furnished to do so, subject to the following conditions:
10
-
*
11
-
* The above copyright notice and this permission notice shall be included in
12
-
* all copies or substantial portions of the Software.
13
-
*
14
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
-
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
-
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
-
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
-
* OTHER DEALINGS IN THE SOFTWARE.
21
-
*
22
-
*/
23
-
#include "amdgpu.h"
24
-
#include "nv.h"
25
-
26
-
#include "soc15_common.h"
27
-
#include "soc15_hw_ip.h"
28
-
#include "sienna_cichlid_ip_offset.h"
29
-
30
-
int sienna_cichlid_reg_base_init(struct amdgpu_device *adev)
31
-
{
32
-
/* HW has more IP blocks, only initialized the blocke needed by driver */
33
-
uint32_t i;
34
-
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
35
-
adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
36
-
adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
37
-
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
38
-
adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
39
-
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
40
-
adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
41
-
adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
42
-
adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
43
-
adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
44
-
adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
45
-
adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
46
-
adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
47
-
adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
48
-
adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
49
-
adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
50
-
adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
51
-
adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
52
-
}
53
-
return 0;
54
-
}
-50
drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
-50
drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
···
1
-
/*
2
-
* Copyright 2019 Advanced Micro Devices, Inc.
3
-
*
4
-
* Permission is hereby granted, free of charge, to any person obtaining a
5
-
* copy of this software and associated documentation files (the "Software"),
6
-
* to deal in the Software without restriction, including without limitation
7
-
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
-
* and/or sell copies of the Software, and to permit persons to whom the
9
-
* Software is furnished to do so, subject to the following conditions:
10
-
*
11
-
* The above copyright notice and this permission notice shall be included in
12
-
* all copies or substantial portions of the Software.
13
-
*
14
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
-
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
-
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
-
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
-
* OTHER DEALINGS IN THE SOFTWARE.
21
-
*
22
-
*/
23
-
#include "amdgpu.h"
24
-
#include "nv.h"
25
-
26
-
#include "soc15_common.h"
27
-
#include "soc15_hw_ip.h"
28
-
#include "vangogh_ip_offset.h"
29
-
30
-
void vangogh_reg_base_init(struct amdgpu_device *adev)
31
-
{
32
-
/* HW has more IP blocks, only initialized the blocke needed by driver */
33
-
uint32_t i;
34
-
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
35
-
adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
36
-
adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
37
-
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
38
-
adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
39
-
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
40
-
adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
41
-
adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
42
-
adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
43
-
adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
44
-
adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
45
-
adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
46
-
adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
47
-
adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
48
-
adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
49
-
}
50
-
}
-51
drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c
-51
drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c
···
1
-
/*
2
-
* Copyright 2019 Advanced Micro Devices, Inc.
3
-
*
4
-
* Permission is hereby granted, free of charge, to any person obtaining a
5
-
* copy of this software and associated documentation files (the "Software"),
6
-
* to deal in the Software without restriction, including without limitation
7
-
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
-
* and/or sell copies of the Software, and to permit persons to whom the
9
-
* Software is furnished to do so, subject to the following conditions:
10
-
*
11
-
* The above copyright notice and this permission notice shall be included in
12
-
* all copies or substantial portions of the Software.
13
-
*
14
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
-
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
-
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
-
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
-
* OTHER DEALINGS IN THE SOFTWARE.
21
-
*
22
-
*/
23
-
#include "amdgpu.h"
24
-
#include "nv.h"
25
-
26
-
#include "soc15_common.h"
27
-
#include "soc15_hw_ip.h"
28
-
#include "yellow_carp_offset.h"
29
-
30
-
int yellow_carp_reg_base_init(struct amdgpu_device *adev)
31
-
{
32
-
/* HW has more IP blocks, only initialized the block needed by driver */
33
-
uint32_t i;
34
-
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
35
-
adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
36
-
adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
37
-
adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
38
-
adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
39
-
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
40
-
adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
41
-
adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
42
-
adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
43
-
adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
44
-
adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
45
-
adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
46
-
adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
47
-
adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
48
-
adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
49
-
}
50
-
return 0;
51
-
}