drm/i915/sprite: convert to struct intel_display

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_sprite.[ch] to struct intel_display.

Some stragglers are left behind where needed.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/094db6a9f40404fcc14843d32b45465d31730d96.1724342644.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Jani Nikula 2 years ago 065ca63e ab0b0eb5

+112 -97

1 changed file

expand all

drivers

gpu

drm

i915

display

intel_sprite.c

+112 -97

drivers/gpu/drm/i915/display/intel_sprite.c

··· 48 48 #include "intel_sprite.h" 49 49 #include "intel_sprite_regs.h" 50 50 51 - static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite) 51 + static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite) 52 52 { 53 - return pipe * DISPLAY_RUNTIME_INFO(i915)->num_sprites[pipe] + sprite + 'A'; 53 + return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A'; 54 54 } 55 55 56 56 static void i9xx_plane_linear_gamma(u16 gamma[8]) ··· 67 67 chv_sprite_update_csc(const struct intel_plane_state *plane_state) 68 68 { 69 69 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 70 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 70 + struct intel_display *display = to_intel_display(plane->base.dev); 71 71 const struct drm_framebuffer *fb = plane_state->hw.fb; 72 72 enum plane_id plane_id = plane->id; 73 73 /* ··· 100 100 if (!fb->format->is_yuv) 101 101 return; 102 102 103 - intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id), 103 + intel_de_write_fw(display, SPCSCYGOFF(plane_id), 104 104 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 105 - intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id), 105 + intel_de_write_fw(display, SPCSCCBOFF(plane_id), 106 106 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 107 - intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id), 107 + intel_de_write_fw(display, SPCSCCROFF(plane_id), 108 108 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 109 109 110 - intel_de_write_fw(dev_priv, SPCSCC01(plane_id), 110 + intel_de_write_fw(display, SPCSCC01(plane_id), 111 111 SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); 112 - intel_de_write_fw(dev_priv, SPCSCC23(plane_id), 112 + intel_de_write_fw(display, SPCSCC23(plane_id), 113 113 SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); 114 - intel_de_write_fw(dev_priv, SPCSCC45(plane_id), 114 + intel_de_write_fw(display, SPCSCC45(plane_id), 115 115 SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); 116 - intel_de_write_fw(dev_priv, SPCSCC67(plane_id), 116 + intel_de_write_fw(display, SPCSCC67(plane_id), 117 117 SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); 118 - intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8])); 118 + intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8])); 119 119 120 - intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id), 120 + intel_de_write_fw(display, SPCSCYGICLAMP(plane_id), 121 121 SPCSC_IMAX(1023) | SPCSC_IMIN(0)); 122 - intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id), 122 + intel_de_write_fw(display, SPCSCCBICLAMP(plane_id), 123 123 SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 124 - intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id), 124 + intel_de_write_fw(display, SPCSCCRICLAMP(plane_id), 125 125 SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 126 126 127 - intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id), 127 + intel_de_write_fw(display, SPCSCYGOCLAMP(plane_id), 128 128 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 129 - intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id), 129 + intel_de_write_fw(display, SPCSCCBOCLAMP(plane_id), 130 130 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 131 - intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id), 131 + intel_de_write_fw(display, SPCSCCROCLAMP(plane_id), 132 132 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 133 133 } 134 134 ··· 139 139 vlv_sprite_update_clrc(const struct intel_plane_state *plane_state) 140 140 { 141 141 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 142 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 142 + struct intel_display *display = to_intel_display(plane->base.dev); 143 143 const struct drm_framebuffer *fb = plane_state->hw.fb; 144 144 enum pipe pipe = plane->pipe; 145 145 enum plane_id plane_id = plane->id; ··· 168 168 } 169 169 170 170 /* FIXME these register are single buffered :( */ 171 - intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id), 171 + intel_de_write_fw(display, SPCLRC0(pipe, plane_id), 172 172 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); 173 - intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id), 173 + intel_de_write_fw(display, SPCLRC1(pipe, plane_id), 174 174 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); 175 175 } 176 176 ··· 357 357 static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state) 358 358 { 359 359 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 360 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 360 + struct intel_display *display = to_intel_display(plane->base.dev); 361 361 const struct drm_framebuffer *fb = plane_state->hw.fb; 362 362 enum pipe pipe = plane->pipe; 363 363 enum plane_id plane_id = plane->id; ··· 373 373 /* FIXME these register are single buffered :( */ 374 374 /* The two end points are implicit (0.0 and 1.0) */ 375 375 for (i = 1; i < 8 - 1; i++) 376 - intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1), 376 + intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1), 377 377 gamma[i] << 16 | gamma[i] << 8 | gamma[i]); 378 378 } 379 379 ··· 382 382 const struct intel_crtc_state *crtc_state, 383 383 const struct intel_plane_state *plane_state) 384 384 { 385 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 385 + struct intel_display *display = to_intel_display(plane->base.dev); 386 386 enum pipe pipe = plane->pipe; 387 387 enum plane_id plane_id = plane->id; 388 388 int crtc_x = plane_state->uapi.dst.x1; ··· 390 390 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 391 391 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 392 392 393 - intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id), 393 + intel_de_write_fw(display, SPSTRIDE(pipe, plane_id), 394 394 plane_state->view.color_plane[0].mapping_stride); 395 - intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id), 395 + intel_de_write_fw(display, SPPOS(pipe, plane_id), 396 396 SP_POS_Y(crtc_y) | SP_POS_X(crtc_x)); 397 - intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id), 397 + intel_de_write_fw(display, SPSIZE(pipe, plane_id), 398 398 SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1)); 399 399 } 400 400 ··· 403 403 const struct intel_crtc_state *crtc_state, 404 404 const struct intel_plane_state *plane_state) 405 405 { 406 + struct intel_display *display = to_intel_display(plane->base.dev); 406 407 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 407 408 enum pipe pipe = plane->pipe; 408 409 enum plane_id plane_id = plane->id; ··· 421 420 chv_sprite_update_csc(plane_state); 422 421 423 422 if (key->flags) { 424 - intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id), 423 + intel_de_write_fw(display, SPKEYMINVAL(pipe, plane_id), 425 424 key->min_value); 426 - intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id), 425 + intel_de_write_fw(display, SPKEYMSK(pipe, plane_id), 427 426 key->channel_mask); 428 - intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id), 427 + intel_de_write_fw(display, SPKEYMAXVAL(pipe, plane_id), 429 428 key->max_value); 430 429 } 431 430 432 - intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0); 431 + intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0); 433 432 434 - intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset); 435 - intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), 433 + intel_de_write_fw(display, SPLINOFF(pipe, plane_id), linear_offset); 434 + intel_de_write_fw(display, SPTILEOFF(pipe, plane_id), 436 435 SP_OFFSET_Y(y) | SP_OFFSET_X(x)); 437 436 438 437 /* ··· 440 439 * disabled. Try to make the plane enable atomic by writing 441 440 * the control register just before the surface register. 442 441 */ 443 - intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl); 444 - intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 442 + intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl); 443 + intel_de_write_fw(display, SPSURF(pipe, plane_id), 445 444 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 446 445 447 446 vlv_sprite_update_clrc(plane_state); ··· 452 451 vlv_sprite_disable_arm(struct intel_plane *plane, 453 452 const struct intel_crtc_state *crtc_state) 454 453 { 455 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 454 + struct intel_display *display = to_intel_display(plane->base.dev); 456 455 enum pipe pipe = plane->pipe; 457 456 enum plane_id plane_id = plane->id; 458 457 459 - intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0); 460 - intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0); 458 + intel_de_write_fw(display, SPCNTR(pipe, plane_id), 0); 459 + intel_de_write_fw(display, SPSURF(pipe, plane_id), 0); 461 460 } 462 461 463 462 static bool 464 463 vlv_sprite_get_hw_state(struct intel_plane *plane, 465 464 enum pipe *pipe) 466 465 { 466 + struct intel_display *display = to_intel_display(plane->base.dev); 467 467 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 468 468 enum intel_display_power_domain power_domain; 469 469 enum plane_id plane_id = plane->id; ··· 476 474 if (!wakeref) 477 475 return false; 478 476 479 - ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; 477 + ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; 480 478 481 479 *pipe = plane->pipe; 482 480 ··· 768 766 static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state) 769 767 { 770 768 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 771 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 769 + struct intel_display *display = to_intel_display(plane->base.dev); 772 770 enum pipe pipe = plane->pipe; 773 771 u16 gamma[18]; 774 772 int i; ··· 780 778 781 779 /* FIXME these register are single buffered :( */ 782 780 for (i = 0; i < 16; i++) 783 - intel_de_write_fw(dev_priv, SPRGAMC(pipe, i), 781 + intel_de_write_fw(display, SPRGAMC(pipe, i), 784 782 gamma[i] << 20 | gamma[i] << 10 | gamma[i]); 785 783 786 - intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]); 787 - intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]); 788 - intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]); 784 + intel_de_write_fw(display, SPRGAMC16(pipe, 0), gamma[i]); 785 + intel_de_write_fw(display, SPRGAMC16(pipe, 1), gamma[i]); 786 + intel_de_write_fw(display, SPRGAMC16(pipe, 2), gamma[i]); 789 787 i++; 790 788 791 - intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]); 792 - intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]); 793 - intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]); 789 + intel_de_write_fw(display, SPRGAMC17(pipe, 0), gamma[i]); 790 + intel_de_write_fw(display, SPRGAMC17(pipe, 1), gamma[i]); 791 + intel_de_write_fw(display, SPRGAMC17(pipe, 2), gamma[i]); 794 792 i++; 795 793 } 796 794 ··· 799 797 const struct intel_crtc_state *crtc_state, 800 798 const struct intel_plane_state *plane_state) 801 799 { 800 + struct intel_display *display = to_intel_display(plane->base.dev); 802 801 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 803 802 enum pipe pipe = plane->pipe; 804 803 int crtc_x = plane_state->uapi.dst.x1; ··· 815 812 SPRITE_SRC_WIDTH(src_w - 1) | 816 813 SPRITE_SRC_HEIGHT(src_h - 1); 817 814 818 - intel_de_write_fw(dev_priv, SPRSTRIDE(pipe), 815 + intel_de_write_fw(display, SPRSTRIDE(pipe), 819 816 plane_state->view.color_plane[0].mapping_stride); 820 - intel_de_write_fw(dev_priv, SPRPOS(pipe), 817 + intel_de_write_fw(display, SPRPOS(pipe), 821 818 SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x)); 822 - intel_de_write_fw(dev_priv, SPRSIZE(pipe), 819 + intel_de_write_fw(display, SPRSIZE(pipe), 823 820 SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1)); 824 821 if (IS_IVYBRIDGE(dev_priv)) 825 - intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale); 822 + intel_de_write_fw(display, SPRSCALE(pipe), sprscale); 826 823 } 827 824 828 825 static void ··· 830 827 const struct intel_crtc_state *crtc_state, 831 828 const struct intel_plane_state *plane_state) 832 829 { 830 + struct intel_display *display = to_intel_display(plane->base.dev); 833 831 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 834 832 enum pipe pipe = plane->pipe; 835 833 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; ··· 844 840 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 845 841 846 842 if (key->flags) { 847 - intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value); 848 - intel_de_write_fw(dev_priv, SPRKEYMSK(pipe), 843 + intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value); 844 + intel_de_write_fw(display, SPRKEYMSK(pipe), 849 845 key->channel_mask); 850 - intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value); 846 + intel_de_write_fw(display, SPRKEYMAX(pipe), key->max_value); 851 847 } 852 848 853 849 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET 854 850 * register */ 855 851 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 856 - intel_de_write_fw(dev_priv, SPROFFSET(pipe), 852 + intel_de_write_fw(display, SPROFFSET(pipe), 857 853 SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x)); 858 854 } else { 859 - intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset); 860 - intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), 855 + intel_de_write_fw(display, SPRLINOFF(pipe), linear_offset); 856 + intel_de_write_fw(display, SPRTILEOFF(pipe), 861 857 SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x)); 862 858 } 863 859 ··· 866 862 * disabled. Try to make the plane enable atomic by writing 867 863 * the control register just before the surface register. 868 864 */ 869 - intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl); 870 - intel_de_write_fw(dev_priv, SPRSURF(pipe), 865 + intel_de_write_fw(display, SPRCTL(pipe), sprctl); 866 + intel_de_write_fw(display, SPRSURF(pipe), 871 867 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 872 868 873 869 ivb_sprite_update_gamma(plane_state); ··· 877 873 ivb_sprite_disable_arm(struct intel_plane *plane, 878 874 const struct intel_crtc_state *crtc_state) 879 875 { 876 + struct intel_display *display = to_intel_display(plane->base.dev); 880 877 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 881 878 enum pipe pipe = plane->pipe; 882 879 883 - intel_de_write_fw(dev_priv, SPRCTL(pipe), 0); 880 + intel_de_write_fw(display, SPRCTL(pipe), 0); 884 881 /* Disable the scaler */ 885 882 if (IS_IVYBRIDGE(dev_priv)) 886 - intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0); 887 - intel_de_write_fw(dev_priv, SPRSURF(pipe), 0); 883 + intel_de_write_fw(display, SPRSCALE(pipe), 0); 884 + intel_de_write_fw(display, SPRSURF(pipe), 0); 888 885 } 889 886 890 887 static bool 891 888 ivb_sprite_get_hw_state(struct intel_plane *plane, 892 889 enum pipe *pipe) 893 890 { 891 + struct intel_display *display = to_intel_display(plane->base.dev); 894 892 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 895 893 enum intel_display_power_domain power_domain; 896 894 intel_wakeref_t wakeref; ··· 903 897 if (!wakeref) 904 898 return false; 905 899 906 - ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE; 900 + ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE; 907 901 908 902 *pipe = plane->pipe; 909 903 ··· 1079 1073 static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state) 1080 1074 { 1081 1075 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1082 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1076 + struct intel_display *display = to_intel_display(plane->base.dev); 1083 1077 const struct drm_framebuffer *fb = plane_state->hw.fb; 1084 1078 enum pipe pipe = plane->pipe; 1085 1079 u16 gamma[8]; ··· 1094 1088 /* FIXME these register are single buffered :( */ 1095 1089 /* The two end points are implicit (0.0 and 1.0) */ 1096 1090 for (i = 1; i < 8 - 1; i++) 1097 - intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1), 1091 + intel_de_write_fw(display, DVSGAMC_G4X(pipe, i - 1), 1098 1092 gamma[i] << 16 | gamma[i] << 8 | gamma[i]); 1099 1093 } 1100 1094 ··· 1109 1103 static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state) 1110 1104 { 1111 1105 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1112 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1106 + struct intel_display *display = to_intel_display(plane->base.dev); 1113 1107 const struct drm_framebuffer *fb = plane_state->hw.fb; 1114 1108 enum pipe pipe = plane->pipe; 1115 1109 u16 gamma[17]; ··· 1123 1117 1124 1118 /* FIXME these register are single buffered :( */ 1125 1119 for (i = 0; i < 16; i++) 1126 - intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i), 1120 + intel_de_write_fw(display, DVSGAMC_ILK(pipe, i), 1127 1121 gamma[i] << 20 | gamma[i] << 10 | gamma[i]); 1128 1122 1129 - intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]); 1130 - intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]); 1131 - intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]); 1123 + intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 0), gamma[i]); 1124 + intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 1), gamma[i]); 1125 + intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 2), gamma[i]); 1132 1126 i++; 1133 1127 } 1134 1128 ··· 1137 1131 const struct intel_crtc_state *crtc_state, 1138 1132 const struct intel_plane_state *plane_state) 1139 1133 { 1140 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1134 + struct intel_display *display = to_intel_display(plane->base.dev); 1141 1135 enum pipe pipe = plane->pipe; 1142 1136 int crtc_x = plane_state->uapi.dst.x1; 1143 1137 int crtc_y = plane_state->uapi.dst.y1; ··· 1152 1146 DVS_SRC_WIDTH(src_w - 1) | 1153 1147 DVS_SRC_HEIGHT(src_h - 1); 1154 1148 1155 - intel_de_write_fw(dev_priv, DVSSTRIDE(pipe), 1149 + intel_de_write_fw(display, DVSSTRIDE(pipe), 1156 1150 plane_state->view.color_plane[0].mapping_stride); 1157 - intel_de_write_fw(dev_priv, DVSPOS(pipe), 1151 + intel_de_write_fw(display, DVSPOS(pipe), 1158 1152 DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x)); 1159 - intel_de_write_fw(dev_priv, DVSSIZE(pipe), 1153 + intel_de_write_fw(display, DVSSIZE(pipe), 1160 1154 DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1)); 1161 - intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale); 1155 + intel_de_write_fw(display, DVSSCALE(pipe), dvsscale); 1162 1156 } 1163 1157 1164 1158 static void ··· 1166 1160 const struct intel_crtc_state *crtc_state, 1167 1161 const struct intel_plane_state *plane_state) 1168 1162 { 1163 + struct intel_display *display = to_intel_display(plane->base.dev); 1169 1164 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1170 1165 enum pipe pipe = plane->pipe; 1171 1166 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; ··· 1180 1173 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1181 1174 1182 1175 if (key->flags) { 1183 - intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value); 1184 - intel_de_write_fw(dev_priv, DVSKEYMSK(pipe), 1176 + intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value); 1177 + intel_de_write_fw(display, DVSKEYMSK(pipe), 1185 1178 key->channel_mask); 1186 - intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value); 1179 + intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value); 1187 1180 } 1188 1181 1189 - intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset); 1190 - intel_de_write_fw(dev_priv, DVSTILEOFF(pipe), 1182 + intel_de_write_fw(display, DVSLINOFF(pipe), linear_offset); 1183 + intel_de_write_fw(display, DVSTILEOFF(pipe), 1191 1184 DVS_OFFSET_Y(y) | DVS_OFFSET_X(x)); 1192 1185 1193 1186 /* ··· 1195 1188 * disabled. Try to make the plane enable atomic by writing 1196 1189 * the control register just before the surface register. 1197 1190 */ 1198 - intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr); 1199 - intel_de_write_fw(dev_priv, DVSSURF(pipe), 1191 + intel_de_write_fw(display, DVSCNTR(pipe), dvscntr); 1192 + intel_de_write_fw(display, DVSSURF(pipe), 1200 1193 intel_plane_ggtt_offset(plane_state) + dvssurf_offset); 1201 1194 1202 1195 if (IS_G4X(dev_priv)) ··· 1209 1202 g4x_sprite_disable_arm(struct intel_plane *plane, 1210 1203 const struct intel_crtc_state *crtc_state) 1211 1204 { 1212 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1205 + struct intel_display *display = to_intel_display(plane->base.dev); 1213 1206 enum pipe pipe = plane->pipe; 1214 1207 1215 - intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0); 1208 + intel_de_write_fw(display, DVSCNTR(pipe), 0); 1216 1209 /* Disable the scaler */ 1217 - intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0); 1218 - intel_de_write_fw(dev_priv, DVSSURF(pipe), 0); 1210 + intel_de_write_fw(display, DVSSCALE(pipe), 0); 1211 + intel_de_write_fw(display, DVSSURF(pipe), 0); 1219 1212 } 1220 1213 1221 1214 static bool 1222 1215 g4x_sprite_get_hw_state(struct intel_plane *plane, 1223 1216 enum pipe *pipe) 1224 1217 { 1218 + struct intel_display *display = to_intel_display(plane->base.dev); 1225 1219 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1226 1220 enum intel_display_power_domain power_domain; 1227 1221 intel_wakeref_t wakeref; ··· 1233 1225 if (!wakeref) 1234 1226 return false; 1235 1227 1236 - ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE; 1228 + ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE; 1237 1229 1238 1230 *pipe = plane->pipe; 1239 1231 ··· 1263 1255 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, 1264 1256 struct intel_plane_state *plane_state) 1265 1257 { 1266 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1258 + struct intel_display *display = to_intel_display(crtc_state); 1267 1259 const struct drm_framebuffer *fb = plane_state->hw.fb; 1268 1260 const struct drm_rect *src = &plane_state->uapi.src; 1269 1261 const struct drm_rect *dst = &plane_state->uapi.dst; ··· 1289 1281 1290 1282 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1291 1283 if (src_h & 1) { 1292 - drm_dbg_kms(&i915->drm, "Source height must be even with interlaced modes\n"); 1284 + drm_dbg_kms(display->drm, 1285 + "Source height must be even with interlaced modes\n"); 1293 1286 return -EINVAL; 1294 1287 } 1295 1288 min_height = 6; ··· 1302 1293 1303 1294 if (src_w < min_width || src_h < min_height || 1304 1295 src_w > 2048 || src_h > 2048) { 1305 - drm_dbg_kms(&i915->drm, "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n", 1296 + drm_dbg_kms(display->drm, 1297 + "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n", 1306 1298 src_w, src_h, min_width, min_height, 2048, 2048); 1307 1299 return -EINVAL; 1308 1300 } 1309 1301 1310 1302 if (width_bytes > 4096) { 1311 - drm_dbg_kms(&i915->drm, "Fetch width (%d) exceeds hardware max with scaling (%u)\n", 1303 + drm_dbg_kms(display->drm, 1304 + "Fetch width (%d) exceeds hardware max with scaling (%u)\n", 1312 1305 width_bytes, 4096); 1313 1306 return -EINVAL; 1314 1307 } 1315 1308 1316 1309 if (stride > 4096) { 1317 - drm_dbg_kms(&i915->drm, "Stride (%u) exceeds hardware max with scaling (%u)\n", 1310 + drm_dbg_kms(display->drm, 1311 + "Stride (%u) exceeds hardware max with scaling (%u)\n", 1318 1312 stride, 4096); 1319 1313 return -EINVAL; 1320 1314 } ··· 1329 1317 g4x_sprite_check(struct intel_crtc_state *crtc_state, 1330 1318 struct intel_plane_state *plane_state) 1331 1319 { 1320 + struct intel_display *display = to_intel_display(crtc_state); 1332 1321 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1333 1322 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1334 1323 int min_scale = DRM_PLANE_NO_SCALING; ··· 1337 1324 int ret; 1338 1325 1339 1326 if (g4x_fb_scalable(plane_state->hw.fb)) { 1340 - if (DISPLAY_VER(dev_priv) < 7) { 1327 + if (DISPLAY_VER(display) < 7) { 1341 1328 min_scale = 1; 1342 1329 max_scale = 16 << 16; 1343 1330 } else if (IS_IVYBRIDGE(dev_priv)) { ··· 1366 1353 if (ret) 1367 1354 return ret; 1368 1355 1369 - if (DISPLAY_VER(dev_priv) >= 7) 1356 + if (DISPLAY_VER(display) >= 7) 1370 1357 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); 1371 1358 else 1372 1359 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); ··· 1377 1364 int chv_plane_check_rotation(const struct intel_plane_state *plane_state) 1378 1365 { 1379 1366 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1367 + struct intel_display *display = to_intel_display(plane->base.dev); 1380 1368 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1381 1369 unsigned int rotation = plane_state->hw.rotation; 1382 1370 ··· 1385 1371 if (IS_CHERRYVIEW(dev_priv) && 1386 1372 rotation & DRM_MODE_ROTATE_180 && 1387 1373 rotation & DRM_MODE_REFLECT_X) { 1388 - drm_dbg_kms(&dev_priv->drm, 1374 + drm_dbg_kms(display->drm, 1389 1375 "Cannot rotate and reflect at the same time\n"); 1390 1376 return -EINVAL; 1391 1377 } ··· 1587 1573 intel_sprite_plane_create(struct drm_i915_private *dev_priv, 1588 1574 enum pipe pipe, int sprite) 1589 1575 { 1576 + struct intel_display *display = &dev_priv->display; 1590 1577 struct intel_plane *plane; 1591 1578 const struct drm_plane_funcs *plane_funcs; 1592 1579 unsigned int supported_rotations; ··· 1619 1604 } 1620 1605 1621 1606 plane_funcs = &vlv_sprite_funcs; 1622 - } else if (DISPLAY_VER(dev_priv) >= 7) { 1607 + } else if (DISPLAY_VER(display) >= 7) { 1623 1608 plane->update_noarm = ivb_sprite_update_noarm; 1624 1609 plane->update_arm = ivb_sprite_update_arm; 1625 1610 plane->disable_arm = ivb_sprite_disable_arm; ··· 1678 1663 1679 1664 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); 1680 1665 1681 - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 1666 + ret = drm_universal_plane_init(display->drm, &plane->base, 1682 1667 0, plane_funcs, 1683 1668 formats, num_formats, modifiers, 1684 1669 DRM_PLANE_TYPE_OVERLAY, 1685 - "sprite %c", sprite_name(dev_priv, pipe, sprite)); 1670 + "sprite %c", sprite_name(display, pipe, sprite)); 1686 1671 kfree(modifiers); 1687 1672 1688 1673 if (ret)