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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
[IA64] MCA/INIT: remove the physical mode path from minstate.h
Remove the physical mode path from minstate.h.
Signed-off-by: Keith Owens <kaos@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
authored by
Keith Owens
and committed by
Tony Luck
05f335ea
7f613c7d
-1
arch/ia64/kernel/ivt.S
-1
arch/ia64/kernel/ivt.S
+18
-70
arch/ia64/kernel/minstate.h
+18
-70
arch/ia64/kernel/minstate.h
···
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#include "entry.h"
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/*
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* For ivt.s we want to access the stack virtually so we don't have to disable translation
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* on interrupts.
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*
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* On entry:
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* r1: pointer to current task (ar.k6)
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*/
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#define MINSTATE_START_SAVE_MIN_VIRT \
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(pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
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;; \
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(pUStk) mov.m r24=ar.rnat; \
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(pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
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(pKStk) mov r1=sp; /* get sp */ \
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;; \
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(pUStk) lfetch.fault.excl.nt1 [r22]; \
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(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
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(pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
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;; \
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(pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
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(pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \
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;; \
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(pUStk) mov r18=ar.bsp; \
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(pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */
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-
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#define MINSTATE_END_SAVE_MIN_VIRT \
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bsw.1; /* switch back to bank 1 (must be last in insn group) */ \
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;;
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/*
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* For mca_asm.S we want to access the stack physically since the state is saved before we
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* go virtual and don't want to destroy the iip or ipsr.
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*/
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#define MINSTATE_START_SAVE_MIN_PHYS \
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(pKStk) mov r3=IA64_KR(PER_CPU_DATA);; \
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(pKStk) addl r3=THIS_CPU(ia64_mca_data),r3;; \
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(pKStk) ld8 r3 = [r3];; \
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(pKStk) addl r3=IA64_MCA_CPU_INIT_STACK_OFFSET,r3;; \
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(pKStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r3; \
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(pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
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(pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of register backing store */ \
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;; \
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(pUStk) mov r24=ar.rnat; \
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(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
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(pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
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(pUStk) dep r22=-1,r22,61,3; /* compute kernel virtual addr of RBS */ \
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;; \
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(pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
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;; \
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(pUStk) mov r18=ar.bsp; \
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(pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \
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#define MINSTATE_END_SAVE_MIN_PHYS \
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dep r12=-1,r12,61,3; /* make sp a kernel virtual address */ \
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;;
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#ifdef MINSTATE_VIRT
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# define MINSTATE_GET_CURRENT(reg) mov reg=IA64_KR(CURRENT)
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# define MINSTATE_START_SAVE_MIN MINSTATE_START_SAVE_MIN_VIRT
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# define MINSTATE_END_SAVE_MIN MINSTATE_END_SAVE_MIN_VIRT
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#endif
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#ifdef MINSTATE_PHYS
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# define MINSTATE_GET_CURRENT(reg) mov reg=IA64_KR(CURRENT);; tpa reg=reg
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# define MINSTATE_START_SAVE_MIN MINSTATE_START_SAVE_MIN_PHYS
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# define MINSTATE_END_SAVE_MIN MINSTATE_END_SAVE_MIN_PHYS
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#endif
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/*
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* DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
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* the minimum state necessary that allows us to turn psr.ic back
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* on.
···
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* we can pass interruption state as arguments to a handler.
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*/
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#define DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \
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MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \
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mov r16=IA64_KR(CURRENT); /* M */ \
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mov r27=ar.rsc; /* M */ \
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mov r20=r1; /* A */ \
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mov r25=ar.unat; /* M */ \
···
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SAVE_IFS; \
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cmp.eq pKStk,pUStk=r0,r17; /* are we in kernel mode already? */ \
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;; \
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MINSTATE_START_SAVE_MIN \
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(pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
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;; \
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(pUStk) mov.m r24=ar.rnat; \
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(pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
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(pKStk) mov r1=sp; /* get sp */ \
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;; \
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(pUStk) lfetch.fault.excl.nt1 [r22]; \
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(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
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(pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
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;; \
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(pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
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(pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \
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;; \
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(pUStk) mov r18=ar.bsp; \
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(pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \
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adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \
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adds r16=PT(CR_IPSR),r1; \
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;; \
···
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EXTRA; \
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movl r1=__gp; /* establish kernel global pointer */ \
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;; \
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MINSTATE_END_SAVE_MIN
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bsw.1; /* switch back to bank 1 (must be last in insn group) */ \
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;;
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/*
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* SAVE_REST saves the remainder of pt_regs (with psr.ic on).