···4919 pci_cmd &= ~PCI_COMMAND_SERR;4920 pci_cmd |= PCI_COMMAND_PARITY;4921 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);4922- pci_set_mwi(pdev);0004923 /*4924 * On some architectures, the default cache line size set4925 * by pci_set_mwi reduces perforamnce. We have to increase
···4919 pci_cmd &= ~PCI_COMMAND_SERR;4920 pci_cmd |= PCI_COMMAND_PARITY;4921 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);4922+ if (pci_set_mwi(pdev))4923+ printk(KERN_WARNING PFX "Could enable MWI for %s\n",4924+ pci_name(pdev));4925+4926 /*4927 * On some architectures, the default cache line size set4928 * by pci_set_mwi reduces perforamnce. We have to increase