···49194919 pci_cmd &= ~PCI_COMMAND_SERR;49204920 pci_cmd |= PCI_COMMAND_PARITY;49214921 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);49224922- pci_set_mwi(pdev);49224922+ if (pci_set_mwi(pdev))49234923+ printk(KERN_WARNING PFX "Could enable MWI for %s\n",49244924+ pci_name(pdev));49254925+49234926 /*49244927 * On some architectures, the default cache line size set49254928 * by pci_set_mwi reduces perforamnce. We have to increase