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kernel
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linux
clk: mmp: Add Marvell PXA1908 APBCP driver
Add driver for the APBCP controller block found on Marvell's PXA1908
SoC.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-6-e050609b8d6c@skole.hr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Duje Mihanović
and committed by
Stephen Boyd
a89233db
51ce5591
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drivers/clk/mmp/Makefile
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-1
drivers/clk/mmp/Makefile
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drivers/clk/mmp/clk-pxa1908-apbcp.c
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drivers/clk/mmp/clk-pxa1908-apbcp.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <dt-bindings/clock/marvell,pxa1908.h>
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#include "clk.h"
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#define APBCP_UART2 0x1c
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#define APBCP_TWSI2 0x28
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#define APBCP_AICER 0x38
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#define APBCP_NR_CLKS 4
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struct pxa1908_clk_unit {
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struct mmp_clk_unit unit;
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void __iomem *base;
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};
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static DEFINE_SPINLOCK(uart2_lock);
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static const char * const uart_parent_names[] = {"pll1_117", "uart_pll"};
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static struct mmp_param_gate_clk apbcp_gate_clks[] = {
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{PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
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{PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, APBCP_TWSI2, 0x7, 0x3, 0x0, 0, NULL},
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{PXA1908_CLK_AICER, "ripc_clk", NULL, 0, APBCP_AICER, 0x7, 0x2, 0x0, 0, NULL},
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};
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static struct mmp_param_mux_clk apbcp_mux_clks[] = {
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{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
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};
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static void pxa1908_apb_p_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
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{
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struct mmp_clk_unit *unit = &pxa_unit->unit;
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mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->base,
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ARRAY_SIZE(apbcp_mux_clks));
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mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->base,
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ARRAY_SIZE(apbcp_gate_clks));
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}
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static int pxa1908_apbcp_probe(struct platform_device *pdev)
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{
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struct pxa1908_clk_unit *pxa_unit;
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pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL);
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if (IS_ERR(pxa_unit))
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return PTR_ERR(pxa_unit);
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pxa_unit->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pxa_unit->base))
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return PTR_ERR(pxa_unit->base);
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mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, APBCP_NR_CLKS);
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pxa1908_apb_p_periph_clk_init(pxa_unit);
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return 0;
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}
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static const struct of_device_id pxa1908_apbcp_match_table[] = {
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{ .compatible = "marvell,pxa1908-apbcp" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, pxa1908_apbcp_match_table);
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static struct platform_driver pxa1908_apbcp_driver = {
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.probe = pxa1908_apbcp_probe,
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.driver = {
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.name = "pxa1908-apbcp",
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.of_match_table = pxa1908_apbcp_match_table
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}
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};
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module_platform_driver(pxa1908_apbcp_driver);
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MODULE_AUTHOR("Duje Mihanović <duje.mihanovic@skole.hr>");
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MODULE_DESCRIPTION("Marvell PXA1908 APBCP Clock Driver");
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MODULE_LICENSE("GPL");