Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
x86: fixup config space size of CPU functions for AMD family 11h
Impact: extend allowed configuration space access on 11h CPUs from 256 to 4K
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
authored by Andreas Herrmann and committed by Ingo Molnar ffd565a8 de90add3
+14
-11
arch/x86/pci/fixup.c
+14
-11
arch/x86/pci/fixup.c
···
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pci_siemens_interrupt_controller);
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/*
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* Regular PCI devices have 256 bytes, but AMD Family 10h Opteron ext config
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* have 4096 bytes. Even if the device is capable, that doesn't mean we can
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* access it. Maybe we don't have a way to generate extended config space
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* accesses. So check it
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*/
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static void fam10h_pci_cfg_space_size(struct pci_dev *dev)
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{
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dev->cfg_size = pci_cfg_space_size_ext(dev);
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}
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-
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, fam10h_pci_cfg_space_size);
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-
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, fam10h_pci_cfg_space_size);
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/*
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* SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
···
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pci_siemens_interrupt_controller);
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/*
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* Regular PCI devices have 256 bytes, but AMD Family 10h/11h CPUs have
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* 4096 bytes configuration space for each function of their processor
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* configuration space.
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*/
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+
static void amd_cpu_pci_cfg_space_size(struct pci_dev *dev)
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{
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dev->cfg_size = pci_cfg_space_size_ext(dev);
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}
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+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, amd_cpu_pci_cfg_space_size);
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+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, amd_cpu_pci_cfg_space_size);
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+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1300, amd_cpu_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1301, amd_cpu_pci_cfg_space_size);
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+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1302, amd_cpu_pci_cfg_space_size);
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+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1303, amd_cpu_pci_cfg_space_size);
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+
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1304, amd_cpu_pci_cfg_space_size);
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/*
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* SB600: Disable BAR1 on device 14.0 to avoid HPET resources from