tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu/jpeg2.6: Add jpeg2.6 support
Aldebaran is using jpeg2.6, and the main change is jpeg2.6 using
AMDGPU_MMHUB_0, and jpeg2.5 using AMDGPU_MMHUB_1.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
James Zhu
and committed by
Alex Deucher
ff6885ac
7ffe7238
+64
-2
+63
-2
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+63
-2
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
···
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.set_powergating_state = jpeg_v2_5_set_powergating_state,
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};
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+
static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
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.name = "jpeg_v2_6",
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+
.early_init = jpeg_v2_5_early_init,
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+
.late_init = NULL,
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+
.sw_init = jpeg_v2_5_sw_init,
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+
.sw_fini = jpeg_v2_5_sw_fini,
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+
.hw_init = jpeg_v2_5_hw_init,
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+
.hw_fini = jpeg_v2_5_hw_fini,
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+
.suspend = jpeg_v2_5_suspend,
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+
.resume = jpeg_v2_5_resume,
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+
.is_idle = jpeg_v2_5_is_idle,
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+
.wait_for_idle = jpeg_v2_5_wait_for_idle,
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+
.check_soft_reset = NULL,
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+
.pre_soft_reset = NULL,
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+
.soft_reset = NULL,
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+
.post_soft_reset = NULL,
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.set_clockgating_state = jpeg_v2_5_set_clockgating_state,
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+
.set_powergating_state = jpeg_v2_5_set_powergating_state,
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};
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+
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static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_JPEG,
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.align_mask = 0xf,
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.vmhub = AMDGPU_MMHUB_1,
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+
.get_rptr = jpeg_v2_5_dec_ring_get_rptr,
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+
.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
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+
.set_wptr = jpeg_v2_5_dec_ring_set_wptr,
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+
.emit_frame_size =
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SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
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SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
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8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
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+
18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
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+
8 + 16,
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+
.emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
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+
.emit_ib = jpeg_v2_0_dec_ring_emit_ib,
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+
.emit_fence = jpeg_v2_0_dec_ring_emit_fence,
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+
.emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
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+
.test_ring = amdgpu_jpeg_dec_ring_test_ring,
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+
.test_ib = amdgpu_jpeg_dec_ring_test_ib,
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+
.insert_nop = jpeg_v2_0_dec_ring_nop,
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.insert_start = jpeg_v2_0_dec_ring_insert_start,
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+
.insert_end = jpeg_v2_0_dec_ring_insert_end,
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+
.pad_ib = amdgpu_ring_generic_pad_ib,
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+
.begin_use = amdgpu_jpeg_ring_begin_use,
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+
.end_use = amdgpu_jpeg_ring_end_use,
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+
.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
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+
.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
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.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
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+
};
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+
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static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_JPEG,
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+
.align_mask = 0xf,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = jpeg_v2_5_dec_ring_get_rptr,
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.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
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.set_wptr = jpeg_v2_5_dec_ring_set_wptr,
···
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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-
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-
adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs;
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+
if (adev->asic_type == CHIP_ARCTURUS)
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adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs;
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+
else /* CHIP_ALDEBARAN */
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adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_6_dec_ring_vm_funcs;
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adev->jpeg.inst[i].ring_dec.me = i;
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DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i);
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}
···
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.minor = 5,
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.rev = 0,
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.funcs = &jpeg_v2_5_ip_funcs,
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+
};
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+
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const struct amdgpu_ip_block_version jpeg_v2_6_ip_block =
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{
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.type = AMD_IP_BLOCK_TYPE_JPEG,
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.major = 2,
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+
.minor = 6,
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.rev = 0,
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.funcs = &jpeg_v2_6_ip_funcs,
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};