Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

sh: Remove implicit sign extension from assembler immediates

The SH instruction set has several instructions which accept an 8 bit
immediate operand. For logical instructions this operand is zero extended,
for arithmetic instructions the operand is sign extended. After adding an
option to the assembler to check this, it was found that several pieces
of assembly code were assuming this behaviour, and in one case
getting it wrong.

So this patch explicitly sign extends any immediate operands, which makes
it obvious what is happening, and fixes the one case which got it wrong.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

authored by

Stuart Menefy and committed by
Paul Mundt
fea966f7 d724a9c9

+7 -6
+1 -1
arch/sh/boot/compressed/head_32.S
··· 22 22 bt clear_bss 23 23 sub r0, r2 24 24 mov.l bss_start_addr, r0 25 - mov #0xe0, r1 25 + mov #0xffffffe0, r1 26 26 and r1, r0 ! align cache line 27 27 mov.l text_start_addr, r3 28 28 mov r0, r1
+1 -1
arch/sh/include/asm/entry-macros.S
··· 7 7 .endm 8 8 9 9 .macro sti 10 - mov #0xf0, r11 10 + mov #0xfffffff0, r11 11 11 extu.b r11, r11 12 12 not r11, r11 13 13 stc sr, r10
+1 -1
arch/sh/kernel/cpu/sh3/entry.S
··· 257 257 ! 258 258 ! Calculate new SR value 259 259 mov k3, k2 ! original SR value 260 - mov #0xf0, k1 260 + mov #0xfffffff0, k1 261 261 extu.b k1, k1 262 262 not k1, k1 263 263 and k1, k2 ! Mask original SR value
+3 -2
arch/sh/kernel/entry-common.S
··· 98 98 99 99 mov #OFF_SR, r0 100 100 mov.l @(r0,r15), r0 ! get status register 101 - and #0xf0, r0 ! interrupts off (exception path)? 102 - cmp/eq #0xf0, r0 101 + shlr r0 102 + and #(0xf0>>1), r0 ! interrupts off (exception path)? 103 + cmp/eq #(0xf0>>1), r0 103 104 bt noresched 104 105 mov.l 3f, r0 105 106 jsr @r0 ! call preempt_schedule_irq
+1 -1
arch/sh/lib/clear_page.S
··· 57 57 ENTRY(__clear_user) 58 58 ! 59 59 mov #0, r0 60 - mov #0xe0, r1 ! 0xffffffe0 60 + mov #0xffffffe0, r1 61 61 ! 62 62 ! r4..(r4+31)&~32 -------- not aligned [ Area 0 ] 63 63 ! (r4+31)&~32..(r4+r5)&~32 -------- aligned [ Area 1 ]