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ARM: dts: imx6q-dhcom: Cleanup of the devicetrees

Following cleanups of the devicetrees done, no change in function:
- Remove parentheses from the license
- Update copyright date
- Alphabetical sorting
- Add comments
- Update pinctrl names
- Hex values in lower case
- Set 3rd values of fixed regulators gpio property to 0
- Replace interrupt type with a define
- Remove superfluous property max-speed from the fec node

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

authored by

Christoph Niedermaier and committed by
Shawn Guo fea4e8a9 1f58e94c

+217 -201
+45 -45
arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
··· 1 - // SPDX-License-Identifier: (GPL-2.0+) 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 /* 3 - * Copyright (C) 2015 DH electronics GmbH 3 + * Copyright (C) 2015-2021 DH electronics GmbH 4 4 * Copyright (C) 2018 Marek Vasut <marex@denx.de> 5 5 */ 6 6 ··· 18 18 }; 19 19 20 20 clk_ext_audio_codec: clock-codec { 21 - compatible = "fixed-clock"; 22 21 #clock-cells = <0>; 23 22 clock-frequency = <24000000>; 23 + compatible = "fixed-clock"; 24 24 }; 25 25 26 26 display_bl: display-bl { 27 - compatible = "pwm-backlight"; 28 - pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; 29 27 brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; 28 + compatible = "pwm-backlight"; 30 29 default-brightness-level = <8>; 31 - enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; 30 + enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */ 31 + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; 32 32 status = "okay"; 33 33 }; 34 34 35 35 lcd_display: disp0 { 36 - compatible = "fsl,imx-parallel-display"; 37 36 #address-cells = <1>; 38 37 #size-cells = <0>; 38 + compatible = "fsl,imx-parallel-display"; 39 39 interface-pix-fmt = "rgb24"; 40 - pinctrl-names = "default"; 41 40 pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>; 41 + pinctrl-names = "default"; 42 42 status = "okay"; 43 43 44 44 port@0 { ··· 63 63 compatible = "gpio-keys"; 64 64 65 65 button-0 { 66 + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */ 66 67 label = "TA1-GPIO-A"; 67 68 linux,code = <KEY_A>; 68 - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; 69 69 pinctrl-0 = <&pinctrl_dhcom_a>; 70 70 pinctrl-names = "default"; 71 71 wakeup-source; 72 72 }; 73 73 74 74 button-1 { 75 + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */ 75 76 label = "TA2-GPIO-B"; 76 77 linux,code = <KEY_B>; 77 - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 78 78 pinctrl-0 = <&pinctrl_dhcom_b>; 79 79 pinctrl-names = "default"; 80 80 wakeup-source; 81 81 }; 82 82 83 83 button-2 { 84 + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */ 84 85 label = "TA3-GPIO-C"; 85 86 linux,code = <KEY_C>; 86 - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 87 87 pinctrl-0 = <&pinctrl_dhcom_c>; 88 88 pinctrl-names = "default"; 89 89 wakeup-source; 90 90 }; 91 91 92 92 button-3 { 93 + gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */ 93 94 label = "TA4-GPIO-D"; 94 95 linux,code = <KEY_D>; 95 - gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; 96 96 pinctrl-0 = <&pinctrl_dhcom_d>; 97 97 pinctrl-names = "default"; 98 98 wakeup-source; ··· 108 108 */ 109 109 led-5 { 110 110 color = <LED_COLOR_ID_GREEN>; 111 + default-state = "off"; 111 112 function = LED_FUNCTION_INDICATOR; 112 113 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */ 113 - default-state = "off"; 114 114 pinctrl-0 = <&pinctrl_dhcom_e>; 115 115 pinctrl-names = "default"; 116 116 status = "disabled"; ··· 118 118 119 119 led-6 { 120 120 color = <LED_COLOR_ID_GREEN>; 121 + default-state = "off"; 121 122 function = LED_FUNCTION_INDICATOR; 122 123 gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */ 123 - default-state = "off"; 124 124 pinctrl-0 = <&pinctrl_dhcom_f>; 125 125 pinctrl-names = "default"; 126 126 }; 127 127 128 128 led-7 { 129 129 color = <LED_COLOR_ID_GREEN>; 130 + default-state = "off"; 130 131 function = LED_FUNCTION_INDICATOR; 131 132 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */ 132 - default-state = "off"; 133 133 pinctrl-0 = <&pinctrl_dhcom_h>; 134 134 pinctrl-names = "default"; 135 135 }; 136 136 137 137 led-8 { 138 138 color = <LED_COLOR_ID_GREEN>; 139 + default-state = "off"; 139 140 function = LED_FUNCTION_INDICATOR; 140 141 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ 141 - default-state = "off"; 142 142 pinctrl-0 = <&pinctrl_dhcom_i>; 143 143 pinctrl-names = "default"; 144 144 }; 145 145 }; 146 146 147 147 panel { 148 - compatible = "edt,etm0700g0edh6"; 149 148 backlight = <&display_bl>; 149 + compatible = "edt,etm0700g0edh6"; 150 150 151 151 port { 152 152 lcd_panel_in: endpoint { ··· 156 156 }; 157 157 158 158 sound { 159 - compatible = "fsl,imx-audio-sgtl5000"; 160 - model = "imx-sgtl5000"; 161 - ssi-controller = <&ssi1>; 162 159 audio-codec = <&sgtl5000>; 163 160 audio-routing = 164 161 "MIC_IN", "Mic Jack", 165 162 "Mic Jack", "Mic Bias", 166 163 "LINE_IN", "Line In Jack", 167 164 "Headphone Jack", "HP_OUT"; 168 - mux-int-port = <1>; 165 + compatible = "fsl,imx-audio-sgtl5000"; 166 + model = "imx-sgtl5000"; 169 167 mux-ext-port = <3>; 168 + mux-int-port = <1>; 169 + ssi-controller = <&ssi1>; 170 170 }; 171 171 }; 172 172 173 173 &audmux { 174 - pinctrl-names = "default"; 175 174 pinctrl-0 = <&pinctrl_audmux_ext>; 175 + pinctrl-names = "default"; 176 176 status = "okay"; 177 177 }; 178 178 ··· 189 189 &fec { 190 190 phy-mode = "rgmii"; 191 191 phy-handle = <&ethphy7>; 192 - pinctrl-names = "default"; 193 192 pinctrl-0 = <&pinctrl_enet_1G>; 193 + pinctrl-names = "default"; 194 194 status = "okay"; 195 195 196 196 mdio { ··· 204 204 pinctrl-0 = <&pinctrl_ethphy7>; 205 205 pinctrl-names = "default"; 206 206 reg = <7>; 207 - reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; 208 207 reset-assert-us = <1000>; 209 208 reset-deassert-us = <1000>; 209 + reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; 210 210 rxc-skew-ps = <3000>; 211 211 rxd0-skew-ps = <0>; 212 212 rxd1-skew-ps = <0>; 213 213 rxd2-skew-ps = <0>; 214 214 rxd3-skew-ps = <0>; 215 + rxdv-skew-ps = <0>; 215 216 txc-skew-ps = <3000>; 216 217 txd0-skew-ps = <0>; 217 218 txd1-skew-ps = <0>; 218 219 txd2-skew-ps = <0>; 219 220 txd3-skew-ps = <0>; 220 - rxdv-skew-ps = <0>; 221 221 txen-skew-ps = <0>; 222 222 }; 223 223 }; ··· 230 230 231 231 &i2c2 { 232 232 sgtl5000: codec@a { 233 - compatible = "fsl,sgtl5000"; 234 - reg = <0x0a>; 235 233 #sound-dai-cells = <0>; 236 234 clocks = <&clk_ext_audio_codec>; 235 + compatible = "fsl,sgtl5000"; 236 + reg = <0x0a>; 237 237 VDDA-supply = <&reg_3p3v>; 238 238 VDDIO-supply = <&sw2_reg>; 239 239 }; 240 240 241 241 touchscreen@38 { 242 - pinctrl-names = "default"; 243 - pinctrl-0 = <&pinctrl_dhcom_e>; 244 242 compatible = "edt,edt-ft5406"; 245 - reg = <0x38>; 246 243 interrupt-parent = <&gpio4>; 247 244 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ 245 + pinctrl-0 = <&pinctrl_dhcom_e>; 246 + pinctrl-names = "default"; 247 + reg = <0x38>; 248 248 }; 249 249 }; 250 250 ··· 254 254 255 255 &pcie { 256 256 pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>; 257 - reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; 257 + reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */ 258 258 status = "okay"; 259 259 }; 260 260 261 261 &pwm1 { 262 - pinctrl-names = "default"; 263 262 pinctrl-0 = <&pinctrl_pwm1>; 263 + pinctrl-names = "default"; 264 264 status = "okay"; 265 265 }; 266 266 ··· 272 272 status = "okay"; 273 273 }; 274 274 275 - &usdhc3 { 275 + &usdhc3 { /* Micro SD card on module */ 276 276 status = "okay"; 277 277 }; 278 278 279 279 &iomuxc { 280 - pinctrl-names = "default"; 281 280 pinctrl-0 = < 282 281 /* 283 282 * The following DHCOM GPIOs are used on this board. ··· 299 300 &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u 300 301 &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int 301 302 >; 303 + pinctrl-names = "default"; 302 304 303 305 pinctrl_audmux_ext: audmux-ext-grp { 304 306 fsl,pins = < 305 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 306 307 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 307 308 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 308 309 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 310 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 309 311 >; 310 312 }; 311 313 312 314 pinctrl_enet_1G: enet-1G-grp { 313 315 fsl,pins = < 314 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 315 316 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 316 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 317 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 318 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 319 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 320 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 321 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 317 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 322 318 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 323 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 324 319 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 325 320 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 326 321 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 327 322 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 328 323 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 324 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 325 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 326 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 327 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 328 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 329 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 330 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 329 331 >; 330 332 }; 331 333 332 334 pinctrl_ethphy7: ethphy7-grp { 333 335 fsl,pins = < 336 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */ 334 337 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */ 335 338 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ 336 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */ 337 339 >; 338 340 }; 339 341 340 342 pinctrl_ipu1_lcdif: ipu1-lcdif-grp { 341 343 fsl,pins = < 342 344 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 343 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 344 345 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 345 346 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 347 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 346 348 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 347 349 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 348 350 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
+172 -156
arch/arm/boot/dts/imx6q-dhcom-som.dtsi
··· 1 - // SPDX-License-Identifier: (GPL-2.0+) 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 /* 3 - * Copyright (C) 2015 DH electronics GmbH 3 + * Copyright (C) 2015-2021 DH electronics GmbH 4 4 * Copyright (C) 2018 Marek Vasut <marex@denx.de> 5 5 */ 6 6 ··· 28 28 serial4 = &uart3; 29 29 }; 30 30 31 - memory@10000000 { 31 + memory@10000000 { /* Appropriate memory size will be filled by U-Boot */ 32 32 device_type = "memory"; 33 33 reg = <0x10000000 0x20000000>; 34 34 }; 35 35 36 + reg_3p3v: regulator-3P3V { 37 + compatible = "regulator-fixed"; 38 + regulator-always-on; 39 + regulator-min-microvolt = <3300000>; 40 + regulator-max-microvolt = <3300000>; 41 + regulator-name = "3P3V"; 42 + }; 43 + 36 44 reg_eth_vio: regulator-eth-vio { 37 45 compatible = "regulator-fixed"; 38 - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; 46 + gpio = <&gpio1 7 0>; 39 47 pinctrl-0 = <&pinctrl_enet_vio>; 40 48 pinctrl-names = "default"; 41 49 regulator-always-on; ··· 62 54 regulator-name = "latch_oe_on"; 63 55 }; 64 56 65 - reg_usb_otg_vbus: regulator-usb-otg-vbus { 66 - compatible = "regulator-fixed"; 67 - regulator-name = "usb_otg_vbus"; 68 - regulator-min-microvolt = <5000000>; 69 - regulator-max-microvolt = <5000000>; 70 - }; 71 - 72 57 reg_usb_h1_vbus: regulator-usb-h1-vbus { 73 58 compatible = "regulator-fixed"; 74 - regulator-name = "usb_h1_vbus"; 59 + enable-active-high; 60 + gpio = <&gpio3 31 0>; 75 61 regulator-min-microvolt = <5000000>; 76 62 regulator-max-microvolt = <5000000>; 77 - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; 78 - enable-active-high; 63 + regulator-name = "usb_h1_vbus"; 79 64 }; 80 65 81 - reg_3p3v: regulator-3P3V { 66 + reg_usb_otg_vbus: regulator-usb-otg-vbus { 82 67 compatible = "regulator-fixed"; 83 - regulator-name = "3P3V"; 84 - regulator-min-microvolt = <3300000>; 85 - regulator-max-microvolt = <3300000>; 86 - regulator-always-on; 68 + regulator-min-microvolt = <5000000>; 69 + regulator-max-microvolt = <5000000>; 70 + regulator-name = "usb_otg_vbus"; 87 71 }; 88 72 }; 89 73 90 74 &can1 { 91 - pinctrl-names = "default"; 92 75 pinctrl-0 = <&pinctrl_flexcan1>; 76 + pinctrl-names = "default"; 93 77 }; 94 78 79 + /* 80 + * Special hardware required which uses the pins from micro SD card. The pins 81 + * SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 Tx 82 + * and Rx are output on DHCOM uart1 rts/cts pins. So to enable can2 on the board 83 + * device tree file, you also need to disable the micro SD card and the uart1 84 + * rts/cts have to be disabled or output on other DHCOM pins. 85 + */ 95 86 &can2 { 96 - pinctrl-names = "default"; 97 87 pinctrl-0 = <&pinctrl_flexcan2>; 88 + pinctrl-names = "default"; 98 89 }; 99 90 100 91 &ecspi1 { 101 92 cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>; 102 - pinctrl-names = "default"; 103 93 pinctrl-0 = <&pinctrl_ecspi1>; 94 + pinctrl-names = "default"; 104 95 status = "okay"; 105 96 106 - flash@0 { /* S25FL116K */ 97 + flash@0 { /* S25FL116K */ 107 98 #address-cells = <1>; 108 99 #size-cells = <1>; 109 100 compatible = "jedec,spi-nor"; 110 - spi-max-frequency = <50000000>; 111 - reg = <0>; 112 101 m25p,fast-read; 102 + reg = <0>; 103 + spi-max-frequency = <50000000>; 113 104 }; 114 105 }; 115 106 116 107 &ecspi2 { 117 108 cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; 118 - pinctrl-names = "default"; 119 109 pinctrl-0 = <&pinctrl_ecspi2>; 110 + pinctrl-names = "default"; 120 111 status = "okay"; 121 112 }; 122 113 123 114 &fec { 124 - pinctrl-names = "default"; 125 - pinctrl-0 = <&pinctrl_enet_100M>; 126 115 phy-mode = "rmii"; 127 116 phy-handle = <&ethphy0>; 117 + pinctrl-0 = <&pinctrl_enet_100M>; 118 + pinctrl-names = "default"; 128 119 status = "okay"; 129 120 130 121 mdio { 131 122 #address-cells = <1>; 132 123 #size-cells = <0>; 133 124 134 - ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ 125 + ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ 135 126 compatible = "ethernet-phy-ieee802.3-c22"; 136 127 interrupt-parent = <&gpio4>; 137 128 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 138 - max-speed = <100>; 139 129 pinctrl-0 = <&pinctrl_ethphy0>; 140 130 pinctrl-names = "default"; 141 131 reg = <0>; 142 - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 143 132 reset-assert-us = <1000>; 144 133 reset-deassert-us = <1000>; 134 + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 145 135 smsc,disable-energy-detect; /* Make plugin detection reliable */ 146 136 }; 147 137 }; ··· 202 196 }; 203 197 204 198 &i2c1 { 199 + /* 200 + * Info: According to erratum ERR007805 clock frequency limit is 375000. 201 + * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2]. 202 + * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf 203 + * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf 204 + */ 205 205 clock-frequency = <100000>; 206 - pinctrl-names = "default", "gpio"; 207 206 pinctrl-0 = <&pinctrl_i2c1>; 208 207 pinctrl-1 = <&pinctrl_i2c1_gpio>; 208 + pinctrl-names = "default", "gpio"; 209 209 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 210 210 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 211 211 status = "okay"; 212 212 }; 213 213 214 214 &i2c2 { 215 + /* Info: Clock frequency limit is 375000 (for details see i2c1) */ 215 216 clock-frequency = <100000>; 216 - pinctrl-names = "default", "gpio"; 217 217 pinctrl-0 = <&pinctrl_i2c2>; 218 218 pinctrl-1 = <&pinctrl_i2c2_gpio>; 219 + pinctrl-names = "default", "gpio"; 219 220 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 220 221 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 221 222 status = "okay"; 222 223 }; 223 224 224 225 &i2c3 { 226 + /* Info: Clock frequency limit is 375000 (for details see i2c1) */ 225 227 clock-frequency = <100000>; 226 - pinctrl-names = "default", "gpio"; 227 228 pinctrl-0 = <&pinctrl_i2c3>; 228 229 pinctrl-1 = <&pinctrl_i2c3_gpio>; 230 + pinctrl-names = "default", "gpio"; 229 231 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 230 232 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 231 233 status = "okay"; 232 234 233 235 ltc3676: pmic@3c { 234 236 compatible = "lltc,ltc3676"; 235 - pinctrl-names = "default"; 236 - pinctrl-0 = <&pinctrl_pmic_hw300>; 237 - reg = <0x3c>; 238 237 interrupt-parent = <&gpio5>; 239 238 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 239 + pinctrl-0 = <&pinctrl_pmic>; 240 + pinctrl-names = "default"; 241 + reg = <0x3c>; 240 242 241 243 regulators { 242 244 sw1_reg: sw1 { 243 - regulator-min-microvolt = <787500>; 244 - regulator-max-microvolt = <1527272>; 245 245 lltc,fb-voltage-divider = <100000 110000>; 246 - regulator-suspend-mem-microvolt = <1040000>; 247 - regulator-ramp-delay = <7000>; 248 - regulator-boot-on; 249 246 regulator-always-on; 247 + regulator-boot-on; 248 + regulator-max-microvolt = <1527272>; 249 + regulator-min-microvolt = <787500>; 250 + regulator-ramp-delay = <7000>; 251 + regulator-suspend-mem-microvolt = <1040000>; 250 252 }; 251 253 252 254 sw2_reg: sw2 { 253 - regulator-min-microvolt = <1885714>; 254 - regulator-max-microvolt = <3657142>; 255 255 lltc,fb-voltage-divider = <100000 28000>; 256 - regulator-ramp-delay = <7000>; 257 - regulator-boot-on; 258 256 regulator-always-on; 257 + regulator-boot-on; 258 + regulator-max-microvolt = <3657142>; 259 + regulator-min-microvolt = <1885714>; 260 + regulator-ramp-delay = <7000>; 259 261 }; 260 262 261 263 sw3_reg: sw3 { 262 - regulator-min-microvolt = <787500>; 263 - regulator-max-microvolt = <1527272>; 264 264 lltc,fb-voltage-divider = <100000 110000>; 265 - regulator-suspend-mem-microvolt = <980000>; 266 - regulator-ramp-delay = <7000>; 267 - regulator-boot-on; 268 265 regulator-always-on; 266 + regulator-boot-on; 267 + regulator-max-microvolt = <1527272>; 268 + regulator-min-microvolt = <787500>; 269 + regulator-ramp-delay = <7000>; 270 + regulator-suspend-mem-microvolt = <980000>; 269 271 }; 270 272 271 273 sw4_reg: sw4 { 272 - regulator-min-microvolt = <855571>; 273 - regulator-max-microvolt = <1659291>; 274 274 lltc,fb-voltage-divider = <100000 93100>; 275 - regulator-ramp-delay = <7000>; 276 - regulator-boot-on; 277 275 regulator-always-on; 276 + regulator-boot-on; 277 + regulator-max-microvolt = <1659291>; 278 + regulator-min-microvolt = <855571>; 279 + regulator-ramp-delay = <7000>; 278 280 }; 279 281 280 282 ldo1_reg: ldo1 { 281 - regulator-min-microvolt = <3240306>; 282 - regulator-max-microvolt = <3240306>; 283 283 lltc,fb-voltage-divider = <102000 29400>; 284 - regulator-boot-on; 285 284 regulator-always-on; 285 + regulator-boot-on; 286 + regulator-max-microvolt = <3240306>; 287 + regulator-min-microvolt = <3240306>; 286 288 }; 287 289 288 290 ldo2_reg: ldo2 { 289 - regulator-min-microvolt = <2484708>; 290 - regulator-max-microvolt = <2484708>; 291 291 lltc,fb-voltage-divider = <100000 41200>; 292 - regulator-boot-on; 293 292 regulator-always-on; 293 + regulator-boot-on; 294 + regulator-max-microvolt = <2484708>; 295 + regulator-min-microvolt = <2484708>; 294 296 }; 295 297 }; 296 298 }; 297 299 298 - touchscreen@49 { /* TSC2004 */ 300 + touchscreen@49 { /* TSC2004 */ 299 301 compatible = "ti,tsc2004"; 302 + interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>; 303 + pinctrl-0 = <&pinctrl_tsc2004>; 304 + pinctrl-names = "default"; 300 305 reg = <0x49>; 301 306 vio-supply = <&reg_3p3v>; 302 - pinctrl-names = "default"; 303 - pinctrl-0 = <&pinctrl_tsc2004_hw300>; 304 - interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>; 305 307 status = "disabled"; 306 308 }; 307 309 308 310 eeprom@50 { 309 311 compatible = "atmel,24c02"; 310 - reg = <0x50>; 311 312 pagesize = <16>; 313 + reg = <0x50>; 312 314 }; 313 315 314 316 rtc_i2c: rtc@56 { 315 317 compatible = "microcrystal,rv3029"; 316 - pinctrl-names = "default"; 317 - pinctrl-0 = <&pinctrl_rtc_hw300>; 318 - reg = <0x56>; 319 318 interrupt-parent = <&gpio7>; 320 - interrupts = <12 2>; 319 + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; 320 + pinctrl-0 = <&pinctrl_rtc>; 321 + pinctrl-names = "default"; 322 + reg = <0x56>; 321 323 }; 322 324 }; 323 325 324 326 &pcie { 325 - pinctrl-names = "default"; 326 327 pinctrl-0 = <&pinctrl_pcie>; 328 + pinctrl-names = "default"; 327 329 }; 328 330 329 331 &reg_arm { 330 332 vin-supply = <&sw3_reg>; 331 333 }; 332 334 333 - &reg_soc { 335 + &reg_pu { 334 336 vin-supply = <&sw1_reg>; 335 337 }; 336 338 337 - &reg_pu { 339 + &reg_soc { 338 340 vin-supply = <&sw1_reg>; 339 341 }; 340 342 ··· 354 340 vin-supply = <&sw2_reg>; 355 341 }; 356 342 357 - &uart1 { 358 - pinctrl-names = "default"; 359 - pinctrl-0 = <&pinctrl_uart1>; 360 - uart-has-rtscts; 361 - dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 362 - dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 343 + &uart1 { /* DHCOM UART1 */ 363 344 dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 345 + dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 346 + dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 364 347 rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; 348 + pinctrl-0 = <&pinctrl_uart1>; 349 + pinctrl-names = "default"; 350 + uart-has-rtscts; 365 351 status = "okay"; 366 352 }; 367 353 368 - &uart4 { 369 - pinctrl-names = "default"; 354 + &uart4 { /* DHCOM UART3 */ 370 355 pinctrl-0 = <&pinctrl_uart4>; 356 + pinctrl-names = "default"; 371 357 status = "okay"; 372 358 }; 373 359 374 - &uart5 { 375 - pinctrl-names = "default"; 360 + &uart5 { /* DHCOM UART2 */ 376 361 pinctrl-0 = <&pinctrl_uart5>; 362 + pinctrl-names = "default"; 377 363 uart-has-rtscts; 378 364 status = "okay"; 379 365 }; 380 366 381 367 &usbh1 { 382 - pinctrl-names = "default"; 383 - pinctrl-0 = <&pinctrl_usbh1>; 384 - vbus-supply = <&reg_usb_h1_vbus>; 385 368 dr_mode = "host"; 369 + pinctrl-0 = <&pinctrl_usbh1>; 370 + pinctrl-names = "default"; 371 + vbus-supply = <&reg_usb_h1_vbus>; 386 372 status = "okay"; 387 373 }; 388 374 389 375 &usbotg { 390 - vbus-supply = <&reg_usb_otg_vbus>; 391 - pinctrl-names = "default"; 392 - pinctrl-0 = <&pinctrl_usbotg>; 393 376 disable-over-current; 394 377 dr_mode = "otg"; 378 + pinctrl-0 = <&pinctrl_usbotg>; 379 + pinctrl-names = "default"; 380 + vbus-supply = <&reg_usb_otg_vbus>; 395 381 status = "okay"; 396 382 }; 397 383 398 - &usdhc2 { 399 - pinctrl-names = "default"; 400 - pinctrl-0 = <&pinctrl_usdhc2>; 384 + &usdhc2 { /* External SD card via DHCOM */ 401 385 cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; 402 386 keep-power-in-suspend; 387 + pinctrl-0 = <&pinctrl_usdhc2>; 388 + pinctrl-names = "default"; 403 389 status = "okay"; 404 390 }; 405 391 406 - &usdhc3 { 407 - pinctrl-names = "default"; 408 - pinctrl-0 = <&pinctrl_usdhc3>; 392 + &usdhc3 { /* Micro SD card on module */ 409 393 cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; 410 394 fsl,wp-controller; 411 395 keep-power-in-suspend; 396 + pinctrl-0 = <&pinctrl_usdhc3>; 397 + pinctrl-names = "default"; 412 398 status = "disabled"; 413 399 }; 414 400 415 - &usdhc4 { 416 - pinctrl-names = "default"; 417 - pinctrl-0 = <&pinctrl_usdhc4>; 418 - non-removable; 401 + &usdhc4 { /* eMMC on module */ 419 402 bus-width = <8>; 420 - no-1-8-v; 421 403 keep-power-in-suspend; 404 + no-1-8-v; 405 + non-removable; 406 + pinctrl-0 = <&pinctrl_usdhc4>; 407 + pinctrl-names = "default"; 422 408 status = "okay"; 423 409 }; 424 410 ··· 426 412 #address-cells = <2>; 427 413 #size-cells = <1>; 428 414 fsl,weim-cs-gpr = <&gpr>; 429 - pinctrl-names = "default"; 430 415 pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>; 416 + pinctrl-names = "default"; 431 417 /* It is necessary to setup 2x 64MB otherwise setting gpr fails */ 432 418 ranges = <0 0 0x08000000 0x04000000>, /* CS0 */ 433 419 <1 0 0x0c000000 0x04000000>; /* CS1 */ ··· 435 421 }; 436 422 437 423 &iomuxc { 438 - pinctrl-names = "default"; 439 424 pinctrl-0 = < 440 425 &pinctrl_hog_base 441 426 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c ··· 446 433 &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u 447 434 &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int 448 435 >; 436 + pinctrl-names = "default"; 449 437 450 438 pinctrl_hog_base: hog-base-grp { 451 439 fsl,pins = < 452 - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0 453 - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0 454 - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0 440 + /* GPIOs for memory coding */ 455 441 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0 456 442 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0 443 + /* GPIOs for hardware coding */ 444 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0 445 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0 446 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0 457 447 >; 458 448 }; 459 449 ··· 559 543 560 544 pinctrl_ecspi1: ecspi1-grp { 561 545 fsl,pins = < 546 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 562 547 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 563 548 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 564 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 565 549 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 566 550 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 567 551 >; ··· 569 553 570 554 pinctrl_ecspi2: ecspi2-grp { 571 555 fsl,pins = < 572 - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 573 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 574 556 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 557 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 558 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 575 559 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 576 560 >; 577 561 }; 578 562 579 563 pinctrl_enet_100M: enet-100M-grp { 580 564 fsl,pins = < 581 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 582 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 583 565 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 566 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 567 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 584 568 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 585 569 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 586 570 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 ··· 606 590 607 591 pinctrl_flexcan1: flexcan1-grp { 608 592 fsl,pins = < 609 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 610 593 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 594 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 611 595 >; 612 596 }; 613 597 ··· 660 644 >; 661 645 }; 662 646 663 - pinctrl_pmic_hw300: pmic-hw300-grp { 664 - fsl,pins = < 665 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0 666 - >; 667 - }; 668 - 669 - pinctrl_rtc_hw300: rtc-hw300-grp { 670 - fsl,pins = < 671 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120B0 672 - >; 673 - }; 674 - 675 - pinctrl_tsc2004_hw300: tsc2004-hw300-grp { 676 - fsl,pins = < 677 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120B0 678 - >; 679 - }; 680 - 681 647 pinctrl_pcie: pcie-grp { 682 648 fsl,pins = < 683 649 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */ 684 650 >; 685 651 }; 686 652 653 + pinctrl_pmic: pmic-grp { 654 + fsl,pins = < 655 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 656 + >; 657 + }; 658 + 659 + pinctrl_rtc: rtc-grp { 660 + fsl,pins = < 661 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0 662 + >; 663 + }; 664 + 665 + pinctrl_tsc2004: tsc2004-grp { 666 + fsl,pins = < 667 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0 668 + >; 669 + }; 670 + 687 671 pinctrl_uart1: uart1-grp { 688 672 fsl,pins = < 689 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 690 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 691 - MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 692 673 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1 674 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 693 675 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1 694 676 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1 695 677 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1 696 678 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1 679 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 680 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 697 681 >; 698 682 }; 699 683 ··· 715 699 716 700 pinctrl_usbh1: usbh1-grp { 717 701 fsl,pins = < 718 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120B0 702 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0 719 703 >; 720 704 }; 721 705 ··· 727 711 728 712 pinctrl_usdhc2: usdhc2-grp { 729 713 fsl,pins = < 730 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 714 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0 731 715 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 716 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 732 717 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 733 718 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 734 719 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 735 720 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 736 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120B0 737 721 >; 738 722 }; 739 723 740 724 pinctrl_usdhc3: usdhc3-grp { 741 725 fsl,pins = < 742 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 743 726 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 727 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 744 728 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 745 729 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 746 730 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 747 731 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 748 - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120B0 732 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0 749 733 >; 750 734 }; 751 735 752 736 pinctrl_usdhc4: usdhc4-grp { 753 737 fsl,pins = < 754 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 755 738 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 739 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 756 740 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 757 741 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 758 742 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 ··· 766 750 767 751 pinctrl_weim: weim-grp { 768 752 fsl,pins = < 753 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6 754 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6 755 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6 756 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6 757 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6 758 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6 759 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6 760 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6 761 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6 762 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6 763 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6 764 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6 765 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6 766 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6 767 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6 768 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6 769 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 770 + MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */ 769 771 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6 770 772 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */ 771 - MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */ 772 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 773 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6 774 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6 775 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6 776 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6 777 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6 778 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6 779 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6 780 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6 781 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6 782 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6 783 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6 784 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6 785 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6 786 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6 787 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6 788 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6 789 773 >; 790 774 }; 791 775