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spi: zynq: Add DT bindings documentation for Zynq Ultrascale+ MPSoC GQSPI controller
Add bindings documentation for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Ranjit Waghmode
and committed by
Mark Brown
fe8e48ad
b787f68c
+26
+26
Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
+26
Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
···
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Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
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-------------------------------------------------------------------
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Required properties:
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- compatible : Should be "xlnx,zynqmp-qspi-1.0".
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- reg : Physical base address and size of GQSPI registers map.
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- interrupts : Property with a value describing the interrupt
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number.
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- interrupt-parent : Must be core interrupt controller.
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- clock-names : List of input clock names - "ref_clk", "pclk"
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(See clock bindings for details).
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- clocks : Clock phandles (see clock bindings for details).
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Optional properties:
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- num-cs : Number of chip selects used.
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Example:
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qspi: spi@ff0f0000 {
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compatible = "xlnx,zynqmp-qspi-1.0";
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clock-names = "ref_clk", "pclk";
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clocks = <&misc_clk &misc_clk>;
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interrupts = <0 15 4>;
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interrupt-parent = <&gic>;
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num-cs = <1>;
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reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;
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};