tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: display: tegra: Convert to json-schema
Convert the Tegra host1x controller bindings from the free-form text
format to json-schema.
This also adds the missing display-hub DT bindings that were not
previously documented.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
+2522
-775
-41
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
-41
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
···
1
-
NVIDIA Tegra MIPI pad calibration controller
2
-
3
-
Required properties:
4
-
- compatible: "nvidia,tegra<chip>-mipi"
5
-
- reg: Physical base address and length of the controller's registers.
6
-
- clocks: Must contain an entry for each entry in clock-names.
7
-
See ../clocks/clock-bindings.txt for details.
8
-
- clock-names: Must include the following entries:
9
-
- mipi-cal
10
-
- #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
11
-
that need to be calibrated for a given device.
12
-
13
-
User nodes need to contain an nvidia,mipi-calibrate property that has a
14
-
phandle to refer to the calibration controller node and a bitmask of the pads
15
-
that need to be calibrated.
16
-
17
-
Example:
18
-
19
-
mipi: mipi@700e3000 {
20
-
compatible = "nvidia,tegra114-mipi";
21
-
reg = <0x700e3000 0x100>;
22
-
clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
23
-
clock-names = "mipi-cal";
24
-
#nvidia,mipi-calibrate-cells = <1>;
25
-
};
26
-
27
-
...
28
-
29
-
host1x@50000000 {
30
-
...
31
-
32
-
dsi@54300000 {
33
-
...
34
-
35
-
nvidia,mipi-calibrate = <&mipi 0x060>;
36
-
37
-
...
38
-
};
39
-
40
-
...
41
-
};
+74
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
+74
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra MIPI pad calibration controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^mipi@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra114-mipi
20
+
- nvidia,tegra210-mipi
21
+
- nvidia,tegra186-mipi
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: module clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: mipi-cal
33
+
34
+
power-domains:
35
+
maxItems: 1
36
+
37
+
"#nvidia,mipi-calibrate-cells":
38
+
description: The number of cells in a MIPI calibration specifier.
39
+
Should be 1. The single cell specifies a bitmask of the pads that
40
+
need to be calibrated for a given device.
41
+
$ref: "/schemas/types.yaml#/definitions/uint32"
42
+
const: 1
43
+
44
+
additionalProperties: false
45
+
46
+
required:
47
+
- compatible
48
+
- reg
49
+
- clocks
50
+
- "#nvidia,mipi-calibrate-cells"
51
+
52
+
examples:
53
+
- |
54
+
#include <dt-bindings/clock/tegra114-car.h>
55
+
56
+
mipi@700e3000 {
57
+
compatible = "nvidia,tegra114-mipi";
58
+
reg = <0x700e3000 0x100>;
59
+
clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
60
+
clock-names = "mipi-cal";
61
+
#nvidia,mipi-calibrate-cells = <1>;
62
+
};
63
+
64
+
dsia: dsi@54300000 {
65
+
compatible = "nvidia,tegra114-dsi";
66
+
reg = <0x54300000 0x00040000>;
67
+
clocks = <&tegra_car TEGRA114_CLK_DSIA>,
68
+
<&tegra_car TEGRA114_CLK_DSIALP>,
69
+
<&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
70
+
clock-names = "dsi", "lp", "parent";
71
+
resets = <&tegra_car 48>;
72
+
reset-names = "dsi";
73
+
nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
74
+
};
+152
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
+152
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra DisplayPort AUX Interface
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: |
14
+
The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
15
+
pins which can be assigned to either the DPAUX channel or to an I2C
16
+
controller.
17
+
18
+
When configured for DisplayPort AUX operation, the DPAUX controller
19
+
can also be used to communicate with a DisplayPort device using the
20
+
AUX channel.
21
+
22
+
properties:
23
+
$nodename:
24
+
pattern: "^dpaux@[0-9a-f]+$"
25
+
26
+
compatible:
27
+
oneOf:
28
+
- enum:
29
+
- nvidia,tegra124-dpaux
30
+
- nvidia,tegra210-dpaux
31
+
- nvidia,tegra186-dpaux
32
+
- nvidia,tegra194-dpaux
33
+
34
+
- items:
35
+
- const: nvidia,tegra132-dpaux
36
+
- const: nvidia,tegra124-dpaux
37
+
38
+
reg:
39
+
maxItems: 1
40
+
41
+
interrupts:
42
+
maxItems: 1
43
+
44
+
clocks:
45
+
items:
46
+
- description: clock input for the DPAUX hardware
47
+
- description: reference clock
48
+
49
+
clock-names:
50
+
items:
51
+
- const: dpaux
52
+
- const: parent
53
+
54
+
resets:
55
+
items:
56
+
- description: module reset
57
+
58
+
reset-names:
59
+
items:
60
+
- const: dpaux
61
+
62
+
power-domains:
63
+
maxItems: 1
64
+
65
+
i2c-bus:
66
+
description: Subnode where I2C slave devices are listed. This
67
+
subnode must be always present. If there are no I2C slave
68
+
devices, an empty node should be added. See ../../i2c/i2c.yaml
69
+
for more information.
70
+
type: object
71
+
72
+
aux-bus:
73
+
$ref: /schemas/display/dp-aux-bus.yaml#
74
+
75
+
vdd-supply:
76
+
description: phandle of a supply that powers the DisplayPort
77
+
link
78
+
79
+
patternProperties:
80
+
"^pinmux-[a-z0-9]+$":
81
+
description:
82
+
Since only three configurations are possible, only three child
83
+
nodes are needed to describe the pin mux'ing options for the
84
+
DPAUX pads. Furthermore, given that the pad functions are only
85
+
applicable to a single set of pads, the child nodes only need
86
+
to describe the pad group the functions are being applied to
87
+
rather than the individual pads.
88
+
type: object
89
+
properties:
90
+
groups:
91
+
const: dpaux-io
92
+
93
+
function:
94
+
enum:
95
+
- aux
96
+
- i2c
97
+
- off
98
+
99
+
additionalProperties: false
100
+
101
+
required:
102
+
- groups
103
+
- function
104
+
105
+
additionalProperties: false
106
+
107
+
required:
108
+
- compatible
109
+
- reg
110
+
- interrupts
111
+
- clocks
112
+
- clock-names
113
+
- resets
114
+
- reset-names
115
+
116
+
examples:
117
+
- |
118
+
#include <dt-bindings/clock/tegra210-car.h>
119
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
120
+
121
+
dpaux: dpaux@545c0000 {
122
+
compatible = "nvidia,tegra210-dpaux";
123
+
reg = <0x545c0000 0x00040000>;
124
+
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
125
+
clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
126
+
<&tegra_car TEGRA210_CLK_PLL_DP>;
127
+
clock-names = "dpaux", "parent";
128
+
resets = <&tegra_car 181>;
129
+
reset-names = "dpaux";
130
+
power-domains = <&pd_sor>;
131
+
status = "disabled";
132
+
133
+
state_dpaux_aux: pinmux-aux {
134
+
groups = "dpaux-io";
135
+
function = "aux";
136
+
};
137
+
138
+
state_dpaux_i2c: pinmux-i2c {
139
+
groups = "dpaux-io";
140
+
function = "i2c";
141
+
};
142
+
143
+
state_dpaux_off: pinmux-off {
144
+
groups = "dpaux-io";
145
+
function = "off";
146
+
};
147
+
148
+
i2c-bus {
149
+
#address-cells = <1>;
150
+
#size-cells = <0>;
151
+
};
152
+
};
+197
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
+197
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra SOR Output Encoder
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: |
14
+
The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
15
+
and DP outputs.
16
+
17
+
properties:
18
+
$nodename:
19
+
pattern: "^sor@[0-9a-f]+$"
20
+
21
+
compatible:
22
+
oneOf:
23
+
- enum:
24
+
- nvidia,tegra124-sor
25
+
- nvidia,tegra210-sor
26
+
- nvidia,tegra210-sor1
27
+
- nvidia,tegra186-sor
28
+
- nvidia,tegra186-sor1
29
+
- nvidia,tegra194-sor
30
+
31
+
- items:
32
+
- const: nvidia,tegra132-sor
33
+
- const: nvidia,tegra124-sor
34
+
35
+
reg:
36
+
maxItems: 1
37
+
38
+
interrupts:
39
+
maxItems: 1
40
+
41
+
clocks:
42
+
minItems: 5
43
+
maxItems: 6
44
+
45
+
clock-names:
46
+
minItems: 5
47
+
maxItems: 6
48
+
49
+
resets:
50
+
items:
51
+
- description: module reset
52
+
53
+
reset-names:
54
+
items:
55
+
- const: sor
56
+
57
+
power-domains:
58
+
maxItems: 1
59
+
60
+
avdd-io-hdmi-dp-supply:
61
+
description: I/O supply for HDMI/DP
62
+
63
+
vdd-hdmi-dp-pll-supply:
64
+
description: PLL supply for HDMI/DP
65
+
66
+
hdmi-supply:
67
+
description: +5.0V HDMI connector supply, required for HDMI
68
+
69
+
# Tegra186 and later
70
+
nvidia,interface:
71
+
description: index of the SOR interface
72
+
$ref: "/schemas/types.yaml#/definitions/uint32"
73
+
74
+
nvidia,ddc-i2c-bus:
75
+
description: phandle of an I2C controller used for DDC EDID
76
+
probing
77
+
$ref: "/schemas/types.yaml#/definitions/phandle"
78
+
79
+
nvidia,hpd-gpio:
80
+
description: specifies a GPIO used for hotplug detection
81
+
maxItems: 1
82
+
83
+
nvidia,edid:
84
+
description: supplies a binary EDID blob
85
+
$ref: "/schemas/types.yaml#/definitions/uint8-array"
86
+
87
+
nvidia,panel:
88
+
description: phandle of a display panel, required for eDP
89
+
$ref: "/schemas/types.yaml#/definitions/phandle"
90
+
91
+
nvidia,xbar-cfg:
92
+
description: 5 cells containing the crossbar configuration.
93
+
Each lane of the SOR, identified by the cell's index, is
94
+
mapped via the crossbar to the pad specified by the cell's
95
+
value.
96
+
$ref: "/schemas/types.yaml#/definitions/uint32-array"
97
+
98
+
# optional when driving an eDP output
99
+
nvidia,dpaux:
100
+
description: phandle to a DispayPort AUX interface
101
+
$ref: "/schemas/types.yaml#/definitions/phandle"
102
+
103
+
allOf:
104
+
- if:
105
+
properties:
106
+
compatible:
107
+
contains:
108
+
enum:
109
+
- nvidia,tegra186-sor
110
+
- nvidia,tegra194-sor
111
+
then:
112
+
properties:
113
+
clocks:
114
+
items:
115
+
- description: clock input for the SOR hardware
116
+
- description: SOR output clock
117
+
- description: input for the pixel clock
118
+
- description: reference clock for the SOR clock
119
+
- description: safe reference clock for the SOR clock
120
+
during power up
121
+
- description: SOR pad output clock
122
+
123
+
clock-names:
124
+
items:
125
+
- const: sor
126
+
- enum:
127
+
- source # deprecated
128
+
- out
129
+
- const: parent
130
+
- const: dp
131
+
- const: safe
132
+
- const: pad
133
+
else:
134
+
properties:
135
+
clocks:
136
+
items:
137
+
- description: clock input for the SOR hardware
138
+
- description: SOR output clock
139
+
- description: input for the pixel clock
140
+
- description: reference clock for the SOR clock
141
+
- description: safe reference clock for the SOR clock
142
+
during power up
143
+
144
+
clock-names:
145
+
items:
146
+
- const: sor
147
+
- enum:
148
+
- source # deprecated
149
+
- out
150
+
- const: parent
151
+
- const: dp
152
+
- const: safe
153
+
154
+
additionalProperties: false
155
+
156
+
required:
157
+
- compatible
158
+
- reg
159
+
- interrupts
160
+
- clocks
161
+
- clock-names
162
+
- resets
163
+
- reset-names
164
+
- avdd-io-hdmi-dp-supply
165
+
- vdd-hdmi-dp-pll-supply
166
+
167
+
examples:
168
+
- |
169
+
#include <dt-bindings/clock/tegra210-car.h>
170
+
#include <dt-bindings/gpio/tegra-gpio.h>
171
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
172
+
173
+
sor0: sor@54540000 {
174
+
compatible = "nvidia,tegra210-sor";
175
+
reg = <0x54540000 0x00040000>;
176
+
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
177
+
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
178
+
<&tegra_car TEGRA210_CLK_SOR0_OUT>,
179
+
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
180
+
<&tegra_car TEGRA210_CLK_PLL_DP>,
181
+
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
182
+
clock-names = "sor", "out", "parent", "dp", "safe";
183
+
resets = <&tegra_car 182>;
184
+
reset-names = "sor";
185
+
pinctrl-0 = <&state_dpaux_aux>;
186
+
pinctrl-1 = <&state_dpaux_i2c>;
187
+
pinctrl-2 = <&state_dpaux_off>;
188
+
pinctrl-names = "aux", "i2c", "off";
189
+
power-domains = <&pd_sor>;
190
+
191
+
avdd-io-hdmi-dp-supply = <&avdd_1v05>;
192
+
vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
193
+
hdmi-supply = <&vdd_hdmi>;
194
+
195
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
196
+
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>;
197
+
};
+71
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
+71
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Video Image Composer
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^vic@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
oneOf:
19
+
- enum:
20
+
- nvidia,tegra124-vic
21
+
- nvidia,tegra210-vic
22
+
- nvidia,tegra186-vic
23
+
- nvidia,tegra194-vic
24
+
25
+
- items:
26
+
- const: nvidia,tegra132-vic
27
+
- const: nvidia,tegra124-vic
28
+
29
+
reg:
30
+
maxItems: 1
31
+
32
+
interrupts:
33
+
maxItems: 1
34
+
35
+
clocks:
36
+
items:
37
+
- description: clock input for the VIC hardware
38
+
39
+
clock-names:
40
+
items:
41
+
- const: vic
42
+
43
+
resets:
44
+
items:
45
+
- description: module reset
46
+
47
+
reset-names:
48
+
items:
49
+
- const: vic
50
+
51
+
power-domains:
52
+
maxItems: 1
53
+
54
+
iommus:
55
+
maxItems: 1
56
+
57
+
interconnects:
58
+
description: Description of the interconnect paths for the VIC;
59
+
see ../interconnect/interconnect.txt for details.
60
+
items:
61
+
- description: memory read client for VIC
62
+
- description: memory write client for VIC
63
+
64
+
interconnect-names:
65
+
items:
66
+
- const: dma-mem # read
67
+
- const: write
68
+
69
+
dma-coherent: true
70
+
71
+
additionalProperties: false
+85
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
+85
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra186 (and later) Display Controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^display@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra186-dc
20
+
- nvidia,tegra194-dc
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
clocks:
29
+
items:
30
+
- description: display controller pixel clock
31
+
32
+
clock-names:
33
+
items:
34
+
- const: dc
35
+
36
+
resets:
37
+
items:
38
+
- description: display controller reset
39
+
40
+
reset-names:
41
+
items:
42
+
- const: dc
43
+
44
+
power-domains:
45
+
maxItems: 1
46
+
47
+
iommus:
48
+
maxItems: 1
49
+
50
+
interconnects:
51
+
description: Description of the interconnect paths for the
52
+
display controller; see ../interconnect/interconnect.txt
53
+
for details.
54
+
55
+
interconnect-names:
56
+
items:
57
+
- const: dma-mem # read-0
58
+
- const: read-1
59
+
60
+
nvidia,outputs:
61
+
description: A list of phandles of outputs that this display
62
+
controller can drive.
63
+
$ref: "/schemas/types.yaml#/definitions/phandle-array"
64
+
65
+
nvidia,head:
66
+
description: The number of the display controller head. This
67
+
is used to setup the various types of output to receive
68
+
video data from the given head.
69
+
$ref: "/schemas/types.yaml#/definitions/uint32"
70
+
71
+
additionalProperties: false
72
+
73
+
required:
74
+
- compatible
75
+
- reg
76
+
- interrupts
77
+
- clocks
78
+
- clock-names
79
+
- resets
80
+
- reset-names
81
+
- power-domains
82
+
- nvidia,outputs
83
+
- nvidia,head
84
+
85
+
# see nvidia,tegra186-display.yaml for examples
+310
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
+310
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra186 (and later) Display Hub
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^display-hub@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra186-display
20
+
- nvidia,tegra194-display
21
+
22
+
'#address-cells':
23
+
const: 1
24
+
25
+
'#size-cells':
26
+
const: 1
27
+
28
+
reg:
29
+
maxItems: 1
30
+
31
+
interrupts:
32
+
maxItems: 1
33
+
34
+
clocks:
35
+
minItems: 2
36
+
maxItems: 3
37
+
38
+
clock-names:
39
+
minItems: 2
40
+
maxItems: 3
41
+
42
+
resets:
43
+
items:
44
+
- description: display hub reset
45
+
- description: window group 0 reset
46
+
- description: window group 1 reset
47
+
- description: window group 2 reset
48
+
- description: window group 3 reset
49
+
- description: window group 4 reset
50
+
- description: window group 5 reset
51
+
52
+
reset-names:
53
+
items:
54
+
- const: misc
55
+
- const: wgrp0
56
+
- const: wgrp1
57
+
- const: wgrp2
58
+
- const: wgrp3
59
+
- const: wgrp4
60
+
- const: wgrp5
61
+
62
+
power-domains:
63
+
maxItems: 1
64
+
65
+
ranges:
66
+
maxItems: 1
67
+
68
+
patternProperties:
69
+
"^display@[0-9a-f]+$":
70
+
type: object
71
+
72
+
allOf:
73
+
- if:
74
+
properties:
75
+
compatible:
76
+
contains:
77
+
const: nvidia,tegra186-display
78
+
then:
79
+
properties:
80
+
clocks:
81
+
items:
82
+
- description: display core clock
83
+
- description: display stream compression clock
84
+
- description: display hub clock
85
+
86
+
clock-names:
87
+
items:
88
+
- const: disp
89
+
- const: dsc
90
+
- const: hub
91
+
else:
92
+
properties:
93
+
clocks:
94
+
items:
95
+
- description: display core clock
96
+
- description: display hub clock
97
+
98
+
clock-names:
99
+
items:
100
+
- const: disp
101
+
- const: hub
102
+
103
+
additionalProperties: false
104
+
105
+
required:
106
+
- compatible
107
+
- reg
108
+
- clocks
109
+
- clock-names
110
+
- resets
111
+
- reset-names
112
+
- power-domains
113
+
- "#address-cells"
114
+
- "#size-cells"
115
+
- ranges
116
+
117
+
examples:
118
+
- |
119
+
#include <dt-bindings/clock/tegra186-clock.h>
120
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
121
+
#include <dt-bindings/memory/tegra186-mc.h>
122
+
#include <dt-bindings/power/tegra186-powergate.h>
123
+
#include <dt-bindings/reset/tegra186-reset.h>
124
+
125
+
display-hub@15200000 {
126
+
compatible = "nvidia,tegra186-display";
127
+
reg = <0x15200000 0x00040000>;
128
+
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
129
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
130
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
131
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
132
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
133
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
134
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
135
+
reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
136
+
"wgrp3", "wgrp4", "wgrp5";
137
+
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
138
+
<&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
139
+
<&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
140
+
clock-names = "disp", "dsc", "hub";
141
+
status = "disabled";
142
+
143
+
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
144
+
145
+
#address-cells = <1>;
146
+
#size-cells = <1>;
147
+
148
+
ranges = <0x15200000 0x15200000 0x40000>;
149
+
150
+
display@15200000 {
151
+
compatible = "nvidia,tegra186-dc";
152
+
reg = <0x15200000 0x10000>;
153
+
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
154
+
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
155
+
clock-names = "dc";
156
+
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
157
+
reset-names = "dc";
158
+
159
+
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
160
+
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
161
+
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
162
+
interconnect-names = "dma-mem", "read-1";
163
+
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
164
+
165
+
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
166
+
nvidia,head = <0>;
167
+
};
168
+
169
+
display@15210000 {
170
+
compatible = "nvidia,tegra186-dc";
171
+
reg = <0x15210000 0x10000>;
172
+
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
173
+
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
174
+
clock-names = "dc";
175
+
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
176
+
reset-names = "dc";
177
+
178
+
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
179
+
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
180
+
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
181
+
interconnect-names = "dma-mem", "read-1";
182
+
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
183
+
184
+
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
185
+
nvidia,head = <1>;
186
+
};
187
+
188
+
display@15220000 {
189
+
compatible = "nvidia,tegra186-dc";
190
+
reg = <0x15220000 0x10000>;
191
+
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
192
+
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
193
+
clock-names = "dc";
194
+
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
195
+
reset-names = "dc";
196
+
197
+
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
198
+
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
199
+
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
200
+
interconnect-names = "dma-mem", "read-1";
201
+
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
202
+
203
+
nvidia,outputs = <&sor0 &sor1>;
204
+
nvidia,head = <2>;
205
+
};
206
+
};
207
+
208
+
- |
209
+
#include <dt-bindings/clock/tegra194-clock.h>
210
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
211
+
#include <dt-bindings/memory/tegra194-mc.h>
212
+
#include <dt-bindings/power/tegra194-powergate.h>
213
+
#include <dt-bindings/reset/tegra194-reset.h>
214
+
215
+
display-hub@15200000 {
216
+
compatible = "nvidia,tegra194-display";
217
+
reg = <0x15200000 0x00040000>;
218
+
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
219
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
220
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
221
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
222
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
223
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
224
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
225
+
reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
226
+
"wgrp3", "wgrp4", "wgrp5";
227
+
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
228
+
<&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
229
+
clock-names = "disp", "hub";
230
+
status = "disabled";
231
+
232
+
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
233
+
234
+
#address-cells = <1>;
235
+
#size-cells = <1>;
236
+
237
+
ranges = <0x15200000 0x15200000 0x40000>;
238
+
239
+
display@15200000 {
240
+
compatible = "nvidia,tegra194-dc";
241
+
reg = <0x15200000 0x10000>;
242
+
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
243
+
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
244
+
clock-names = "dc";
245
+
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
246
+
reset-names = "dc";
247
+
248
+
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
249
+
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
250
+
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
251
+
interconnect-names = "dma-mem", "read-1";
252
+
253
+
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
254
+
nvidia,head = <0>;
255
+
};
256
+
257
+
display@15210000 {
258
+
compatible = "nvidia,tegra194-dc";
259
+
reg = <0x15210000 0x10000>;
260
+
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
261
+
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
262
+
clock-names = "dc";
263
+
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
264
+
reset-names = "dc";
265
+
266
+
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
267
+
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
268
+
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
269
+
interconnect-names = "dma-mem", "read-1";
270
+
271
+
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
272
+
nvidia,head = <1>;
273
+
};
274
+
275
+
display@15220000 {
276
+
compatible = "nvidia,tegra194-dc";
277
+
reg = <0x15220000 0x10000>;
278
+
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
279
+
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
280
+
clock-names = "dc";
281
+
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
282
+
reset-names = "dc";
283
+
284
+
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
285
+
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
286
+
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
287
+
interconnect-names = "dma-mem", "read-1";
288
+
289
+
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
290
+
nvidia,head = <2>;
291
+
};
292
+
293
+
display@15230000 {
294
+
compatible = "nvidia,tegra194-dc";
295
+
reg = <0x15230000 0x10000>;
296
+
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
297
+
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
298
+
clock-names = "dc";
299
+
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
300
+
reset-names = "dc";
301
+
302
+
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
303
+
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
304
+
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
305
+
interconnect-names = "dma-mem", "read-1";
306
+
307
+
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
308
+
nvidia,head = <3>;
309
+
};
310
+
};
+45
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
+45
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dsi-padctl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra MIPI DSI pad controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^padctl@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
const: nvidia,tegra186-dsi-padctl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
resets:
24
+
items:
25
+
- description: module reset
26
+
27
+
reset-names:
28
+
items:
29
+
- const: dsi
30
+
31
+
allOf:
32
+
- $ref: "/schemas/reset/reset.yaml"
33
+
34
+
additionalProperties: false
35
+
36
+
examples:
37
+
- |
38
+
#include <dt-bindings/reset/tegra186-reset.h>
39
+
40
+
padctl@15880000 {
41
+
compatible = "nvidia,tegra186-dsi-padctl";
42
+
reg = <0x15880000 0x10000>;
43
+
resets = <&bpmp TEGRA186_RESET_DSI>;
44
+
reset-names = "dsi";
45
+
};
+183
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
+183
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Display Controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^dc@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
oneOf:
19
+
- enum:
20
+
- nvidia,tegra20-dc
21
+
- nvidia,tegra30-dc
22
+
- nvidia,tegra114-dc
23
+
- nvidia,tegra124-dc
24
+
- nvidia,tegra210-dc
25
+
26
+
- items:
27
+
- const: nvidia,tegra124-dc
28
+
- const: nvidia,tegra132-dc
29
+
30
+
reg:
31
+
maxItems: 1
32
+
33
+
interrupts:
34
+
maxItems: 1
35
+
36
+
clocks:
37
+
minItems: 1
38
+
items:
39
+
- description: display controller pixel clock
40
+
- description: parent clock # optional
41
+
42
+
clock-names:
43
+
minItems: 1
44
+
items:
45
+
- const: dc
46
+
- const: parent # optional
47
+
48
+
resets:
49
+
items:
50
+
- description: module reset
51
+
52
+
reset-names:
53
+
items:
54
+
- const: dc
55
+
56
+
interconnect-names: true
57
+
interconnects: true
58
+
59
+
iommus:
60
+
maxItems: 1
61
+
62
+
operating-points-v2:
63
+
$ref: "/schemas/types.yaml#/definitions/phandle"
64
+
65
+
power-domains:
66
+
items:
67
+
- description: phandle to the core power domain
68
+
69
+
memory-region: true
70
+
71
+
nvidia,head:
72
+
$ref: /schemas/types.yaml#/definitions/uint32
73
+
description: The number of the display controller head. This is used to setup the various
74
+
types of output to receive video data from the given head.
75
+
76
+
nvidia,outputs:
77
+
$ref: /schemas/types.yaml#/definitions/phandle-array
78
+
description: A list of phandles of outputs that this display controller can drive.
79
+
80
+
rgb:
81
+
type: object
82
+
83
+
allOf:
84
+
- if:
85
+
properties:
86
+
compatible:
87
+
contains:
88
+
enum:
89
+
- nvidia,tegra20-dc
90
+
- nvidia,tegra30-dc
91
+
- nvidia,tegra114-dc
92
+
then:
93
+
properties:
94
+
interconnects:
95
+
items:
96
+
- description: window A memory client
97
+
- description: window B memory client
98
+
- description: window B memory client (vertical filter)
99
+
- description: window C memory client
100
+
- description: cursor memory client
101
+
102
+
interconnect-names:
103
+
items:
104
+
- const: wina
105
+
- const: winb
106
+
- const: winb-vfilter
107
+
- const: winc
108
+
- const: cursor
109
+
110
+
rgb:
111
+
description: Each display controller node has a child node, named "rgb", that represents
112
+
the RGB output associated with the controller.
113
+
type: object
114
+
properties:
115
+
nvidia,ddc-i2c-bus:
116
+
$ref: /schemas/types.yaml#/definitions/phandle
117
+
description: phandle of an I2C controller used for DDC EDID probing
118
+
119
+
nvidia,hpd-gpio:
120
+
description: specifies a GPIO used for hotplug detection
121
+
maxItems: 1
122
+
123
+
nvidia,edid:
124
+
$ref: /schemas/types.yaml#/definitions/uint8-array
125
+
description: supplies a binary EDID blob
126
+
127
+
nvidia,panel:
128
+
$ref: /schemas/types.yaml#/definitions/phandle
129
+
description: phandle of a display panel
130
+
131
+
- if:
132
+
properties:
133
+
compatible:
134
+
contains:
135
+
enum:
136
+
- nvidia,tegra124-dc
137
+
then:
138
+
properties:
139
+
interconnects:
140
+
minItems: 4
141
+
items:
142
+
- description: window A memory client
143
+
- description: window B memory client
144
+
- description: window C memory client
145
+
- description: cursor memory client
146
+
- description: window D memory client
147
+
- description: window T memory client
148
+
149
+
interconnect-names:
150
+
minItems: 4
151
+
items:
152
+
- const: wina
153
+
- const: winb
154
+
- const: winc
155
+
- const: cursor
156
+
- const: wind
157
+
- const: wint
158
+
159
+
additionalProperties: false
160
+
161
+
required:
162
+
- compatible
163
+
- reg
164
+
- interrupts
165
+
- clocks
166
+
- clock-names
167
+
- resets
168
+
- reset-names
169
+
170
+
examples:
171
+
- |
172
+
#include <dt-bindings/clock/tegra20-car.h>
173
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
174
+
175
+
dc@54200000 {
176
+
compatible = "nvidia,tegra20-dc";
177
+
reg = <0x54200000 0x00040000>;
178
+
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
179
+
clocks = <&tegra_car TEGRA20_CLK_DISP1>;
180
+
clock-names = "dc";
181
+
resets = <&tegra_car 27>;
182
+
reset-names = "dc";
183
+
};
+159
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
+159
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Display Serial Interface
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
compatible:
15
+
oneOf:
16
+
- enum:
17
+
- nvidia,tegra20-dsi
18
+
- nvidia,tegra30-dsi
19
+
- nvidia,tegra114-dsi
20
+
- nvidia,tegra124-dsi
21
+
- nvidia,tegra210-dsi
22
+
- nvidia,tegra186-dsi
23
+
24
+
- items:
25
+
- const: nvidia,tegra132-dsi
26
+
- const: nvidia,tegra124-dsi
27
+
28
+
reg:
29
+
maxItems: 1
30
+
31
+
interrupts:
32
+
maxItems: 1
33
+
34
+
clocks:
35
+
minItems: 2
36
+
maxItems: 3
37
+
38
+
clock-names:
39
+
minItems: 2
40
+
maxItems: 3
41
+
42
+
resets:
43
+
items:
44
+
- description: module reset
45
+
46
+
reset-names:
47
+
items:
48
+
- const: dsi
49
+
50
+
operating-points-v2:
51
+
$ref: "/schemas/types.yaml#/definitions/phandle"
52
+
53
+
power-domains:
54
+
maxItems: 1
55
+
56
+
avdd-dsi-csi-supply:
57
+
description: phandle of a supply that powers the DSI controller
58
+
59
+
nvidia,mipi-calibrate:
60
+
description: Should contain a phandle and a specifier specifying
61
+
which pads are used by this DSI output and need to be
62
+
calibrated. See nvidia,tegra114-mipi.yaml for details.
63
+
$ref: "/schemas/types.yaml#/definitions/phandle-array"
64
+
65
+
nvidia,ddc-i2c-bus:
66
+
description: phandle of an I2C controller used for DDC EDID
67
+
probing
68
+
$ref: "/schemas/types.yaml#/definitions/phandle"
69
+
70
+
nvidia,hpd-gpio:
71
+
description: specifies a GPIO used for hotplug detection
72
+
maxItems: 1
73
+
74
+
nvidia,edid:
75
+
description: supplies a binary EDID blob
76
+
$ref: "/schemas/types.yaml#/definitions/uint8-array"
77
+
78
+
nvidia,panel:
79
+
description: phandle of a display panel
80
+
$ref: "/schemas/types.yaml#/definitions/phandle"
81
+
82
+
nvidia,ganged-mode:
83
+
description: contains a phandle to a second DSI controller to
84
+
gang up with in order to support up to 8 data lanes
85
+
$ref: "/schemas/types.yaml#/definitions/phandle"
86
+
87
+
allOf:
88
+
- $ref: "../dsi-controller.yaml#"
89
+
- if:
90
+
properties:
91
+
compatible:
92
+
contains:
93
+
enum:
94
+
- nvidia,tegra20-dsi
95
+
- nvidia,tegra30-dsi
96
+
then:
97
+
properties:
98
+
clocks:
99
+
items:
100
+
- description: DSI module clock
101
+
- description: input for the pixel clock
102
+
103
+
clock-names:
104
+
items:
105
+
- const: dsi
106
+
- const: parent
107
+
else:
108
+
properties:
109
+
clocks:
110
+
items:
111
+
- description: DSI module clock
112
+
- description: low-power module clock
113
+
- description: input for the pixel clock
114
+
115
+
clock-names:
116
+
items:
117
+
- const: dsi
118
+
- const: lp
119
+
- const: parent
120
+
121
+
- if:
122
+
properties:
123
+
compatible:
124
+
contains:
125
+
const: nvidia,tegra186-dsi
126
+
then:
127
+
required:
128
+
- interrupts
129
+
130
+
unevaluatedProperties: false
131
+
132
+
required:
133
+
- compatible
134
+
- reg
135
+
- clocks
136
+
- clock-names
137
+
- resets
138
+
- reset-names
139
+
140
+
examples:
141
+
- |
142
+
#include <dt-bindings/clock/tegra186-clock.h>
143
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
144
+
#include <dt-bindings/power/tegra186-powergate.h>
145
+
#include <dt-bindings/reset/tegra186-reset.h>
146
+
147
+
dsi@15300000 {
148
+
compatible = "nvidia,tegra186-dsi";
149
+
reg = <0x15300000 0x10000>;
150
+
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
151
+
clocks = <&bpmp TEGRA186_CLK_DSI>,
152
+
<&bpmp TEGRA186_CLK_DSIA_LP>,
153
+
<&bpmp TEGRA186_CLK_PLLD>;
154
+
clock-names = "dsi", "lp", "parent";
155
+
resets = <&bpmp TEGRA186_RESET_DSI>;
156
+
reset-names = "dsi";
157
+
158
+
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
159
+
};
+70
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
+70
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Encoder Pre-Processor
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^epp@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra20-epp
20
+
- nvidia,tegra30-epp
21
+
- nvidia,tegra114-epp
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
maxItems: 1
31
+
32
+
resets:
33
+
items:
34
+
- description: module reset
35
+
36
+
reset-names:
37
+
items:
38
+
- const: epp
39
+
40
+
iommus:
41
+
maxItems: 1
42
+
43
+
interconnects:
44
+
maxItems: 4
45
+
46
+
interconnect-names:
47
+
maxItems: 4
48
+
49
+
operating-points-v2:
50
+
$ref: "/schemas/types.yaml#/definitions/phandle"
51
+
52
+
power-domains:
53
+
items:
54
+
- description: phandle to the core power domain
55
+
56
+
additionalProperties: false
57
+
58
+
examples:
59
+
- |
60
+
#include <dt-bindings/clock/tegra20-car.h>
61
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
62
+
63
+
epp@540c0000 {
64
+
compatible = "nvidia,tegra20-epp";
65
+
reg = <0x540c0000 0x00040000>;
66
+
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
67
+
clocks = <&tegra_car TEGRA20_CLK_EPP>;
68
+
resets = <&tegra_car 19>;
69
+
reset-names = "epp";
70
+
};
+74
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
+74
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA 2D graphics engine
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^gr2d@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra20-gr2d
20
+
- nvidia,tegra30-gr2d
21
+
- nvidia,tegra114-gr2d
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
items:
31
+
- description: module clock
32
+
33
+
resets:
34
+
items:
35
+
- description: module reset
36
+
- description: memory client hotflush reset
37
+
38
+
reset-names:
39
+
items:
40
+
- const: 2d
41
+
- const: mc
42
+
43
+
iommus:
44
+
maxItems: 1
45
+
46
+
interconnects:
47
+
maxItems: 4
48
+
49
+
interconnect-names:
50
+
maxItems: 4
51
+
52
+
operating-points-v2:
53
+
$ref: "/schemas/types.yaml#/definitions/phandle"
54
+
55
+
power-domains:
56
+
items:
57
+
- description: phandle to the HEG or core power domain
58
+
59
+
additionalProperties: false
60
+
61
+
examples:
62
+
- |
63
+
#include <dt-bindings/clock/tegra20-car.h>
64
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
65
+
#include <dt-bindings/memory/tegra20-mc.h>
66
+
67
+
gr2d@54140000 {
68
+
compatible = "nvidia,tegra20-gr2d";
69
+
reg = <0x54140000 0x00040000>;
70
+
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
71
+
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
72
+
resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
73
+
reset-names = "2d", "mc";
74
+
};
+215
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
+215
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA 3D graphics engine
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^gr3d@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra20-gr3d
20
+
- nvidia,tegra30-gr3d
21
+
- nvidia,tegra114-gr3d
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
minItems: 1
28
+
maxItems: 2
29
+
30
+
clock-names:
31
+
minItems: 1
32
+
maxItems: 2
33
+
34
+
resets:
35
+
minItems: 2
36
+
maxItems: 4
37
+
38
+
reset-names:
39
+
minItems: 2
40
+
maxItems: 4
41
+
42
+
iommus:
43
+
minItems: 1
44
+
maxItems: 2
45
+
46
+
interconnects:
47
+
minItems: 4
48
+
maxItems: 10
49
+
50
+
interconnect-names:
51
+
minItems: 4
52
+
maxItems: 10
53
+
54
+
operating-points-v2:
55
+
$ref: "/schemas/types.yaml#/definitions/phandle"
56
+
57
+
power-domains:
58
+
minItems: 1
59
+
maxItems: 2
60
+
61
+
power-domain-names:
62
+
minItems: 2
63
+
maxItems: 2
64
+
65
+
allOf:
66
+
- if:
67
+
properties:
68
+
compatible:
69
+
contains:
70
+
const: nvidia,tegra20-gr2d
71
+
then:
72
+
properties:
73
+
clocks:
74
+
items:
75
+
- description: module clock
76
+
77
+
clock-names:
78
+
items:
79
+
- const: 3d
80
+
81
+
resets:
82
+
items:
83
+
- description: module reset
84
+
- description: memory client hotflush reset
85
+
86
+
reset-names:
87
+
items:
88
+
- const: 3d
89
+
- const: mc
90
+
91
+
iommus:
92
+
maxItems: 1
93
+
94
+
interconnects:
95
+
minItems: 4
96
+
maxItems: 4
97
+
98
+
interconnect-names:
99
+
minItems: 4
100
+
maxItems: 4
101
+
102
+
power-domains:
103
+
items:
104
+
- description: phandle to the TD power domain
105
+
106
+
- if:
107
+
properties:
108
+
compatible:
109
+
contains:
110
+
const: nvidia,tegra30-gr3d
111
+
then:
112
+
properties:
113
+
clocks:
114
+
items:
115
+
- description: primary module clock
116
+
- description: secondary module clock
117
+
118
+
clock-names:
119
+
items:
120
+
- const: 3d
121
+
- const: 3d2
122
+
123
+
resets:
124
+
items:
125
+
- description: primary module reset
126
+
- description: secondary module reset
127
+
- description: primary memory client hotflush reset
128
+
- description: secondary memory client hotflush reset
129
+
130
+
reset-names:
131
+
items:
132
+
- const: 3d
133
+
- const: 3d2
134
+
- const: mc
135
+
- const: mc2
136
+
137
+
iommus:
138
+
minItems: 2
139
+
maxItems: 2
140
+
141
+
interconnects:
142
+
minItems: 8
143
+
maxItems: 8
144
+
145
+
interconnect-names:
146
+
minItems: 8
147
+
maxItems: 8
148
+
149
+
power-domains:
150
+
items:
151
+
- description: phandle to the TD power domain
152
+
- description: phandle to the TD2 power domain
153
+
154
+
power-domain-names:
155
+
items:
156
+
- const: 3d0
157
+
- const: 3d1
158
+
159
+
dependencies:
160
+
power-domains: [ power-domain-names ]
161
+
162
+
- if:
163
+
properties:
164
+
compatible:
165
+
contains:
166
+
const: nvidia,tegra114-gr2d
167
+
then:
168
+
properties:
169
+
clocks:
170
+
items:
171
+
- description: module clock
172
+
173
+
clock-names:
174
+
items:
175
+
- const: 3d
176
+
177
+
resets:
178
+
items:
179
+
- description: module reset
180
+
- description: memory client hotflush reset
181
+
182
+
reset-names:
183
+
items:
184
+
- const: 3d
185
+
- const: mc
186
+
187
+
iommus:
188
+
maxItems: 1
189
+
190
+
interconnects:
191
+
minItems: 10
192
+
maxItems: 10
193
+
194
+
interconnect-names:
195
+
minItems: 10
196
+
maxItems: 10
197
+
198
+
power-domains:
199
+
items:
200
+
- description: phandle to the TD power domain
201
+
202
+
additionalProperties: false
203
+
204
+
examples:
205
+
- |
206
+
#include <dt-bindings/clock/tegra20-car.h>
207
+
#include <dt-bindings/memory/tegra20-mc.h>
208
+
209
+
gr3d@54180000 {
210
+
compatible = "nvidia,tegra20-gr3d";
211
+
reg = <0x54180000 0x00040000>;
212
+
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
213
+
resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
214
+
reset-names = "3d", "mc";
215
+
};
+126
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
+126
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra HDMI Output Encoder
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^hdmi@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
oneOf:
19
+
- enum:
20
+
- nvidia,tegra20-hdmi
21
+
- nvidia,tegra30-hdmi
22
+
- nvidia,tegra114-hdmi
23
+
- nvidia,tegra124-hdmi
24
+
25
+
- items:
26
+
- const: nvidia,tegra132-hdmi
27
+
- const: nvidia,tegra124-hdmi
28
+
29
+
reg:
30
+
maxItems: 1
31
+
32
+
interrupts:
33
+
maxItems: 1
34
+
35
+
clocks:
36
+
items:
37
+
- description: module clock
38
+
- description: parent clock
39
+
40
+
clock-names:
41
+
items:
42
+
- const: hdmi
43
+
- const: parent
44
+
45
+
resets:
46
+
items:
47
+
- description: module reset
48
+
49
+
reset-names:
50
+
items:
51
+
- const: hdmi
52
+
53
+
operating-points-v2:
54
+
$ref: "/schemas/types.yaml#/definitions/phandle"
55
+
56
+
power-domains:
57
+
items:
58
+
- description: phandle to the core power domain
59
+
60
+
hdmi-supply:
61
+
description: supply for the +5V HDMI connector pin
62
+
63
+
vdd-supply:
64
+
description: regulator for supply voltage
65
+
66
+
pll-supply:
67
+
description: regulator for PLL
68
+
69
+
nvidia,ddc-i2c-bus:
70
+
description: phandle of an I2C controller used for DDC EDID
71
+
probing
72
+
$ref: "/schemas/types.yaml#/definitions/phandle"
73
+
74
+
nvidia,hpd-gpio:
75
+
description: specifies a GPIO used for hotplug detection
76
+
maxItems: 1
77
+
78
+
nvidia,edid:
79
+
description: supplies a binary EDID blob
80
+
$ref: "/schemas/types.yaml#/definitions/uint8-array"
81
+
82
+
nvidia,panel:
83
+
description: phandle of a display panel
84
+
$ref: "/schemas/types.yaml#/definitions/phandle"
85
+
86
+
"#sound-dai-cells":
87
+
const: 0
88
+
89
+
additionalProperties: false
90
+
91
+
required:
92
+
- compatible
93
+
- reg
94
+
- interrupts
95
+
- clocks
96
+
- clock-names
97
+
- resets
98
+
- reset-names
99
+
- pll-supply
100
+
- vdd-supply
101
+
- nvidia,ddc-i2c-bus
102
+
- nvidia,hpd-gpio
103
+
104
+
examples:
105
+
- |
106
+
#include <dt-bindings/clock/tegra124-car.h>
107
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
108
+
#include <dt-bindings/gpio/tegra-gpio.h>
109
+
110
+
hdmi@54280000 {
111
+
compatible = "nvidia,tegra124-hdmi";
112
+
reg = <0x54280000 0x00040000>;
113
+
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
114
+
clocks = <&tegra_car TEGRA124_CLK_HDMI>,
115
+
<&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
116
+
clock-names = "hdmi", "parent";
117
+
resets = <&tegra_car 51>;
118
+
reset-names = "hdmi";
119
+
120
+
hdmi-supply = <&vdd_5v0_hdmi>;
121
+
pll-supply = <&vdd_hdmi_pll>;
122
+
vdd-supply = <&vdd_3v3_hdmi>;
123
+
124
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
125
+
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
126
+
};
-675
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
-675
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
···
1
-
NVIDIA Tegra host1x
2
-
3
-
Required properties:
4
-
- compatible: "nvidia,tegra<chip>-host1x"
5
-
- reg: Physical base address and length of the controller's registers.
6
-
For pre-Tegra186, one entry describing the whole register area.
7
-
For Tegra186, one entry for each entry in reg-names:
8
-
"vm" - VM region assigned to Linux
9
-
"hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10
-
- interrupts: The interrupt outputs from the controller.
11
-
- #address-cells: The number of cells used to represent physical base addresses
12
-
in the host1x address space. Should be 1.
13
-
- #size-cells: The number of cells used to represent the size of an address
14
-
range in the host1x address space. Should be 1.
15
-
- ranges: The mapping of the host1x address space to the CPU address space.
16
-
- clocks: Must contain one entry, for the module clock.
17
-
See ../clocks/clock-bindings.txt for details.
18
-
- resets: Must contain an entry for each entry in reset-names.
19
-
See ../reset/reset.txt for details.
20
-
- reset-names: Must include the following entries:
21
-
- host1x
22
-
- mc
23
-
24
-
Optional properties:
25
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
26
-
- power-domains: Phandle to HEG or core power domain.
27
-
28
-
For each opp entry in 'operating-points-v2' table of host1x and its modules:
29
-
- opp-supported-hw: One bitfield indicating:
30
-
On Tegra20: SoC process ID mask
31
-
On Tegra30+: SoC speedo ID mask
32
-
33
-
A bitwise AND is performed against the value and if any bit
34
-
matches, the OPP gets enabled.
35
-
36
-
Each host1x client module having to perform DMA through the Memory Controller
37
-
should have the interconnect endpoints set to the Memory Client and External
38
-
Memory respectively.
39
-
40
-
The host1x top-level node defines a number of children, each representing one
41
-
of the following host1x client modules:
42
-
43
-
- mpe: video encoder
44
-
45
-
Required properties:
46
-
- compatible: "nvidia,tegra<chip>-mpe"
47
-
- reg: Physical base address and length of the controller's registers.
48
-
- interrupts: The interrupt outputs from the controller.
49
-
- clocks: Must contain one entry, for the module clock.
50
-
See ../clocks/clock-bindings.txt for details.
51
-
- resets: Must contain an entry for each entry in reset-names.
52
-
See ../reset/reset.txt for details.
53
-
- reset-names: Must include the following entries:
54
-
- mpe
55
-
56
-
Optional properties:
57
-
- interconnects: Must contain entry for the MPE memory clients.
58
-
- interconnect-names: Must include name of the interconnect path for each
59
-
interconnect entry. Consult TRM documentation for information about
60
-
available memory clients, see MEMORY CONTROLLER section.
61
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
62
-
- power-domains: Phandle to MPE power domain.
63
-
64
-
- vi: video input
65
-
66
-
Required properties:
67
-
- compatible: "nvidia,tegra<chip>-vi"
68
-
- reg: Physical base address and length of the controller registers.
69
-
- interrupts: The interrupt outputs from the controller.
70
-
- clocks: clocks: Must contain one entry, for the module clock.
71
-
See ../clocks/clock-bindings.txt for details.
72
-
- Tegra20/Tegra30/Tegra114/Tegra124:
73
-
- resets: Must contain an entry for each entry in reset-names.
74
-
See ../reset/reset.txt for details.
75
-
- reset-names: Must include the following entries:
76
-
- vi
77
-
- Tegra210:
78
-
- power-domains: Must include venc powergate node as vi is in VE partition.
79
-
80
-
ports (optional node)
81
-
vi can have optional ports node and max 6 ports are supported. Each port
82
-
should have single 'endpoint' child node. All port nodes are grouped under
83
-
ports node. Please refer to the bindings defined in
84
-
Documentation/devicetree/bindings/media/video-interfaces.txt
85
-
86
-
csi (required node)
87
-
Tegra210 has CSI part of VI sharing same host interface and register space.
88
-
So, VI device node should have CSI child node.
89
-
90
-
- csi: mipi csi interface to vi
91
-
92
-
Required properties:
93
-
- compatible: "nvidia,tegra210-csi"
94
-
- reg: Physical base address offset to parent and length of the controller
95
-
registers.
96
-
- clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
97
-
See ../clocks/clock-bindings.txt for details.
98
-
- power-domains: Must include sor powergate node as csicil is in
99
-
SOR partition.
100
-
101
-
channel (optional nodes)
102
-
Maximum 6 channels are supported with each csi brick as either x4 or x2
103
-
based on hw connectivity to sensor.
104
-
105
-
Required properties:
106
-
- reg: csi port number. Valid port numbers are 0 through 5.
107
-
- nvidia,mipi-calibrate: Should contain a phandle and a specifier
108
-
specifying which pads are used by this CSI port and need to be
109
-
calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
110
-
111
-
Each channel node must contain 2 port nodes which can be grouped
112
-
under 'ports' node and each port should have a single child 'endpoint'
113
-
node.
114
-
115
-
ports node
116
-
Please refer to the bindings defined in
117
-
Documentation/devicetree/bindings/media/video-interfaces.txt
118
-
119
-
ports node must contain below 2 port nodes.
120
-
port@0 with single child 'endpoint' node always a sink.
121
-
port@1 with single child 'endpoint' node always a source.
122
-
123
-
port@0 (required node)
124
-
Required properties:
125
-
- reg: 0
126
-
127
-
endpoint (required node)
128
-
Required properties:
129
-
- data-lanes: an array of data lane from 1 to 8. Valid array
130
-
lengths are 1/2/4/8.
131
-
- remote-endpoint: phandle to sensor 'endpoint' node.
132
-
133
-
port@1 (required node)
134
-
Required properties:
135
-
- reg: 1
136
-
137
-
endpoint (required node)
138
-
Required properties:
139
-
- remote-endpoint: phandle to vi port 'endpoint' node.
140
-
141
-
Optional properties:
142
-
- interconnects: Must contain entry for the VI memory clients.
143
-
- interconnect-names: Must include name of the interconnect path for each
144
-
interconnect entry. Consult TRM documentation for information about
145
-
available memory clients, see MEMORY CONTROLLER section.
146
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
147
-
- power-domains: Phandle to VENC power domain.
148
-
149
-
- epp: encoder pre-processor
150
-
151
-
Required properties:
152
-
- compatible: "nvidia,tegra<chip>-epp"
153
-
- reg: Physical base address and length of the controller's registers.
154
-
- interrupts: The interrupt outputs from the controller.
155
-
- clocks: Must contain one entry, for the module clock.
156
-
See ../clocks/clock-bindings.txt for details.
157
-
- resets: Must contain an entry for each entry in reset-names.
158
-
See ../reset/reset.txt for details.
159
-
- reset-names: Must include the following entries:
160
-
- epp
161
-
162
-
Optional properties:
163
-
- interconnects: Must contain entry for the EPP memory clients.
164
-
- interconnect-names: Must include name of the interconnect path for each
165
-
interconnect entry. Consult TRM documentation for information about
166
-
available memory clients, see MEMORY CONTROLLER section.
167
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
168
-
- power-domains: Phandle to HEG or core power domain.
169
-
170
-
- isp: image signal processor
171
-
172
-
Required properties:
173
-
- compatible: "nvidia,tegra<chip>-isp"
174
-
- reg: Physical base address and length of the controller's registers.
175
-
- interrupts: The interrupt outputs from the controller.
176
-
- clocks: Must contain one entry, for the module clock.
177
-
See ../clocks/clock-bindings.txt for details.
178
-
- resets: Must contain an entry for each entry in reset-names.
179
-
See ../reset/reset.txt for details.
180
-
- reset-names: Must include the following entries:
181
-
- isp
182
-
183
-
Optional properties:
184
-
- interconnects: Must contain entry for the ISP memory clients.
185
-
- interconnect-names: Must include name of the interconnect path for each
186
-
interconnect entry. Consult TRM documentation for information about
187
-
available memory clients, see MEMORY CONTROLLER section.
188
-
- power-domains: Phandle to VENC or core power domain.
189
-
190
-
- gr2d: 2D graphics engine
191
-
192
-
Required properties:
193
-
- compatible: "nvidia,tegra<chip>-gr2d"
194
-
- reg: Physical base address and length of the controller's registers.
195
-
- interrupts: The interrupt outputs from the controller.
196
-
- clocks: Must contain one entry, for the module clock.
197
-
See ../clocks/clock-bindings.txt for details.
198
-
- resets: Must contain an entry for each entry in reset-names.
199
-
See ../reset/reset.txt for details.
200
-
- reset-names: Must include the following entries:
201
-
- 2d
202
-
- mc
203
-
204
-
Optional properties:
205
-
- interconnects: Must contain entry for the GR2D memory clients.
206
-
- interconnect-names: Must include name of the interconnect path for each
207
-
interconnect entry. Consult TRM documentation for information about
208
-
available memory clients, see MEMORY CONTROLLER section.
209
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
210
-
- power-domains: Phandle to HEG or core power domain.
211
-
212
-
- gr3d: 3D graphics engine
213
-
214
-
Required properties:
215
-
- compatible: "nvidia,tegra<chip>-gr3d"
216
-
- reg: Physical base address and length of the controller's registers.
217
-
- clocks: Must contain an entry for each entry in clock-names.
218
-
See ../clocks/clock-bindings.txt for details.
219
-
- clock-names: Must include the following entries:
220
-
(This property may be omitted if the only clock in the list is "3d")
221
-
- 3d
222
-
This MUST be the first entry.
223
-
- 3d2 (Only required on SoCs with two 3D clocks)
224
-
- resets: Must contain an entry for each entry in reset-names.
225
-
See ../reset/reset.txt for details.
226
-
- reset-names: Must include the following entries:
227
-
- 3d
228
-
- 3d2 (Only required on SoCs with two 3D clocks)
229
-
- mc
230
-
- mc2 (Only required on SoCs with two 3D clocks)
231
-
232
-
Optional properties:
233
-
- interconnects: Must contain entry for the GR3D memory clients.
234
-
- interconnect-names: Must include name of the interconnect path for each
235
-
interconnect entry. Consult TRM documentation for information about
236
-
available memory clients, see MEMORY CONTROLLER section.
237
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
238
-
- power-domains: Phandles to 3D or core power domain.
239
-
240
-
- dc: display controller
241
-
242
-
Required properties:
243
-
- compatible: "nvidia,tegra<chip>-dc"
244
-
- reg: Physical base address and length of the controller's registers.
245
-
- interrupts: The interrupt outputs from the controller.
246
-
- clocks: Must contain an entry for each entry in clock-names.
247
-
See ../clocks/clock-bindings.txt for details.
248
-
- clock-names: Must include the following entries:
249
-
- dc
250
-
This MUST be the first entry.
251
-
- parent
252
-
- resets: Must contain an entry for each entry in reset-names.
253
-
See ../reset/reset.txt for details.
254
-
- reset-names: Must include the following entries:
255
-
- dc
256
-
- nvidia,head: The number of the display controller head. This is used to
257
-
setup the various types of output to receive video data from the given
258
-
head.
259
-
260
-
Each display controller node has a child node, named "rgb", that represents
261
-
the RGB output associated with the controller. It can take the following
262
-
optional properties:
263
-
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
264
-
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
265
-
- nvidia,edid: supplies a binary EDID blob
266
-
- nvidia,panel: phandle of a display panel
267
-
- interconnects: Must contain entry for the DC memory clients.
268
-
- interconnect-names: Must include name of the interconnect path for each
269
-
interconnect entry. Consult TRM documentation for information about
270
-
available memory clients, see MEMORY CONTROLLER section.
271
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
272
-
- power-domains: Phandle to core power domain.
273
-
274
-
- hdmi: High Definition Multimedia Interface
275
-
276
-
Required properties:
277
-
- compatible: "nvidia,tegra<chip>-hdmi"
278
-
- reg: Physical base address and length of the controller's registers.
279
-
- interrupts: The interrupt outputs from the controller.
280
-
- hdmi-supply: supply for the +5V HDMI connector pin
281
-
- vdd-supply: regulator for supply voltage
282
-
- pll-supply: regulator for PLL
283
-
- clocks: Must contain an entry for each entry in clock-names.
284
-
See ../clocks/clock-bindings.txt for details.
285
-
- clock-names: Must include the following entries:
286
-
- hdmi
287
-
This MUST be the first entry.
288
-
- parent
289
-
- resets: Must contain an entry for each entry in reset-names.
290
-
See ../reset/reset.txt for details.
291
-
- reset-names: Must include the following entries:
292
-
- hdmi
293
-
294
-
Optional properties:
295
-
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
296
-
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
297
-
- nvidia,edid: supplies a binary EDID blob
298
-
- nvidia,panel: phandle of a display panel
299
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
300
-
301
-
- tvo: TV encoder output
302
-
303
-
Required properties:
304
-
- compatible: "nvidia,tegra<chip>-tvo"
305
-
- reg: Physical base address and length of the controller's registers.
306
-
- interrupts: The interrupt outputs from the controller.
307
-
- clocks: Must contain one entry, for the module clock.
308
-
See ../clocks/clock-bindings.txt for details.
309
-
310
-
Optional properties:
311
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
312
-
- power-domains: Phandle to core power domain.
313
-
314
-
- dsi: display serial interface
315
-
316
-
Required properties:
317
-
- compatible: "nvidia,tegra<chip>-dsi"
318
-
- reg: Physical base address and length of the controller's registers.
319
-
- clocks: Must contain an entry for each entry in clock-names.
320
-
See ../clocks/clock-bindings.txt for details.
321
-
- clock-names: Must include the following entries:
322
-
- dsi
323
-
This MUST be the first entry.
324
-
- lp
325
-
- parent
326
-
- resets: Must contain an entry for each entry in reset-names.
327
-
See ../reset/reset.txt for details.
328
-
- reset-names: Must include the following entries:
329
-
- dsi
330
-
- avdd-dsi-supply: phandle of a supply that powers the DSI controller
331
-
- nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
332
-
which pads are used by this DSI output and need to be calibrated. See also
333
-
../display/tegra/nvidia,tegra114-mipi.txt.
334
-
335
-
Optional properties:
336
-
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
337
-
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
338
-
- nvidia,edid: supplies a binary EDID blob
339
-
- nvidia,panel: phandle of a display panel
340
-
- nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
341
-
up with in order to support up to 8 data lanes
342
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
343
-
344
-
- sor: serial output resource
345
-
346
-
Required properties:
347
-
- compatible: Should be:
348
-
- "nvidia,tegra124-sor": for Tegra124 and Tegra132
349
-
- "nvidia,tegra132-sor": for Tegra132
350
-
- "nvidia,tegra210-sor": for Tegra210
351
-
- "nvidia,tegra210-sor1": for Tegra210
352
-
- "nvidia,tegra186-sor": for Tegra186
353
-
- "nvidia,tegra186-sor1": for Tegra186
354
-
- reg: Physical base address and length of the controller's registers.
355
-
- interrupts: The interrupt outputs from the controller.
356
-
- clocks: Must contain an entry for each entry in clock-names.
357
-
See ../clocks/clock-bindings.txt for details.
358
-
- clock-names: Must include the following entries:
359
-
- sor: clock input for the SOR hardware
360
-
- out: SOR output clock
361
-
- parent: input for the pixel clock
362
-
- dp: reference clock for the SOR clock
363
-
- safe: safe reference for the SOR clock during power up
364
-
365
-
For Tegra186 and later:
366
-
- pad: SOR pad output clock (on Tegra186 and later)
367
-
368
-
Obsolete:
369
-
- source: source clock for the SOR clock (obsolete, use "out" instead)
370
-
371
-
- resets: Must contain an entry for each entry in reset-names.
372
-
See ../reset/reset.txt for details.
373
-
- reset-names: Must include the following entries:
374
-
- sor
375
-
376
-
Required properties on Tegra186 and later:
377
-
- nvidia,interface: index of the SOR interface
378
-
379
-
Optional properties:
380
-
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
381
-
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
382
-
- nvidia,edid: supplies a binary EDID blob
383
-
- nvidia,panel: phandle of a display panel
384
-
- nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
385
-
of the SOR, identified by the cell's index, is mapped via the crossbar to
386
-
the pad specified by the cell's value.
387
-
388
-
Optional properties when driving an eDP output:
389
-
- nvidia,dpaux: phandle to a DispayPort AUX interface
390
-
391
-
- dpaux: DisplayPort AUX interface
392
-
- compatible : Should contain one of the following:
393
-
- "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
394
-
- "nvidia,tegra210-dpaux": for Tegra210
395
-
- reg: Physical base address and length of the controller's registers.
396
-
- interrupts: The interrupt outputs from the controller.
397
-
- clocks: Must contain an entry for each entry in clock-names.
398
-
See ../clocks/clock-bindings.txt for details.
399
-
- clock-names: Must include the following entries:
400
-
- dpaux: clock input for the DPAUX hardware
401
-
- parent: reference clock
402
-
- resets: Must contain an entry for each entry in reset-names.
403
-
See ../reset/reset.txt for details.
404
-
- reset-names: Must include the following entries:
405
-
- dpaux
406
-
- vdd-supply: phandle of a supply that powers the DisplayPort link
407
-
- i2c-bus: Subnode where I2C slave devices are listed. This subnode
408
-
must be always present. If there are no I2C slave devices, an empty
409
-
node should be added. See ../../i2c/i2c.txt for more information.
410
-
411
-
See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
412
-
regarding the DPAUX pad controller bindings.
413
-
414
-
- vic: Video Image Compositor
415
-
- compatible : "nvidia,tegra<chip>-vic"
416
-
- reg: Physical base address and length of the controller's registers.
417
-
- interrupts: The interrupt outputs from the controller.
418
-
- clocks: Must contain an entry for each entry in clock-names.
419
-
See ../clocks/clock-bindings.txt for details.
420
-
- clock-names: Must include the following entries:
421
-
- vic: clock input for the VIC hardware
422
-
- resets: Must contain an entry for each entry in reset-names.
423
-
See ../reset/reset.txt for details.
424
-
- reset-names: Must include the following entries:
425
-
- vic
426
-
427
-
Optional properties:
428
-
- interconnects: Must contain entry for the VIC memory clients.
429
-
- interconnect-names: Must include name of the interconnect path for each
430
-
interconnect entry. Consult TRM documentation for information about
431
-
available memory clients, see MEMORY CONTROLLER section.
432
-
433
-
Example:
434
-
435
-
/ {
436
-
...
437
-
438
-
host1x {
439
-
compatible = "nvidia,tegra20-host1x", "simple-bus";
440
-
reg = <0x50000000 0x00024000>;
441
-
interrupts = <0 65 0x04 /* mpcore syncpt */
442
-
0 67 0x04>; /* mpcore general */
443
-
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
444
-
resets = <&tegra_car 28>;
445
-
reset-names = "host1x";
446
-
operating-points-v2 = <&dvfs_opp_table>;
447
-
power-domains = <&domain>;
448
-
449
-
#address-cells = <1>;
450
-
#size-cells = <1>;
451
-
452
-
ranges = <0x54000000 0x54000000 0x04000000>;
453
-
454
-
mpe {
455
-
compatible = "nvidia,tegra20-mpe";
456
-
reg = <0x54040000 0x00040000>;
457
-
interrupts = <0 68 0x04>;
458
-
clocks = <&tegra_car TEGRA20_CLK_MPE>;
459
-
resets = <&tegra_car 60>;
460
-
reset-names = "mpe";
461
-
operating-points-v2 = <&dvfs_opp_table>;
462
-
power-domains = <&domain>;
463
-
};
464
-
465
-
vi@54080000 {
466
-
compatible = "nvidia,tegra210-vi";
467
-
reg = <0x0 0x54080000 0x0 0x700>;
468
-
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
469
-
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
470
-
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
471
-
operating-points-v2 = <&dvfs_opp_table>;
472
-
473
-
clocks = <&tegra_car TEGRA210_CLK_VI>;
474
-
power-domains = <&pd_venc>;
475
-
476
-
#address-cells = <1>;
477
-
#size-cells = <1>;
478
-
479
-
ranges = <0x0 0x0 0x54080000 0x2000>;
480
-
481
-
ports {
482
-
#address-cells = <1>;
483
-
#size-cells = <0>;
484
-
485
-
port@0 {
486
-
reg = <0>;
487
-
imx219_vi_in0: endpoint {
488
-
remote-endpoint = <&imx219_csi_out0>;
489
-
};
490
-
};
491
-
};
492
-
493
-
csi@838 {
494
-
compatible = "nvidia,tegra210-csi";
495
-
reg = <0x838 0x1300>;
496
-
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
497
-
<&tegra_car TEGRA210_CLK_CILCD>,
498
-
<&tegra_car TEGRA210_CLK_CILE>,
499
-
<&tegra_car TEGRA210_CLK_CSI_TPG>;
500
-
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
501
-
<&tegra_car TEGRA210_CLK_PLL_P>,
502
-
<&tegra_car TEGRA210_CLK_PLL_P>;
503
-
assigned-clock-rates = <102000000>,
504
-
<102000000>,
505
-
<102000000>,
506
-
<972000000>;
507
-
508
-
clocks = <&tegra_car TEGRA210_CLK_CSI>,
509
-
<&tegra_car TEGRA210_CLK_CILAB>,
510
-
<&tegra_car TEGRA210_CLK_CILCD>,
511
-
<&tegra_car TEGRA210_CLK_CILE>,
512
-
<&tegra_car TEGRA210_CLK_CSI_TPG>;
513
-
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
514
-
power-domains = <&pd_sor>;
515
-
516
-
#address-cells = <1>;
517
-
#size-cells = <0>;
518
-
519
-
channel@0 {
520
-
reg = <0>;
521
-
nvidia,mipi-calibrate = <&mipi 0x001>;
522
-
523
-
ports {
524
-
#address-cells = <1>;
525
-
#size-cells = <0>;
526
-
527
-
port@0 {
528
-
reg = <0>;
529
-
imx219_csi_in0: endpoint {
530
-
data-lanes = <1 2>;
531
-
remote-endpoint = <&imx219_out0>;
532
-
};
533
-
};
534
-
535
-
port@1 {
536
-
reg = <1>;
537
-
imx219_csi_out0: endpoint {
538
-
remote-endpoint = <&imx219_vi_in0>;
539
-
};
540
-
};
541
-
};
542
-
};
543
-
};
544
-
};
545
-
546
-
epp {
547
-
compatible = "nvidia,tegra20-epp";
548
-
reg = <0x540c0000 0x00040000>;
549
-
interrupts = <0 70 0x04>;
550
-
clocks = <&tegra_car TEGRA20_CLK_EPP>;
551
-
resets = <&tegra_car 19>;
552
-
reset-names = "epp";
553
-
operating-points-v2 = <&dvfs_opp_table>;
554
-
power-domains = <&domain>;
555
-
};
556
-
557
-
isp {
558
-
compatible = "nvidia,tegra20-isp";
559
-
reg = <0x54100000 0x00040000>;
560
-
interrupts = <0 71 0x04>;
561
-
clocks = <&tegra_car TEGRA20_CLK_ISP>;
562
-
resets = <&tegra_car 23>;
563
-
reset-names = "isp";
564
-
};
565
-
566
-
gr2d {
567
-
compatible = "nvidia,tegra20-gr2d";
568
-
reg = <0x54140000 0x00040000>;
569
-
interrupts = <0 72 0x04>;
570
-
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
571
-
resets = <&tegra_car 21>;
572
-
reset-names = "2d";
573
-
operating-points-v2 = <&dvfs_opp_table>;
574
-
power-domains = <&domain>;
575
-
};
576
-
577
-
gr3d {
578
-
compatible = "nvidia,tegra20-gr3d";
579
-
reg = <0x54180000 0x00040000>;
580
-
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
581
-
resets = <&tegra_car 24>;
582
-
reset-names = "3d";
583
-
operating-points-v2 = <&dvfs_opp_table>;
584
-
power-domains = <&domain>;
585
-
};
586
-
587
-
dc@54200000 {
588
-
compatible = "nvidia,tegra20-dc";
589
-
reg = <0x54200000 0x00040000>;
590
-
interrupts = <0 73 0x04>;
591
-
clocks = <&tegra_car TEGRA20_CLK_DISP1>,
592
-
<&tegra_car TEGRA20_CLK_PLL_P>;
593
-
clock-names = "dc", "parent";
594
-
resets = <&tegra_car 27>;
595
-
reset-names = "dc";
596
-
operating-points-v2 = <&dvfs_opp_table>;
597
-
power-domains = <&domain>;
598
-
599
-
interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
600
-
<&mc TEGRA20_MC_DISPLAY0B &emc>,
601
-
<&mc TEGRA20_MC_DISPLAY0C &emc>,
602
-
<&mc TEGRA20_MC_DISPLAYHC &emc>;
603
-
interconnect-names = "wina",
604
-
"winb",
605
-
"winc",
606
-
"cursor";
607
-
608
-
rgb {
609
-
status = "disabled";
610
-
};
611
-
};
612
-
613
-
dc@54240000 {
614
-
compatible = "nvidia,tegra20-dc";
615
-
reg = <0x54240000 0x00040000>;
616
-
interrupts = <0 74 0x04>;
617
-
clocks = <&tegra_car TEGRA20_CLK_DISP2>,
618
-
<&tegra_car TEGRA20_CLK_PLL_P>;
619
-
clock-names = "dc", "parent";
620
-
resets = <&tegra_car 26>;
621
-
reset-names = "dc";
622
-
operating-points-v2 = <&dvfs_opp_table>;
623
-
power-domains = <&domain>;
624
-
625
-
interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
626
-
<&mc TEGRA20_MC_DISPLAY0BB &emc>,
627
-
<&mc TEGRA20_MC_DISPLAY0CB &emc>,
628
-
<&mc TEGRA20_MC_DISPLAYHCB &emc>;
629
-
interconnect-names = "wina",
630
-
"winb",
631
-
"winc",
632
-
"cursor";
633
-
634
-
rgb {
635
-
status = "disabled";
636
-
};
637
-
};
638
-
639
-
hdmi {
640
-
compatible = "nvidia,tegra20-hdmi";
641
-
reg = <0x54280000 0x00040000>;
642
-
interrupts = <0 75 0x04>;
643
-
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
644
-
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
645
-
clock-names = "hdmi", "parent";
646
-
resets = <&tegra_car 51>;
647
-
reset-names = "hdmi";
648
-
status = "disabled";
649
-
operating-points-v2 = <&dvfs_opp_table>;
650
-
};
651
-
652
-
tvo {
653
-
compatible = "nvidia,tegra20-tvo";
654
-
reg = <0x542c0000 0x00040000>;
655
-
interrupts = <0 76 0x04>;
656
-
clocks = <&tegra_car TEGRA20_CLK_TVO>;
657
-
status = "disabled";
658
-
operating-points-v2 = <&dvfs_opp_table>;
659
-
};
660
-
661
-
dsi {
662
-
compatible = "nvidia,tegra20-dsi";
663
-
reg = <0x54300000 0x00040000>;
664
-
clocks = <&tegra_car TEGRA20_CLK_DSI>,
665
-
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
666
-
clock-names = "dsi", "parent";
667
-
resets = <&tegra_car 48>;
668
-
reset-names = "dsi";
669
-
status = "disabled";
670
-
operating-points-v2 = <&dvfs_opp_table>;
671
-
};
672
-
};
673
-
674
-
...
675
-
};
+348
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+348
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra host1x controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: The host1x top-level node defines a number of children, each
14
+
representing one of the host1x client modules defined in this binding.
15
+
16
+
properties:
17
+
compatible:
18
+
oneOf:
19
+
- enum:
20
+
- nvidia,tegra20-host1x
21
+
- nvidia,tegra30-host1x
22
+
- nvidia,tegra114-host1x
23
+
- nvidia,tegra124-host1x
24
+
- nvidia,tegra210-host1x
25
+
- nvidia,tegra186-host1x
26
+
- nvidia,tegra194-host1x
27
+
28
+
- items:
29
+
- const: nvidia,tegra132-host1x
30
+
- const: nvidia,tegra124-host1x
31
+
32
+
reg:
33
+
minItems: 1
34
+
maxItems: 2
35
+
36
+
reg-names:
37
+
minItems: 1
38
+
maxItems: 2
39
+
40
+
interrupts:
41
+
items:
42
+
- description: host1x syncpoint interrupt
43
+
- description: host1x general interrupt
44
+
minItems: 1
45
+
46
+
interrupt-names:
47
+
items:
48
+
- const: syncpt
49
+
- const: host1x
50
+
minItems: 1
51
+
52
+
'#address-cells':
53
+
description: The number of cells used to represent physical base addresses
54
+
in the host1x address space.
55
+
enum: [1, 2]
56
+
57
+
'#size-cells':
58
+
description: The number of cells used to represent the size of an address
59
+
range in the host1x address space.
60
+
enum: [1, 2]
61
+
62
+
ranges:
63
+
maxItems: 1
64
+
65
+
clocks:
66
+
description: Must contain one entry, for the module clock. See
67
+
../clocks/clock-bindings.txt for details.
68
+
69
+
clock-names:
70
+
items:
71
+
- const: host1x
72
+
73
+
resets:
74
+
minItems: 1 # MC reset is optional on Tegra186 and later
75
+
items:
76
+
- description: module reset
77
+
- description: memory client hotflush reset
78
+
79
+
reset-names:
80
+
minItems: 1 # MC reset is optional on Tegra186 and later
81
+
items:
82
+
- const: host1x
83
+
- const: mc
84
+
85
+
iommus:
86
+
maxItems: 1
87
+
88
+
interconnects:
89
+
items:
90
+
- description: memory read client for host1x
91
+
92
+
interconnect-names:
93
+
items:
94
+
- const: dma-mem # read
95
+
96
+
operating-points-v2:
97
+
$ref: "/schemas/types.yaml#/definitions/phandle"
98
+
99
+
power-domains:
100
+
items:
101
+
- description: phandle to the HEG or core power domain
102
+
103
+
required:
104
+
- compatible
105
+
- interrupts
106
+
- interrupt-names
107
+
- '#address-cells'
108
+
- '#size-cells'
109
+
- ranges
110
+
- reg
111
+
- clocks
112
+
- clock-names
113
+
- resets
114
+
- reset-names
115
+
116
+
unevaluatedProperties:
117
+
type: object
118
+
119
+
allOf:
120
+
- if:
121
+
properties:
122
+
compatible:
123
+
contains:
124
+
enum:
125
+
- nvidia,tegra186-host1x
126
+
- nvidia,tegra194-host1x
127
+
then:
128
+
properties:
129
+
reg-names:
130
+
items:
131
+
- const: hypervisor
132
+
- const: vm
133
+
134
+
reg:
135
+
items:
136
+
- description: physical base address and length of the register
137
+
region assigned to the VM
138
+
- description: physical base address and length of the register
139
+
region used by the hypervisor
140
+
141
+
resets:
142
+
maxItems: 1
143
+
144
+
reset-names:
145
+
maxItems: 1
146
+
147
+
required:
148
+
- reg-names
149
+
150
+
examples:
151
+
- |
152
+
#include <dt-bindings/clock/tegra20-car.h>
153
+
#include <dt-bindings/gpio/tegra-gpio.h>
154
+
#include <dt-bindings/memory/tegra20-mc.h>
155
+
156
+
host1x@50000000 {
157
+
compatible = "nvidia,tegra20-host1x";
158
+
reg = <0x50000000 0x00024000>;
159
+
interrupts = <0 65 0x04 /* mpcore syncpt */
160
+
0 67 0x04>; /* mpcore general */
161
+
interrupt-names = "syncpt", "host1x";
162
+
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
163
+
clock-names = "host1x";
164
+
resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
165
+
reset-names = "host1x", "mc";
166
+
167
+
#address-cells = <1>;
168
+
#size-cells = <1>;
169
+
170
+
ranges = <0x54000000 0x54000000 0x04000000>;
171
+
172
+
mpe@54040000 {
173
+
compatible = "nvidia,tegra20-mpe";
174
+
reg = <0x54040000 0x00040000>;
175
+
interrupts = <0 68 0x04>;
176
+
clocks = <&tegra_car TEGRA20_CLK_MPE>;
177
+
resets = <&tegra_car 60>;
178
+
reset-names = "mpe";
179
+
};
180
+
181
+
vi@54080000 {
182
+
compatible = "nvidia,tegra20-vi";
183
+
reg = <0x54080000 0x00040000>;
184
+
interrupts = <0 69 0x04>;
185
+
clocks = <&tegra_car TEGRA20_CLK_VI>;
186
+
resets = <&tegra_car 100>;
187
+
reset-names = "vi";
188
+
};
189
+
190
+
epp@540c0000 {
191
+
compatible = "nvidia,tegra20-epp";
192
+
reg = <0x540c0000 0x00040000>;
193
+
interrupts = <0 70 0x04>;
194
+
clocks = <&tegra_car TEGRA20_CLK_EPP>;
195
+
resets = <&tegra_car 19>;
196
+
reset-names = "epp";
197
+
};
198
+
199
+
isp@54100000 {
200
+
compatible = "nvidia,tegra20-isp";
201
+
reg = <0x54100000 0x00040000>;
202
+
interrupts = <0 71 0x04>;
203
+
clocks = <&tegra_car TEGRA20_CLK_ISP>;
204
+
resets = <&tegra_car 23>;
205
+
reset-names = "isp";
206
+
};
207
+
208
+
gr2d@54140000 {
209
+
compatible = "nvidia,tegra20-gr2d";
210
+
reg = <0x54140000 0x00040000>;
211
+
interrupts = <0 72 0x04>;
212
+
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
213
+
resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
214
+
reset-names = "2d", "mc";
215
+
};
216
+
217
+
gr3d@54180000 {
218
+
compatible = "nvidia,tegra20-gr3d";
219
+
reg = <0x54180000 0x00040000>;
220
+
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
221
+
resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
222
+
reset-names = "3d", "mc";
223
+
};
224
+
225
+
dc@54200000 {
226
+
compatible = "nvidia,tegra20-dc";
227
+
reg = <0x54200000 0x00040000>;
228
+
interrupts = <0 73 0x04>;
229
+
clocks = <&tegra_car TEGRA20_CLK_DISP1>;
230
+
clock-names = "dc";
231
+
resets = <&tegra_car 27>;
232
+
reset-names = "dc";
233
+
234
+
rgb {
235
+
};
236
+
};
237
+
238
+
dc@54240000 {
239
+
compatible = "nvidia,tegra20-dc";
240
+
reg = <0x54240000 0x00040000>;
241
+
interrupts = <0 74 0x04>;
242
+
clocks = <&tegra_car TEGRA20_CLK_DISP2>;
243
+
clock-names = "dc";
244
+
resets = <&tegra_car 26>;
245
+
reset-names = "dc";
246
+
247
+
rgb {
248
+
};
249
+
};
250
+
251
+
hdmi@54280000 {
252
+
compatible = "nvidia,tegra20-hdmi";
253
+
reg = <0x54280000 0x00040000>;
254
+
interrupts = <0 75 0x04>;
255
+
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
256
+
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
257
+
clock-names = "hdmi", "parent";
258
+
resets = <&tegra_car 51>;
259
+
reset-names = "hdmi";
260
+
261
+
hdmi-supply = <&vdd_5v0_hdmi>;
262
+
pll-supply = <&vdd_hdmi_pll>;
263
+
vdd-supply = <&vdd_3v3_hdmi>;
264
+
265
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
266
+
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
267
+
};
268
+
269
+
tvo@542c0000 {
270
+
compatible = "nvidia,tegra20-tvo";
271
+
reg = <0x542c0000 0x00040000>;
272
+
interrupts = <0 76 0x04>;
273
+
clocks = <&tegra_car TEGRA20_CLK_TVO>;
274
+
};
275
+
276
+
dsi@54300000 {
277
+
compatible = "nvidia,tegra20-dsi";
278
+
reg = <0x54300000 0x00040000>;
279
+
clocks = <&tegra_car TEGRA20_CLK_DSI>,
280
+
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
281
+
clock-names = "dsi", "parent";
282
+
resets = <&tegra_car 48>;
283
+
reset-names = "dsi";
284
+
};
285
+
};
286
+
287
+
- |
288
+
#include <dt-bindings/clock/tegra210-car.h>
289
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
290
+
#include <dt-bindings/memory/tegra210-mc.h>
291
+
292
+
host1x@50000000 {
293
+
compatible = "nvidia,tegra210-host1x";
294
+
reg = <0x50000000 0x00024000>;
295
+
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
296
+
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
297
+
interrupt-names = "syncpt", "host1x";
298
+
clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
299
+
clock-names = "host1x";
300
+
resets = <&tegra_car 28>;
301
+
reset-names = "host1x";
302
+
303
+
#address-cells = <1>;
304
+
#size-cells = <1>;
305
+
306
+
ranges = <0x54000000 0x54000000 0x01000000>;
307
+
iommus = <&mc TEGRA_SWGROUP_HC>;
308
+
309
+
vi@54080000 {
310
+
compatible = "nvidia,tegra210-vi";
311
+
reg = <0x54080000 0x00000700>;
312
+
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
313
+
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
314
+
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
315
+
316
+
clocks = <&tegra_car TEGRA210_CLK_VI>;
317
+
power-domains = <&pd_venc>;
318
+
319
+
#address-cells = <1>;
320
+
#size-cells = <1>;
321
+
322
+
ranges = <0x0 0x54080000 0x2000>;
323
+
324
+
csi@838 {
325
+
compatible = "nvidia,tegra210-csi";
326
+
reg = <0x838 0x1300>;
327
+
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
328
+
<&tegra_car TEGRA210_CLK_CILCD>,
329
+
<&tegra_car TEGRA210_CLK_CILE>,
330
+
<&tegra_car TEGRA210_CLK_CSI_TPG>;
331
+
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
332
+
<&tegra_car TEGRA210_CLK_PLL_P>,
333
+
<&tegra_car TEGRA210_CLK_PLL_P>;
334
+
assigned-clock-rates = <102000000>,
335
+
<102000000>,
336
+
<102000000>,
337
+
<972000000>;
338
+
339
+
clocks = <&tegra_car TEGRA210_CLK_CSI>,
340
+
<&tegra_car TEGRA210_CLK_CILAB>,
341
+
<&tegra_car TEGRA210_CLK_CILCD>,
342
+
<&tegra_car TEGRA210_CLK_CILE>,
343
+
<&tegra_car TEGRA210_CLK_CSI_TPG>;
344
+
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
345
+
power-domains = <&pd_sor>;
346
+
};
347
+
};
348
+
};
+67
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
+67
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra ISP processor
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- nvidia,tegra20-isp
17
+
- nvidia,tegra30-isp
18
+
- nvidia,tegra210-isp
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: module clock
29
+
30
+
resets:
31
+
items:
32
+
- description: module reset
33
+
34
+
reset-names:
35
+
items:
36
+
- const: isp
37
+
38
+
iommus:
39
+
maxItems: 1
40
+
41
+
interconnects:
42
+
items:
43
+
- description: memory write client
44
+
45
+
interconnect-names:
46
+
items:
47
+
- const: dma-mem # write
48
+
49
+
power-domains:
50
+
items:
51
+
- description: phandle to the VENC or core power domain
52
+
53
+
additionalProperties: false
54
+
55
+
examples:
56
+
- |
57
+
#include <dt-bindings/clock/tegra20-car.h>
58
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
59
+
60
+
isp@54100000 {
61
+
compatible = "nvidia,tegra20-isp";
62
+
reg = <0x54100000 0x00040000>;
63
+
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
64
+
clocks = <&tegra_car TEGRA20_CLK_ISP>;
65
+
resets = <&tegra_car 23>;
66
+
reset-names = "isp";
67
+
};
+73
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
+73
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Video Encoder
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^mpe@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra20-mpe
20
+
- nvidia,tegra30-mpe
21
+
- nvidia,tegra114-mpe
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
items:
31
+
- description: module clock
32
+
33
+
resets:
34
+
items:
35
+
- description: module reset
36
+
37
+
reset-names:
38
+
items:
39
+
- const: mpe
40
+
41
+
iommus:
42
+
maxItems: 1
43
+
44
+
interconnects:
45
+
minItems: 6
46
+
maxItems: 6
47
+
48
+
interconnect-names:
49
+
minItems: 6
50
+
maxItems: 6
51
+
52
+
operating-points-v2:
53
+
$ref: "/schemas/types.yaml#/definitions/phandle"
54
+
55
+
power-domains:
56
+
items:
57
+
- description: phandle to the MPE power domain
58
+
59
+
additionalProperties: false
60
+
61
+
examples:
62
+
- |
63
+
#include <dt-bindings/clock/tegra20-car.h>
64
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
65
+
66
+
mpe@54040000 {
67
+
compatible = "nvidia,tegra20-mpe";
68
+
reg = <0x54040000 0x00040000>;
69
+
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
70
+
clocks = <&tegra_car TEGRA20_CLK_MPE>;
71
+
resets = <&tegra_car 60>;
72
+
reset-names = "mpe";
73
+
};
+58
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
+58
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra TV Encoder Output
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^tvo@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra20-tvo
20
+
- nvidia,tegra30-tvo
21
+
- nvidia,tegra114-tvo
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
items:
31
+
- description: module clock
32
+
33
+
operating-points-v2:
34
+
$ref: "/schemas/types.yaml#/definitions/phandle"
35
+
36
+
power-domains:
37
+
items:
38
+
- description: phandle to the core power domain
39
+
40
+
additionalProperties: false
41
+
42
+
required:
43
+
- compatible
44
+
- reg
45
+
- interrupts
46
+
- clocks
47
+
48
+
examples:
49
+
- |
50
+
#include <dt-bindings/clock/tegra20-car.h>
51
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
52
+
53
+
tvo@542c0000 {
54
+
compatible = "nvidia,tegra20-tvo";
55
+
reg = <0x542c0000 0x00040000>;
56
+
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
57
+
clocks = <&tegra_car TEGRA20_CLK_TVO>;
58
+
};
+163
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
+163
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Video Input controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^vi@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
oneOf:
19
+
- const: nvidia,tegra20-vi
20
+
- const: nvidia,tegra30-vi
21
+
- const: nvidia,tegra114-vi
22
+
- const: nvidia,tegra124-vi
23
+
- items:
24
+
- const: nvidia,tegra132-vi
25
+
- const: nvidia,tegra124-vi
26
+
- const: nvidia,tegra210-vi
27
+
- const: nvidia,tegra186-vi
28
+
- const: nvidia,tegra194-vi
29
+
30
+
reg:
31
+
maxItems: 1
32
+
33
+
interrupts:
34
+
maxItems: 1
35
+
36
+
clocks:
37
+
maxItems: 1
38
+
39
+
resets:
40
+
items:
41
+
- description: module reset
42
+
43
+
reset-names:
44
+
items:
45
+
- const: vi
46
+
47
+
iommus:
48
+
maxItems: 1
49
+
50
+
interconnects:
51
+
minItems: 4
52
+
maxItems: 5
53
+
54
+
interconnect-names:
55
+
minItems: 4
56
+
maxItems: 5
57
+
58
+
operating-points-v2:
59
+
$ref: "/schemas/types.yaml#/definitions/phandle"
60
+
61
+
power-domains:
62
+
items:
63
+
- description: phandle to the VENC power domain
64
+
65
+
"#address-cells":
66
+
const: 1
67
+
68
+
"#size-cells":
69
+
const: 1
70
+
71
+
ranges:
72
+
maxItems: 1
73
+
74
+
avdd-dsi-csi-supply:
75
+
description: DSI/CSI power supply. Must supply 1.2 V.
76
+
77
+
patternProperties:
78
+
"^csi@[0-9a-f]+$":
79
+
type: object
80
+
81
+
additionalProperties: false
82
+
83
+
required:
84
+
- compatible
85
+
- reg
86
+
- interrupts
87
+
- clocks
88
+
89
+
allOf:
90
+
- if:
91
+
properties:
92
+
compatible:
93
+
contains:
94
+
enum:
95
+
- nvidia,tegra20-vi
96
+
- nvidia,tegra30-vi
97
+
- nvidia,tegra114-vi
98
+
- nvidia,tegra124-vi
99
+
then:
100
+
required:
101
+
- resets
102
+
- reset-names
103
+
else:
104
+
required:
105
+
- power-domains
106
+
107
+
examples:
108
+
- |
109
+
#include <dt-bindings/clock/tegra20-car.h>
110
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
111
+
112
+
vi@54080000 {
113
+
compatible = "nvidia,tegra20-vi";
114
+
reg = <0x54080000 0x00040000>;
115
+
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
116
+
clocks = <&tegra_car TEGRA20_CLK_VI>;
117
+
resets = <&tegra_car 100>;
118
+
reset-names = "vi";
119
+
};
120
+
121
+
- |
122
+
#include <dt-bindings/clock/tegra210-car.h>
123
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
124
+
125
+
vi@54080000 {
126
+
compatible = "nvidia,tegra210-vi";
127
+
reg = <0x54080000 0x00000700>;
128
+
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
129
+
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
130
+
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
131
+
132
+
clocks = <&tegra_car TEGRA210_CLK_VI>;
133
+
power-domains = <&pd_venc>;
134
+
135
+
#address-cells = <1>;
136
+
#size-cells = <1>;
137
+
138
+
ranges = <0x0 0x54080000 0x2000>;
139
+
140
+
csi@838 {
141
+
compatible = "nvidia,tegra210-csi";
142
+
reg = <0x838 0x1300>;
143
+
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
144
+
<&tegra_car TEGRA210_CLK_CILCD>,
145
+
<&tegra_car TEGRA210_CLK_CILE>,
146
+
<&tegra_car TEGRA210_CLK_CSI_TPG>;
147
+
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
148
+
<&tegra_car TEGRA210_CLK_PLL_P>,
149
+
<&tegra_car TEGRA210_CLK_PLL_P>;
150
+
assigned-clock-rates = <102000000>,
151
+
<102000000>,
152
+
<102000000>,
153
+
<972000000>;
154
+
155
+
clocks = <&tegra_car TEGRA210_CLK_CSI>,
156
+
<&tegra_car TEGRA210_CLK_CILAB>,
157
+
<&tegra_car TEGRA210_CLK_CILCD>,
158
+
<&tegra_car TEGRA210_CLK_CILE>,
159
+
<&tegra_car TEGRA210_CLK_CSI_TPG>;
160
+
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
161
+
power-domains = <&pd_sor>;
162
+
};
163
+
};
+52
Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
+52
Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra CSI controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^csi@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra210-csi
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
clocks:
25
+
items:
26
+
- description: module clock
27
+
- description: A/B lanes clock
28
+
- description: C/D lanes clock
29
+
- description: E lane clock
30
+
- description: test pattern generator clock
31
+
32
+
clock-names:
33
+
items:
34
+
- const: csi
35
+
- const: cilab
36
+
- const: cilcd
37
+
- const: cile
38
+
- const: csi_tpg
39
+
40
+
power-domains:
41
+
maxItems: 1
42
+
43
+
additionalProperties: false
44
+
45
+
required:
46
+
- compatible
47
+
- reg
48
+
- clocks
49
+
- clock-names
50
+
- power-domains
51
+
52
+
# see nvidia,tegra20-vi.yaml for an example
-59
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
-59
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
···
1
-
Device tree binding for NVIDIA Tegra DPAUX pad controller
2
-
========================================================
3
-
4
-
The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins
5
-
which can be assigned to either the DPAUX channel or to an I2C
6
-
controller.
7
-
8
-
This document defines the device-specific binding for the DPAUX pad
9
-
controller. Refer to pinctrl-bindings.txt in this directory for generic
10
-
information about pin controller device tree bindings. Please refer to
11
-
the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more
12
-
details on the DPAUX binding.
13
-
14
-
Pin muxing:
15
-
-----------
16
-
17
-
Child nodes contain the pinmux configurations following the conventions
18
-
from the pinctrl-bindings.txt document.
19
-
20
-
Since only three configurations are possible, only three child nodes are
21
-
needed to describe the pin mux'ing options for the DPAUX pads.
22
-
Furthermore, given that the pad functions are only applicable to a
23
-
single set of pads, the child nodes only need to describe the pad group
24
-
the functions are being applied to rather than the individual pads.
25
-
26
-
Required properties:
27
-
- groups: Must be "dpaux-io"
28
-
- function: Must be either "aux", "i2c" or "off".
29
-
30
-
Example:
31
-
--------
32
-
33
-
dpaux@545c0000 {
34
-
...
35
-
36
-
state_dpaux_aux: pinmux-aux {
37
-
groups = "dpaux-io";
38
-
function = "aux";
39
-
};
40
-
41
-
state_dpaux_i2c: pinmux-i2c {
42
-
groups = "dpaux-io";
43
-
function = "i2c";
44
-
};
45
-
46
-
state_dpaux_off: pinmux-off {
47
-
groups = "dpaux-io";
48
-
function = "off";
49
-
};
50
-
};
51
-
52
-
...
53
-
54
-
i2c@7000d100 {
55
-
...
56
-
pinctrl-0 = <&state_dpaux_i2c>;
57
-
pinctrl-1 = <&state_dpaux_off>;
58
-
pinctrl-names = "default", "idle";
59
-
};