tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'phy-fixes-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy fixes from Vinod Koul:

- mapphone-mdm6600 runtime pm & pinctrl handling fixes

- Qualcomm qmp usb pcs register fixes, qmp pcie register size warning
fix, m31 fixes for wrong pointer in PTR_ERR and dropping wrong vreg
check, qmp combo fix for 8550 power config register

- realtek usb fix for debugfs_create_dir() and kconfig dependency

* tag 'phy-fixes-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
phy: realtek: Realtek PHYs should depend on ARCH_REALTEK
phy: qualcomm: Fix typos in comments
phy: qcom-qmp-combo: initialize PCS_USB registers
phy: qcom-qmp-combo: Square out 8550 POWER_STATE_CONFIG1
phy: qcom: m31: Remove unwanted qphy->vreg is NULL check
phy: realtek: usb: Drop unnecessary error check for debugfs_create_dir()
phy: qcom: phy-qcom-m31: change m31_ipq5332_regs to static
phy: qcom: phy-qcom-m31: fix wrong pointer pass to PTR_ERR()
dt-bindings: phy: qcom,ipq8074-qmp-pcie: fix warning regarding reg size
phy: qcom-qmp-usb: split PCS_USB init table for sc8280xp and sa8775p
phy: qcom-qmp-usb: initialize PCS_USB registers
phy: mapphone-mdm6600: Fix pinctrl_pm handling for sleep pins
phy: mapphone-mdm6600: Fix runtime PM for remove
phy: mapphone-mdm6600: Fix runtime disable on probe

Linus Torvalds fe3cfe86 70e65afc

options
unified split
Changed files
+58 -49
Documentation
devicetree
bindings
phy
qcom,ipq8074-qmp-pcie-phy.yaml
drivers
phy
motorola
phy-mapphone-mdm6600.c
qualcomm
phy-qcom-apq8064-sata.c
phy-qcom-m31.c
phy-qcom-qmp-combo.c
phy-qcom-qmp-pcs-usb-v6.h
phy-qcom-qmp-usb.c
realtek
Kconfig
phy-rtk-usb2.c
phy-rtk-usb3.c
+1 -1
Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
··· 70 70 71 71 phy@84000 { 72 72 compatible = "qcom,ipq6018-qmp-pcie-phy"; 73 - reg = <0x0 0x00084000 0x0 0x1000>; 73 + reg = <0x00084000 0x1000>; 74 74 75 75 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 76 76 <&gcc GCC_PCIE0_AHB_CLK>,
+18 -20
drivers/phy/motorola/phy-mapphone-mdm6600.c
··· 122 122 { 123 123 struct phy_mdm6600 *ddata = phy_get_drvdata(x); 124 124 struct gpio_desc *enable_gpio = ddata->ctrl_gpios[PHY_MDM6600_ENABLE]; 125 - int error; 126 125 127 126 if (!ddata->enabled) 128 127 return -ENODEV; 129 - 130 - error = pinctrl_pm_select_default_state(ddata->dev); 131 - if (error) 132 - dev_warn(ddata->dev, "%s: error with default_state: %i\n", 133 - __func__, error); 134 128 135 129 gpiod_set_value_cansleep(enable_gpio, 1); 136 130 ··· 153 159 } 154 160 155 161 gpiod_set_value_cansleep(enable_gpio, 0); 156 - 157 - error = pinctrl_pm_select_sleep_state(ddata->dev); 158 - if (error) 159 - dev_warn(ddata->dev, "%s: error with sleep_state: %i\n", 160 - __func__, error); 161 162 162 163 return 0; 163 164 } ··· 445 456 { 446 457 struct gpio_desc *reset_gpio = 447 458 ddata->ctrl_gpios[PHY_MDM6600_RESET]; 459 + int error; 448 460 449 461 ddata->enabled = false; 450 462 phy_mdm6600_cmd(ddata, PHY_MDM6600_CMD_BP_SHUTDOWN_REQ); ··· 461 471 } else { 462 472 dev_err(ddata->dev, "Timed out powering down\n"); 463 473 } 474 + 475 + /* 476 + * Keep reset gpio high with padconf internal pull-up resistor to 477 + * prevent modem from waking up during deeper SoC idle states. The 478 + * gpio bank lines can have glitches if not in the always-on wkup 479 + * domain. 480 + */ 481 + error = pinctrl_pm_select_sleep_state(ddata->dev); 482 + if (error) 483 + dev_warn(ddata->dev, "%s: error with sleep_state: %i\n", 484 + __func__, error); 464 485 } 465 486 466 487 static void phy_mdm6600_deferred_power_on(struct work_struct *work) ··· 572 571 ddata->dev = &pdev->dev; 573 572 platform_set_drvdata(pdev, ddata); 574 573 575 - /* Active state selected in phy_mdm6600_power_on() */ 576 - error = pinctrl_pm_select_sleep_state(ddata->dev); 577 - if (error) 578 - dev_warn(ddata->dev, "%s: error with sleep_state: %i\n", 579 - __func__, error); 580 - 581 574 error = phy_mdm6600_init_lines(ddata); 582 575 if (error) 583 576 return error; ··· 622 627 pm_runtime_put_autosuspend(ddata->dev); 623 628 624 629 cleanup: 625 - if (error < 0) 630 + if (error < 0) { 626 631 phy_mdm6600_device_power_off(ddata); 627 - pm_runtime_disable(ddata->dev); 628 - pm_runtime_dont_use_autosuspend(ddata->dev); 632 + pm_runtime_disable(ddata->dev); 633 + pm_runtime_dont_use_autosuspend(ddata->dev); 634 + } 635 + 629 636 return error; 630 637 } 631 638 ··· 636 639 struct phy_mdm6600 *ddata = platform_get_drvdata(pdev); 637 640 struct gpio_desc *reset_gpio = ddata->ctrl_gpios[PHY_MDM6600_RESET]; 638 641 642 + pm_runtime_get_noresume(ddata->dev); 639 643 pm_runtime_dont_use_autosuspend(ddata->dev); 640 644 pm_runtime_put_sync(ddata->dev); 641 645 pm_runtime_disable(ddata->dev);
+1 -1
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
··· 152 152 return ret; 153 153 } 154 154 155 - /* SATA phy calibrated succesfully, power up to functional mode */ 155 + /* SATA phy calibrated successfully, power up to functional mode */ 156 156 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); 157 157 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); 158 158 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
+3 -4
drivers/phy/qualcomm/phy-qcom-m31.c
··· 82 82 unsigned int nregs; 83 83 }; 84 84 85 - struct m31_phy_regs m31_ipq5332_regs[] = { 85 + static struct m31_phy_regs m31_ipq5332_regs[] = { 86 86 { 87 87 USB_PHY_CFG0, 88 88 UTMI_PHY_OVERRIDE_EN, ··· 172 172 173 173 ret = clk_prepare_enable(qphy->clk); 174 174 if (ret) { 175 - if (qphy->vreg) 176 - regulator_disable(qphy->vreg); 175 + regulator_disable(qphy->vreg); 177 176 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); 178 177 return ret; 179 178 } ··· 255 256 256 257 qphy->vreg = devm_regulator_get(dev, "vdda-phy"); 257 258 if (IS_ERR(qphy->vreg)) 258 - return dev_err_probe(dev, PTR_ERR(qphy->phy), 259 + return dev_err_probe(dev, PTR_ERR(qphy->vreg), 259 260 "failed to get vreg\n"); 260 261 261 262 phy_set_drvdata(qphy->phy, qphy);
+5 -1
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 859 859 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 860 860 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b), 861 861 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10), 862 - QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 863 862 }; 864 863 865 864 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 865 + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 866 866 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 867 867 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 868 868 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), ··· 2555 2555 void __iomem *tx2 = qmp->tx2; 2556 2556 void __iomem *rx2 = qmp->rx2; 2557 2557 void __iomem *pcs = qmp->pcs; 2558 + void __iomem *pcs_usb = qmp->pcs_usb; 2558 2559 void __iomem *status; 2559 2560 unsigned int val; 2560 2561 int ret; ··· 2576 2575 qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2577 2576 2578 2577 qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2578 + 2579 + if (pcs_usb) 2580 + qmp_combo_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num); 2579 2581 2580 2582 if (cfg->has_pwrdn_delay) 2581 2583 usleep_range(10, 20);
+2 -1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
··· 12 12 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc 13 13 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8 14 14 #define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc 15 - #define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1 0x90 15 + #define QPHY_USB_V6_PCS_POWER_STATE_CONFIG1 0x90 16 16 #define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188 17 17 #define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 18 18 #define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 ··· 23 23 #define QPHY_USB_V6_PCS_EQ_CONFIG1 0x1dc 24 24 #define QPHY_USB_V6_PCS_EQ_CONFIG5 0x1ec 25 25 26 + #define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1 0x00 26 27 #define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18 27 28 #define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c 28 29 #define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+19 -5
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
··· 1112 1112 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1113 1113 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1114 1114 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1115 - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1116 - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1117 1115 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1118 1116 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1119 1117 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1120 1118 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1121 1119 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1122 1120 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1121 + }; 1122 + 1123 + static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = { 1124 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1125 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1123 1126 }; 1124 1127 1125 1128 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = { ··· 1134 1131 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1135 1132 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1136 1133 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1137 - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1138 - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1139 - QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f), 1140 1134 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1141 1135 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1142 1136 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1143 1137 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1144 1138 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1145 1139 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1140 + }; 1141 + 1142 + static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = { 1143 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1144 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1145 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f), 1146 1146 }; 1147 1147 1148 1148 struct qmp_usb_offsets { ··· 1389 1383 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1390 1384 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl, 1391 1385 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl), 1386 + .pcs_usb_tbl = sa8775p_usb3_uniphy_pcs_usb_tbl, 1387 + .pcs_usb_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl), 1392 1388 .clk_list = qmp_v4_phy_clk_l, 1393 1389 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1394 1390 .reset_list = qcm2290_usb3phy_reset_l, ··· 1413 1405 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1414 1406 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl, 1415 1407 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl), 1408 + .pcs_usb_tbl = sc8280xp_usb3_uniphy_pcs_usb_tbl, 1409 + .pcs_usb_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl), 1416 1410 .clk_list = qmp_v4_phy_clk_l, 1417 1411 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1418 1412 .reset_list = qcm2290_usb3phy_reset_l, ··· 1713 1703 void __iomem *tx = qmp->tx; 1714 1704 void __iomem *rx = qmp->rx; 1715 1705 void __iomem *pcs = qmp->pcs; 1706 + void __iomem *pcs_usb = qmp->pcs_usb; 1716 1707 void __iomem *status; 1717 1708 unsigned int val; 1718 1709 int ret; ··· 1736 1725 } 1737 1726 1738 1727 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1728 + 1729 + if (pcs_usb) 1730 + qmp_usb_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num); 1739 1731 1740 1732 if (cfg->has_pwrdn_delay) 1741 1733 usleep_range(10, 20);
+5
drivers/phy/realtek/Kconfig
··· 2 2 # 3 3 # Phy drivers for Realtek platforms 4 4 # 5 + 6 + if ARCH_REALTEK || COMPILE_TEST 7 + 5 8 config PHY_RTK_RTD_USB2PHY 6 9 tristate "Realtek RTD USB2 PHY Transceiver Driver" 7 10 depends on USB_SUPPORT ··· 28 25 The DHC (digital home center) RTD series SoCs used the Synopsys 29 26 DWC3 USB IP. This driver will do the PHY initialization 30 27 of the parameters. 28 + 29 + endif # ARCH_REALTEK || COMPILE_TEST
+2 -8
drivers/phy/realtek/phy-rtk-usb2.c
··· 853 853 854 854 rtk_phy->debug_dir = debugfs_create_dir(dev_name(rtk_phy->dev), 855 855 phy_debug_root); 856 - if (!rtk_phy->debug_dir) 857 - return; 858 856 859 - if (!debugfs_create_file("parameter", 0444, rtk_phy->debug_dir, rtk_phy, 860 - &rtk_usb2_parameter_fops)) 861 - goto file_error; 857 + debugfs_create_file("parameter", 0444, rtk_phy->debug_dir, rtk_phy, 858 + &rtk_usb2_parameter_fops); 862 859 863 860 return; 864 - 865 - file_error: 866 - debugfs_remove_recursive(rtk_phy->debug_dir); 867 861 } 868 862 869 863 static inline void remove_debug_files(struct rtk_phy *rtk_phy)
+2 -8
drivers/phy/realtek/phy-rtk-usb3.c
··· 416 416 return; 417 417 418 418 rtk_phy->debug_dir = debugfs_create_dir(dev_name(rtk_phy->dev), phy_debug_root); 419 - if (!rtk_phy->debug_dir) 420 - return; 421 419 422 - if (!debugfs_create_file("parameter", 0444, rtk_phy->debug_dir, rtk_phy, 423 - &rtk_usb3_parameter_fops)) 424 - goto file_error; 420 + debugfs_create_file("parameter", 0444, rtk_phy->debug_dir, rtk_phy, 421 + &rtk_usb3_parameter_fops); 425 422 426 423 return; 427 - 428 - file_error: 429 - debugfs_remove_recursive(rtk_phy->debug_dir); 430 424 } 431 425 432 426 static inline void remove_debug_files(struct rtk_phy *rtk_phy)