···6262#define MIE (1 << 3) /* master if enable */6363#define TSBE (1 << 2)6464#define FSB (1 << 1) /* force stop bit */6565-#define ESG (1 << 0) /* en startbit gen */6565+#define ESG (1 << 0) /* enable start bit gen */66666767/* ICSSR (also for ICSIER) */6868#define GCAR (1 << 6) /* general call received */···331331332332 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);333333 /*334334- * We don't have a testcase but the HW engineers say that the write order334334+ * We don't have a test case but the HW engineers say that the write order335335 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since336336 * it didn't cause a drawback for me, let's rather be safe than sorry.337337 */···489489490490 /*491491 * Try to use DMA to transmit the rest of the data if492492- * address transfer pashe just finished.492492+ * address transfer phase just finished.493493 */494494 if (msr & MAT)495495 rcar_i2c_dma(priv);