ARM: dts: use macros in clock bindings for exynos5250

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

The patch replaces magic numbers with macros defined in DT header
in exynos5250 clock bindings.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

authored by

Andrzej Hajda and committed by

Kukjin Kim 12 years ago fe273c3e 1c75a78a

+60 -208

2 changed files

expand all

Documentation

devicetree

bindings

clock

exynos5250-clock.txt

arch

arm

boot

dts

exynos5250.dtsi

+6 -157

Documentation/devicetree/bindings/clock/exynos5250-clock.txt

··· 13 13 14 14 - #clock-cells: should be 1. 15 15 16 - The following is the list of clocks generated by the controller. Each clock is 17 - assigned an identifier and client nodes use this identifier to specify the 18 - clock which they consume. 16 + Each clock is assigned an identifier and client nodes can use this identifier 17 + to specify the clock which they consume. 19 18 20 - 21 - [Core Clocks] 22 - 23 - Clock ID 24 - ---------------------------- 25 - 26 - fin_pll 1 27 - 28 - [Clock Gate for Special Clocks] 29 - 30 - Clock ID 31 - ---------------------------- 32 - 33 - sclk_cam_bayer 128 34 - sclk_cam0 129 35 - sclk_cam1 130 36 - sclk_gscl_wa 131 37 - sclk_gscl_wb 132 38 - sclk_fimd1 133 39 - sclk_mipi1 134 40 - sclk_dp 135 41 - sclk_hdmi 136 42 - sclk_pixel 137 43 - sclk_audio0 138 44 - sclk_mmc0 139 45 - sclk_mmc1 140 46 - sclk_mmc2 141 47 - sclk_mmc3 142 48 - sclk_sata 143 49 - sclk_usb3 144 50 - sclk_jpeg 145 51 - sclk_uart0 146 52 - sclk_uart1 147 53 - sclk_uart2 148 54 - sclk_uart3 149 55 - sclk_pwm 150 56 - sclk_audio1 151 57 - sclk_audio2 152 58 - sclk_spdif 153 59 - sclk_spi0 154 60 - sclk_spi1 155 61 - sclk_spi2 156 62 - div_i2s1 157 63 - div_i2s2 158 64 - sclk_hdmiphy 159 65 - div_pcm0 160 66 - 67 - 68 - [Peripheral Clock Gates] 69 - 70 - Clock ID 71 - ---------------------------- 72 - 73 - gscl0 256 74 - gscl1 257 75 - gscl2 258 76 - gscl3 259 77 - gscl_wa 260 78 - gscl_wb 261 79 - smmu_gscl0 262 80 - smmu_gscl1 263 81 - smmu_gscl2 264 82 - smmu_gscl3 265 83 - mfc 266 84 - smmu_mfcl 267 85 - smmu_mfcr 268 86 - rotator 269 87 - jpeg 270 88 - mdma1 271 89 - smmu_rotator 272 90 - smmu_jpeg 273 91 - smmu_mdma1 274 92 - pdma0 275 93 - pdma1 276 94 - sata 277 95 - usbotg 278 96 - mipi_hsi 279 97 - sdmmc0 280 98 - sdmmc1 281 99 - sdmmc2 282 100 - sdmmc3 283 101 - sromc 284 102 - usb2 285 103 - usb3 286 104 - sata_phyctrl 287 105 - sata_phyi2c 288 106 - uart0 289 107 - uart1 290 108 - uart2 291 109 - uart3 292 110 - uart4 293 111 - i2c0 294 112 - i2c1 295 113 - i2c2 296 114 - i2c3 297 115 - i2c4 298 116 - i2c5 299 117 - i2c6 300 118 - i2c7 301 119 - i2c_hdmi 302 120 - adc 303 121 - spi0 304 122 - spi1 305 123 - spi2 306 124 - i2s1 307 125 - i2s2 308 126 - pcm1 309 127 - pcm2 310 128 - pwm 311 129 - spdif 312 130 - ac97 313 131 - hsi2c0 314 132 - hsi2c1 315 133 - hs12c2 316 134 - hs12c3 317 135 - chipid 318 136 - sysreg 319 137 - pmu 320 138 - cmu_top 321 139 - cmu_core 322 140 - cmu_mem 323 141 - tzpc0 324 142 - tzpc1 325 143 - tzpc2 326 144 - tzpc3 327 145 - tzpc4 328 146 - tzpc5 329 147 - tzpc6 330 148 - tzpc7 331 149 - tzpc8 332 150 - tzpc9 333 151 - hdmi_cec 334 152 - mct 335 153 - wdt 336 154 - rtc 337 155 - tmu 338 156 - fimd1 339 157 - mie1 340 158 - dsim0 341 159 - dp 342 160 - mixer 343 161 - hdmi 344 162 - g2d 345 163 - mdma0 346 164 - smmu_mdma0 347 165 - 166 - 167 - [Clock Muxes] 168 - 169 - Clock ID 170 - ---------------------------- 171 - mout_hdmi 1024 172 - 19 + All available clocks are defined as preprocessor macros in 20 + dt-bindings/clock/exynos5250.h header and can be used in device 21 + tree sources. 173 22 174 23 Example 1: An example of a clock controller node is listed below. 175 24 ··· 36 187 compatible = "samsung,exynos4210-uart"; 37 188 reg = <0x13820000 0x100>; 38 189 interrupts = <0 54 0>; 39 - clocks = <&clock 314>, <&clock 153>; 190 + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 40 191 clock-names = "uart", "clk_uart_baud0"; 41 192 };

+54 -51

arch/arm/boot/dts/exynos5250.dtsi

··· 17 17 * published by the Free Software Foundation. 18 18 */ 19 19 20 + #include <dt-bindings/clock/exynos5250.h> 20 21 #include "exynos5.dtsi" 21 22 #include "exynos5250-pinctrl.dtsi" 22 23 ··· 91 90 compatible = "samsung,exynos5250-audss-clock"; 92 91 reg = <0x03810000 0x0C>; 93 92 #clock-cells = <1>; 94 - clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>; 93 + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 94 + <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; 95 95 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 96 96 }; 97 97 ··· 117 115 interrupt-parent = <&mct_map>; 118 116 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 119 117 <4 0>, <5 0>; 120 - clocks = <&clock 1>, <&clock 335>; 118 + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 121 119 clock-names = "fin_pll", "mct"; 122 120 123 121 mct_map: mct-map { ··· 178 176 compatible = "samsung,exynos5250-wdt"; 179 177 reg = <0x101D0000 0x100>; 180 178 interrupts = <0 42 0>; 181 - clocks = <&clock 336>; 179 + clocks = <&clock CLK_WDT>; 182 180 clock-names = "watchdog"; 183 181 samsung,syscon-phandle = <&pmu_system_controller>; 184 182 }; ··· 187 185 compatible = "samsung,exynos5250-g2d"; 188 186 reg = <0x10850000 0x1000>; 189 187 interrupts = <0 91 0>; 190 - clocks = <&clock 345>; 188 + clocks = <&clock CLK_G2D>; 191 189 clock-names = "fimg2d"; 192 190 }; 193 191 ··· 196 194 reg = <0x11000000 0x10000>; 197 195 interrupts = <0 96 0>; 198 196 samsung,power-domain = <&pd_mfc>; 199 - clocks = <&clock 266>; 197 + clocks = <&clock CLK_MFC>; 200 198 clock-names = "mfc"; 201 199 }; 202 200 203 201 rtc@101E0000 { 204 - clocks = <&clock 337>; 202 + clocks = <&clock CLK_RTC>; 205 203 clock-names = "rtc"; 206 204 status = "disabled"; 207 205 }; ··· 210 208 compatible = "samsung,exynos5250-tmu"; 211 209 reg = <0x10060000 0x100>; 212 210 interrupts = <0 65 0>; 213 - clocks = <&clock 338>; 211 + clocks = <&clock CLK_TMU>; 214 212 clock-names = "tmu_apbif"; 215 213 }; 216 214 217 215 serial@12C00000 { 218 - clocks = <&clock 289>, <&clock 146>; 216 + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 219 217 clock-names = "uart", "clk_uart_baud0"; 220 218 }; 221 219 222 220 serial@12C10000 { 223 - clocks = <&clock 290>, <&clock 147>; 221 + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 224 222 clock-names = "uart", "clk_uart_baud0"; 225 223 }; 226 224 227 225 serial@12C20000 { 228 - clocks = <&clock 291>, <&clock 148>; 226 + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 229 227 clock-names = "uart", "clk_uart_baud0"; 230 228 }; 231 229 232 230 serial@12C30000 { 233 - clocks = <&clock 292>, <&clock 149>; 231 + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 234 232 clock-names = "uart", "clk_uart_baud0"; 235 233 }; 236 234 ··· 238 236 compatible = "samsung,exynos5-sata-ahci"; 239 237 reg = <0x122F0000 0x1ff>; 240 238 interrupts = <0 115 0>; 241 - clocks = <&clock 277>, <&clock 143>; 239 + clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 242 240 clock-names = "sata", "sclk_sata"; 243 241 }; 244 242 ··· 253 251 interrupts = <0 56 0>; 254 252 #address-cells = <1>; 255 253 #size-cells = <0>; 256 - clocks = <&clock 294>; 254 + clocks = <&clock CLK_I2C0>; 257 255 clock-names = "i2c"; 258 256 pinctrl-names = "default"; 259 257 pinctrl-0 = <&i2c0_bus>; ··· 266 264 interrupts = <0 57 0>; 267 265 #address-cells = <1>; 268 266 #size-cells = <0>; 269 - clocks = <&clock 295>; 267 + clocks = <&clock CLK_I2C1>; 270 268 clock-names = "i2c"; 271 269 pinctrl-names = "default"; 272 270 pinctrl-0 = <&i2c1_bus>; ··· 279 277 interrupts = <0 58 0>; 280 278 #address-cells = <1>; 281 279 #size-cells = <0>; 282 - clocks = <&clock 296>; 280 + clocks = <&clock CLK_I2C2>; 283 281 clock-names = "i2c"; 284 282 pinctrl-names = "default"; 285 283 pinctrl-0 = <&i2c2_bus>; ··· 292 290 interrupts = <0 59 0>; 293 291 #address-cells = <1>; 294 292 #size-cells = <0>; 295 - clocks = <&clock 297>; 293 + clocks = <&clock CLK_I2C3>; 296 294 clock-names = "i2c"; 297 295 pinctrl-names = "default"; 298 296 pinctrl-0 = <&i2c3_bus>; ··· 305 303 interrupts = <0 60 0>; 306 304 #address-cells = <1>; 307 305 #size-cells = <0>; 308 - clocks = <&clock 298>; 306 + clocks = <&clock CLK_I2C4>; 309 307 clock-names = "i2c"; 310 308 pinctrl-names = "default"; 311 309 pinctrl-0 = <&i2c4_bus>; ··· 318 316 interrupts = <0 61 0>; 319 317 #address-cells = <1>; 320 318 #size-cells = <0>; 321 - clocks = <&clock 299>; 319 + clocks = <&clock CLK_I2C5>; 322 320 clock-names = "i2c"; 323 321 pinctrl-names = "default"; 324 322 pinctrl-0 = <&i2c5_bus>; ··· 331 329 interrupts = <0 62 0>; 332 330 #address-cells = <1>; 333 331 #size-cells = <0>; 334 - clocks = <&clock 300>; 332 + clocks = <&clock CLK_I2C6>; 335 333 clock-names = "i2c"; 336 334 pinctrl-names = "default"; 337 335 pinctrl-0 = <&i2c6_bus>; ··· 344 342 interrupts = <0 63 0>; 345 343 #address-cells = <1>; 346 344 #size-cells = <0>; 347 - clocks = <&clock 301>; 345 + clocks = <&clock CLK_I2C7>; 348 346 clock-names = "i2c"; 349 347 pinctrl-names = "default"; 350 348 pinctrl-0 = <&i2c7_bus>; ··· 357 355 interrupts = <0 64 0>; 358 356 #address-cells = <1>; 359 357 #size-cells = <0>; 360 - clocks = <&clock 302>; 358 + clocks = <&clock CLK_I2C_HDMI>; 361 359 clock-names = "i2c"; 362 360 status = "disabled"; 363 361 }; ··· 367 365 reg = <0x121D0000 0x100>; 368 366 #address-cells = <1>; 369 367 #size-cells = <0>; 370 - clocks = <&clock 288>; 368 + clocks = <&clock CLK_SATA_PHYI2C>; 371 369 clock-names = "i2c"; 372 370 status = "disabled"; 373 371 }; ··· 382 380 dma-names = "tx", "rx"; 383 381 #address-cells = <1>; 384 382 #size-cells = <0>; 385 - clocks = <&clock 304>, <&clock 154>; 383 + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 386 384 clock-names = "spi", "spi_busclk0"; 387 385 pinctrl-names = "default"; 388 386 pinctrl-0 = <&spi0_bus>; ··· 398 396 dma-names = "tx", "rx"; 399 397 #address-cells = <1>; 400 398 #size-cells = <0>; 401 - clocks = <&clock 305>, <&clock 155>; 399 + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 402 400 clock-names = "spi", "spi_busclk0"; 403 401 pinctrl-names = "default"; 404 402 pinctrl-0 = <&spi1_bus>; ··· 414 412 dma-names = "tx", "rx"; 415 413 #address-cells = <1>; 416 414 #size-cells = <0>; 417 - clocks = <&clock 306>, <&clock 156>; 415 + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 418 416 clock-names = "spi", "spi_busclk0"; 419 417 pinctrl-names = "default"; 420 418 pinctrl-0 = <&spi2_bus>; ··· 426 424 #address-cells = <1>; 427 425 #size-cells = <0>; 428 426 reg = <0x12200000 0x1000>; 429 - clocks = <&clock 280>, <&clock 139>; 427 + clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 430 428 clock-names = "biu", "ciu"; 431 429 fifo-depth = <0x80>; 432 430 status = "disabled"; ··· 438 436 #address-cells = <1>; 439 437 #size-cells = <0>; 440 438 reg = <0x12210000 0x1000>; 441 - clocks = <&clock 281>, <&clock 140>; 439 + clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 442 440 clock-names = "biu", "ciu"; 443 441 fifo-depth = <0x80>; 444 442 status = "disabled"; ··· 450 448 #address-cells = <1>; 451 449 #size-cells = <0>; 452 450 reg = <0x12220000 0x1000>; 453 - clocks = <&clock 282>, <&clock 141>; 451 + clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 454 452 clock-names = "biu", "ciu"; 455 453 fifo-depth = <0x80>; 456 454 status = "disabled"; ··· 462 460 interrupts = <0 78 0>; 463 461 #address-cells = <1>; 464 462 #size-cells = <0>; 465 - clocks = <&clock 283>, <&clock 142>; 463 + clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 466 464 clock-names = "biu", "ciu"; 467 465 fifo-depth = <0x80>; 468 466 status = "disabled"; ··· 492 490 dmas = <&pdma1 12 493 491 &pdma1 11>; 494 492 dma-names = "tx", "rx"; 495 - clocks = <&clock 307>, <&clock 157>; 493 + clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; 496 494 clock-names = "iis", "i2s_opclk0"; 497 495 pinctrl-names = "default"; 498 496 pinctrl-0 = <&i2s1_bus>; ··· 505 503 dmas = <&pdma0 12 506 504 &pdma0 11>; 507 505 dma-names = "tx", "rx"; 508 - clocks = <&clock 308>, <&clock 158>; 506 + clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; 509 507 clock-names = "iis", "i2s_opclk0"; 510 508 pinctrl-names = "default"; 511 509 pinctrl-0 = <&i2s2_bus>; ··· 513 511 514 512 usb@12000000 { 515 513 compatible = "samsung,exynos5250-dwusb3"; 516 - clocks = <&clock 286>; 514 + clocks = <&clock CLK_USB3>; 517 515 clock-names = "usbdrd30"; 518 516 #address-cells = <1>; 519 517 #size-cells = <1>; ··· 530 528 usb3_phy: usbphy@12100000 { 531 529 compatible = "samsung,exynos5250-usb3phy"; 532 530 reg = <0x12100000 0x100>; 533 - clocks = <&clock 1>, <&clock 286>; 531 + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>; 534 532 clock-names = "ext_xtal", "usbdrd30"; 535 533 #address-cells = <1>; 536 534 #size-cells = <1>; ··· 546 544 reg = <0x12110000 0x100>; 547 545 interrupts = <0 71 0>; 548 546 549 - clocks = <&clock 285>; 547 + clocks = <&clock CLK_USB2>; 550 548 clock-names = "usbhost"; 551 549 }; 552 550 ··· 555 553 reg = <0x12120000 0x100>; 556 554 interrupts = <0 71 0>; 557 555 558 - clocks = <&clock 285>; 556 + clocks = <&clock CLK_USB2>; 559 557 clock-names = "usbhost"; 560 558 }; 561 559 562 560 usb2_phy: usbphy@12130000 { 563 561 compatible = "samsung,exynos5250-usb2phy"; 564 562 reg = <0x12130000 0x100>; 565 - clocks = <&clock 1>, <&clock 285>; 563 + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>; 566 564 clock-names = "ext_xtal", "usbhost"; 567 565 #address-cells = <1>; 568 566 #size-cells = <1>; ··· 579 577 reg = <0x12dd0000 0x100>; 580 578 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 581 579 #pwm-cells = <3>; 582 - clocks = <&clock 311>; 580 + clocks = <&clock CLK_PWM>; 583 581 clock-names = "timers"; 584 582 }; 585 583 ··· 594 592 compatible = "arm,pl330", "arm,primecell"; 595 593 reg = <0x121A0000 0x1000>; 596 594 interrupts = <0 34 0>; 597 - clocks = <&clock 275>; 595 + clocks = <&clock CLK_PDMA0>; 598 596 clock-names = "apb_pclk"; 599 597 #dma-cells = <1>; 600 598 #dma-channels = <8>; ··· 605 603 compatible = "arm,pl330", "arm,primecell"; 606 604 reg = <0x121B0000 0x1000>; 607 605 interrupts = <0 35 0>; 608 - clocks = <&clock 276>; 606 + clocks = <&clock CLK_PDMA1>; 609 607 clock-names = "apb_pclk"; 610 608 #dma-cells = <1>; 611 609 #dma-channels = <8>; ··· 616 614 compatible = "arm,pl330", "arm,primecell"; 617 615 reg = <0x10800000 0x1000>; 618 616 interrupts = <0 33 0>; 619 - clocks = <&clock 346>; 617 + clocks = <&clock CLK_MDMA0>; 620 618 clock-names = "apb_pclk"; 621 619 #dma-cells = <1>; 622 620 #dma-channels = <8>; ··· 627 625 compatible = "arm,pl330", "arm,primecell"; 628 626 reg = <0x11C10000 0x1000>; 629 627 interrupts = <0 124 0>; 630 - clocks = <&clock 271>; 628 + clocks = <&clock CLK_MDMA1>; 631 629 clock-names = "apb_pclk"; 632 630 #dma-cells = <1>; 633 631 #dma-channels = <8>; ··· 640 638 reg = <0x13e00000 0x1000>; 641 639 interrupts = <0 85 0>; 642 640 samsung,power-domain = <&pd_gsc>; 643 - clocks = <&clock 256>; 641 + clocks = <&clock CLK_GSCL0>; 644 642 clock-names = "gscl"; 645 643 }; 646 644 ··· 649 647 reg = <0x13e10000 0x1000>; 650 648 interrupts = <0 86 0>; 651 649 samsung,power-domain = <&pd_gsc>; 652 - clocks = <&clock 257>; 650 + clocks = <&clock CLK_GSCL1>; 653 651 clock-names = "gscl"; 654 652 }; 655 653 ··· 658 656 reg = <0x13e20000 0x1000>; 659 657 interrupts = <0 87 0>; 660 658 samsung,power-domain = <&pd_gsc>; 661 - clocks = <&clock 258>; 659 + clocks = <&clock CLK_GSCL2>; 662 660 clock-names = "gscl"; 663 661 }; 664 662 ··· 667 665 reg = <0x13e30000 0x1000>; 668 666 interrupts = <0 88 0>; 669 667 samsung,power-domain = <&pd_gsc>; 670 - clocks = <&clock 259>; 668 + clocks = <&clock CLK_GSCL3>; 671 669 clock-names = "gscl"; 672 670 }; 673 671 ··· 675 673 compatible = "samsung,exynos4212-hdmi"; 676 674 reg = <0x14530000 0x70000>; 677 675 interrupts = <0 95 0>; 678 - clocks = <&clock 344>, <&clock 136>, <&clock 137>, 679 - <&clock 159>, <&clock 1024>; 676 + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 677 + <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 678 + <&clock CLK_MOUT_HDMI>; 680 679 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 681 680 "sclk_hdmiphy", "mout_hdmi"; 682 681 }; ··· 686 683 compatible = "samsung,exynos5250-mixer"; 687 684 reg = <0x14450000 0x10000>; 688 685 interrupts = <0 94 0>; 689 - clocks = <&clock 343>, <&clock 136>; 686 + clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; 690 687 clock-names = "mixer", "sclk_hdmi"; 691 688 }; 692 689 ··· 697 694 }; 698 695 699 696 dp-controller@145B0000 { 700 - clocks = <&clock 342>; 697 + clocks = <&clock CLK_DP>; 701 698 clock-names = "dp"; 702 699 phys = <&dp_phy>; 703 700 phy-names = "dp"; 704 701 }; 705 702 706 703 fimd@14400000 { 707 - clocks = <&clock 133>, <&clock 339>; 704 + clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 708 705 clock-names = "sclk_fimd", "fimd"; 709 706 }; 710 707 ··· 712 709 compatible = "samsung,exynos-adc-v1"; 713 710 reg = <0x12D10000 0x100>, <0x10040718 0x4>; 714 711 interrupts = <0 106 0>; 715 - clocks = <&clock 303>; 712 + clocks = <&clock CLK_ADC>; 716 713 clock-names = "adc"; 717 714 #io-channel-cells = <1>; 718 715 io-channel-ranges;