tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'ib-sophgo' into devel
Pull the immutable branch into devel for next.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+3137
-540
+129
Documentation/devicetree/bindings/pinctrl/sophgo,sg2042-pinctrl.yaml
+129
Documentation/devicetree/bindings/pinctrl/sophgo,sg2042-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/sophgo,sg2042-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Sophgo SG2042 Pin Controller
8
+
9
+
maintainers:
10
+
- Inochi Amaoto <inochiama@outlook.com>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- sophgo,sg2042-pinctrl
16
+
- sophgo,sg2044-pinctrl
17
+
18
+
reg:
19
+
maxItems: 1
20
+
21
+
patternProperties:
22
+
'-cfg$':
23
+
type: object
24
+
description:
25
+
A pinctrl node should contain at least one subnode representing the
26
+
pinctrl groups available on the machine.
27
+
28
+
additionalProperties: false
29
+
30
+
patternProperties:
31
+
'-pins$':
32
+
type: object
33
+
description: |
34
+
Each subnode will list the pins it needs, and how they should
35
+
be configured, with regard to muxer configuration, bias input
36
+
enable/disable, input schmitt trigger enable, drive strength
37
+
output enable/disable state. For configuration detail,
38
+
refer to https://github.com/sophgo/sophgo-doc/.
39
+
40
+
allOf:
41
+
- $ref: pincfg-node.yaml#
42
+
- $ref: pinmux-node.yaml#
43
+
44
+
properties:
45
+
pinmux:
46
+
description: |
47
+
The list of GPIOs and their mux settings that properties in the
48
+
node apply to. This should be set using the PINMUX macro.
49
+
50
+
bias-disable: true
51
+
52
+
bias-pull-up:
53
+
type: boolean
54
+
55
+
bias-pull-down:
56
+
type: boolean
57
+
58
+
drive-strength-microamp:
59
+
description: typical current when output low level.
60
+
61
+
input-schmitt-enable: true
62
+
63
+
input-schmitt-disable: true
64
+
65
+
required:
66
+
- pinmux
67
+
68
+
additionalProperties: false
69
+
70
+
required:
71
+
- compatible
72
+
- reg
73
+
74
+
allOf:
75
+
- if:
76
+
properties:
77
+
compatible:
78
+
contains:
79
+
const: sophgo,sg2042-pinctrl
80
+
then:
81
+
patternProperties:
82
+
'-cfg$':
83
+
patternProperties:
84
+
'-pins$':
85
+
properties:
86
+
drive-strength-microamp:
87
+
enum: [ 5400, 8100, 10700, 13400,
88
+
16100, 18800, 21400, 24100,
89
+
26800, 29400, 32100, 34800,
90
+
37400, 40100, 42800, 45400 ]
91
+
92
+
- if:
93
+
properties:
94
+
compatible:
95
+
contains:
96
+
const: sophgo,sg2044-pinctrl
97
+
then:
98
+
patternProperties:
99
+
'-cfg$':
100
+
patternProperties:
101
+
'-pins$':
102
+
properties:
103
+
drive-strength-microamp:
104
+
enum: [ 3200, 6400, 9600, 12700,
105
+
15900, 19100, 22200, 25300,
106
+
29500, 32700, 35900, 39000,
107
+
42000, 45200, 48300, 51400]
108
+
109
+
additionalProperties: false
110
+
111
+
examples:
112
+
- |
113
+
#include <dt-bindings/pinctrl/pinctrl-sg2042.h>
114
+
115
+
pinctrl@30011000 {
116
+
compatible = "sophgo,sg2042-pinctrl";
117
+
reg = <30011000 0x1000>;
118
+
119
+
uart0_cfg: uart0-cfg {
120
+
uart0-pins {
121
+
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
122
+
<PINMUX(PIN_UART0_RX, 0)>;
123
+
bias-pull-up;
124
+
drive-strength-microamp = <13400>;
125
+
};
126
+
};
127
+
};
128
+
129
+
...
+40
-6
drivers/pinctrl/sophgo/Kconfig
+40
-6
drivers/pinctrl/sophgo/Kconfig
···
3
3
# Sophgo SoC PINCTRL drivers
4
4
#
5
5
6
-
config PINCTRL_SOPHGO_CV18XX
7
-
bool
6
+
config PINCTRL_SOPHGO_COMMON
7
+
tristate
8
8
select GENERIC_PINCTRL_GROUPS
9
9
select GENERIC_PINMUX_FUNCTIONS
10
10
select GENERIC_PINCONF
11
+
12
+
config PINCTRL_SOPHGO_CV18XX_OPS
13
+
bool
11
14
12
15
config PINCTRL_SOPHGO_CV1800B
13
16
tristate "Sophgo CV1800B SoC Pinctrl driver"
14
17
depends on ARCH_SOPHGO || COMPILE_TEST
15
18
depends on OF
16
-
select PINCTRL_SOPHGO_CV18XX
19
+
select PINCTRL_SOPHGO_COMMON
20
+
select PINCTRL_SOPHGO_CV18XX_OPS
17
21
help
18
22
Say Y to select the pinctrl driver for CV1800B SoC.
19
23
This pin controller allows selecting the mux function for
···
28
24
tristate "Sophgo CV1812H SoC Pinctrl driver"
29
25
depends on ARCH_SOPHGO || COMPILE_TEST
30
26
depends on OF
31
-
select PINCTRL_SOPHGO_CV18XX
27
+
select PINCTRL_SOPHGO_COMMON
28
+
select PINCTRL_SOPHGO_CV18XX_OPS
32
29
help
33
30
Say Y to select the pinctrl driver for CV1812H SoC.
34
31
This pin controller allows selecting the mux function for
···
40
35
tristate "Sophgo SG2000 SoC Pinctrl driver"
41
36
depends on ARCH_SOPHGO || COMPILE_TEST
42
37
depends on OF
43
-
select PINCTRL_SOPHGO_CV18XX
38
+
select PINCTRL_SOPHGO_COMMON
39
+
select PINCTRL_SOPHGO_CV18XX_OPS
44
40
help
45
41
Say Y to select the pinctrl driver for SG2000 SoC.
46
42
This pin controller allows selecting the mux function for
···
52
46
tristate "Sophgo SG2002 SoC Pinctrl driver"
53
47
depends on ARCH_SOPHGO || COMPILE_TEST
54
48
depends on OF
55
-
select PINCTRL_SOPHGO_CV18XX
49
+
select PINCTRL_SOPHGO_COMMON
50
+
select PINCTRL_SOPHGO_CV18XX_OPS
56
51
help
57
52
Say Y to select the pinctrl driver for SG2002 SoC.
58
53
This pin controller allows selecting the mux function for
59
54
each pin. This driver can also be built as a module called
60
55
pinctrl-sg2002.
56
+
57
+
config PINCTRL_SOPHGO_SG2042_OPS
58
+
bool
59
+
60
+
config PINCTRL_SOPHGO_SG2042
61
+
tristate "Sophgo SG2042 SoC Pinctrl driver"
62
+
depends on ARCH_SOPHGO || COMPILE_TEST
63
+
depends on OF
64
+
select PINCTRL_SOPHGO_COMMON
65
+
select PINCTRL_SOPHGO_SG2042_OPS
66
+
help
67
+
Say Y to select the pinctrl driver for SG2042 SoC.
68
+
This pin controller allows selecting the mux function for
69
+
each pin. This driver can also be built as a module called
70
+
pinctrl-sg2042.
71
+
72
+
config PINCTRL_SOPHGO_SG2044
73
+
tristate "Sophgo SG2044 SoC Pinctrl driver"
74
+
depends on ARCH_SOPHGO || COMPILE_TEST
75
+
depends on OF
76
+
select PINCTRL_SOPHGO_COMMON
77
+
select PINCTRL_SOPHGO_SG2042_OPS
78
+
help
79
+
Say Y to select the pinctrl driver for SG2044 SoC.
80
+
This pin controller allows selecting the mux function for
81
+
each pin. This driver can also be built as a module called
82
+
pinctrl-sg2044.
+7
-1
drivers/pinctrl/sophgo/Makefile
+7
-1
drivers/pinctrl/sophgo/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
3
-
obj-$(CONFIG_PINCTRL_SOPHGO_CV18XX) += pinctrl-cv18xx.o
3
+
obj-$(CONFIG_PINCTRL_SOPHGO_COMMON) += pinctrl-sophgo.o
4
+
pinctrl-sophgo-objs += pinctrl-sophgo-common.o
5
+
pinctrl-sophgo-$(CONFIG_PINCTRL_SOPHGO_CV18XX_OPS) += pinctrl-cv18xx.o
6
+
pinctrl-sophgo-$(CONFIG_PINCTRL_SOPHGO_SG2042_OPS) += pinctrl-sg2042-ops.o
7
+
4
8
obj-$(CONFIG_PINCTRL_SOPHGO_CV1800B) += pinctrl-cv1800b.o
5
9
obj-$(CONFIG_PINCTRL_SOPHGO_CV1812H) += pinctrl-cv1812h.o
6
10
obj-$(CONFIG_PINCTRL_SOPHGO_SG2000) += pinctrl-sg2000.o
7
11
obj-$(CONFIG_PINCTRL_SOPHGO_SG2002) += pinctrl-sg2002.o
12
+
obj-$(CONFIG_PINCTRL_SOPHGO_SG2042) += pinctrl-sg2042.o
13
+
obj-$(CONFIG_PINCTRL_SOPHGO_SG2044) += pinctrl-sg2044.o
+18
-9
drivers/pinctrl/sophgo/pinctrl-cv1800b.c
+18
-9
drivers/pinctrl/sophgo/pinctrl-cv1800b.c
···
34
34
[VDDIO_SD0_SPI] = "VDDIO_SD0_SPI",
35
35
};
36
36
37
-
static int cv1800b_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
37
+
static int cv1800b_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap)
38
38
{
39
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
39
40
u32 pstate = psmap[pin->power_domain];
40
41
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
41
42
···
55
54
return -ENOTSUPP;
56
55
}
57
56
58
-
static int cv1800b_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
57
+
static int cv1800b_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap)
59
58
{
59
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
60
60
u32 pstate = psmap[pin->power_domain];
61
61
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
62
62
···
110
108
17800
111
109
};
112
110
113
-
static int cv1800b_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
111
+
static int cv1800b_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap,
114
112
const u32 **map)
115
113
{
114
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
116
115
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
117
116
u32 pstate = psmap[pin->power_domain];
118
117
···
156
153
1100000
157
154
};
158
155
159
-
static int cv1800b_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
156
+
static int cv1800b_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap,
160
157
const u32 **map)
161
158
{
159
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
162
160
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
163
161
u32 pstate = psmap[pin->power_domain];
164
162
···
181
177
return -ENOTSUPP;
182
178
}
183
179
184
-
static const struct cv1800_vddio_cfg_ops cv1800b_vddio_cfg_ops = {
180
+
static const struct sophgo_vddio_cfg_ops cv1800b_vddio_cfg_ops = {
185
181
.get_pull_up = cv1800b_get_pull_up,
186
182
.get_pull_down = cv1800b_get_pull_down,
187
183
.get_oc_map = cv1800b_get_oc_map,
188
-
.get_schmitt_map = cv1800b_get_schmitt_map,
184
+
.get_schmitt_map = cv1800b_get_schmitt_map,
189
185
};
190
186
191
187
static const struct pinctrl_pin_desc cv1800b_pins[] = {
···
437
433
CV1800_PINCONF_AREA_SYS, 0x120, 5),
438
434
};
439
435
440
-
static const struct cv1800_pinctrl_data cv1800b_pindata = {
436
+
static const struct sophgo_pinctrl_data cv1800b_pindata = {
441
437
.pins = cv1800b_pins,
442
438
.pindata = cv1800b_pin_data,
443
439
.pdnames = cv1800b_power_domain_desc,
444
440
.vddio_ops = &cv1800b_vddio_cfg_ops,
441
+
.cfg_ops = &cv1800_cfg_ops,
442
+
.pctl_ops = &cv1800_pctrl_ops,
443
+
.pmx_ops = &cv1800_pmx_ops,
444
+
.pconf_ops = &cv1800_pconf_ops,
445
445
.npins = ARRAY_SIZE(cv1800b_pins),
446
-
.npd = ARRAY_SIZE(cv1800b_power_domain_desc),
446
+
.npds = ARRAY_SIZE(cv1800b_power_domain_desc),
447
+
.pinsize = sizeof(struct cv1800_pin),
447
448
};
448
449
449
450
static const struct of_device_id cv1800b_pinctrl_ids[] = {
···
458
449
MODULE_DEVICE_TABLE(of, cv1800b_pinctrl_ids);
459
450
460
451
static struct platform_driver cv1800b_pinctrl_driver = {
461
-
.probe = cv1800_pinctrl_probe,
452
+
.probe = sophgo_pinctrl_probe,
462
453
.driver = {
463
454
.name = "cv1800b-pinctrl",
464
455
.suppress_bind_attrs = true,
+18
-9
drivers/pinctrl/sophgo/pinctrl-cv1812h.c
+18
-9
drivers/pinctrl/sophgo/pinctrl-cv1812h.c
···
40
40
[VDDIO_VIVO] = "VDDIO_VIVO",
41
41
};
42
42
43
-
static int cv1812h_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
43
+
static int cv1812h_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap)
44
44
{
45
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
45
46
u32 pstate = psmap[pin->power_domain];
46
47
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
47
48
···
61
60
return -ENOTSUPP;
62
61
}
63
62
64
-
static int cv1812h_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
63
+
static int cv1812h_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap)
65
64
{
65
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
66
66
u32 pstate = psmap[pin->power_domain];
67
67
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
68
68
···
116
114
17800
117
115
};
118
116
119
-
static int cv1812h_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
117
+
static int cv1812h_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap,
120
118
const u32 **map)
121
119
{
120
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
122
121
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
123
122
u32 pstate = psmap[pin->power_domain];
124
123
···
162
159
1100000
163
160
};
164
161
165
-
static int cv1812h_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
162
+
static int cv1812h_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap,
166
163
const u32 **map)
167
164
{
165
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
168
166
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
169
167
u32 pstate = psmap[pin->power_domain];
170
168
···
187
183
return -ENOTSUPP;
188
184
}
189
185
190
-
static const struct cv1800_vddio_cfg_ops cv1812h_vddio_cfg_ops = {
186
+
static const struct sophgo_vddio_cfg_ops cv1812h_vddio_cfg_ops = {
191
187
.get_pull_up = cv1812h_get_pull_up,
192
188
.get_pull_down = cv1812h_get_pull_down,
193
189
.get_oc_map = cv1812h_get_oc_map,
194
-
.get_schmitt_map = cv1812h_get_schmitt_map,
190
+
.get_schmitt_map = cv1812h_get_schmitt_map,
195
191
};
196
192
197
193
static const struct pinctrl_pin_desc cv1812h_pins[] = {
···
746
742
CV1800_PINCONF_AREA_RTC, 0x028),
747
743
};
748
744
749
-
static const struct cv1800_pinctrl_data cv1812h_pindata = {
745
+
static const struct sophgo_pinctrl_data cv1812h_pindata = {
750
746
.pins = cv1812h_pins,
751
747
.pindata = cv1812h_pin_data,
752
748
.pdnames = cv1812h_power_domain_desc,
753
749
.vddio_ops = &cv1812h_vddio_cfg_ops,
750
+
.cfg_ops = &cv1800_cfg_ops,
751
+
.pctl_ops = &cv1800_pctrl_ops,
752
+
.pmx_ops = &cv1800_pmx_ops,
753
+
.pconf_ops = &cv1800_pconf_ops,
754
754
.npins = ARRAY_SIZE(cv1812h_pins),
755
-
.npd = ARRAY_SIZE(cv1812h_power_domain_desc),
755
+
.npds = ARRAY_SIZE(cv1812h_power_domain_desc),
756
+
.pinsize = sizeof(struct cv1800_pin),
756
757
};
757
758
758
759
static const struct of_device_id cv1812h_pinctrl_ids[] = {
···
767
758
MODULE_DEVICE_TABLE(of, cv1812h_pinctrl_ids);
768
759
769
760
static struct platform_driver cv1812h_pinctrl_driver = {
770
-
.probe = cv1800_pinctrl_probe,
761
+
.probe = sophgo_pinctrl_probe,
771
762
.driver = {
772
763
.name = "cv1812h-pinctrl",
773
764
.suppress_bind_attrs = true,
+142
-456
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
+142
-456
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
···
15
15
#include <linux/seq_file.h>
16
16
#include <linux/spinlock.h>
17
17
18
-
#include <linux/pinctrl/consumer.h>
19
-
#include <linux/pinctrl/machine.h>
20
18
#include <linux/pinctrl/pinconf-generic.h>
21
19
#include <linux/pinctrl/pinconf.h>
22
20
#include <linux/pinctrl/pinctrl.h>
···
22
24
23
25
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
24
26
25
-
#include "../core.h"
26
27
#include "../pinctrl-utils.h"
27
-
#include "../pinconf.h"
28
28
#include "../pinmux.h"
29
29
#include "pinctrl-cv18xx.h"
30
30
31
-
struct cv1800_pinctrl {
32
-
struct device *dev;
33
-
struct pinctrl_dev *pctl_dev;
34
-
const struct cv1800_pinctrl_data *data;
35
-
struct pinctrl_desc pdesc;
31
+
struct cv1800_priv {
36
32
u32 *power_cfg;
37
-
38
-
struct mutex mutex;
39
-
raw_spinlock_t lock;
40
-
41
33
void __iomem *regs[2];
42
34
};
43
-
44
-
struct cv1800_pin_mux_config {
45
-
struct cv1800_pin *pin;
46
-
u32 config;
47
-
};
48
-
49
-
static unsigned int cv1800_dt_get_pin(u32 value)
50
-
{
51
-
return value & GENMASK(15, 0);
52
-
}
53
35
54
36
static unsigned int cv1800_dt_get_pin_mux(u32 value)
55
37
{
···
44
66
#define cv1800_pinctrl_get_component_addr(pctrl, _comp) \
45
67
((pctrl)->regs[(_comp)->area] + (_comp)->offset)
46
68
47
-
static int cv1800_cmp_pin(const void *key, const void *pivot)
48
-
{
49
-
const struct cv1800_pin *pin = pivot;
50
-
int pin_id = (long)key;
51
-
int pivid = pin->pin;
52
-
53
-
return pin_id - pivid;
54
-
}
55
-
56
-
static int cv1800_set_power_cfg(struct cv1800_pinctrl *pctrl,
69
+
static int cv1800_set_power_cfg(struct sophgo_pinctrl *pctrl,
57
70
u8 domain, u32 cfg)
58
71
{
59
-
if (domain >= pctrl->data->npd)
72
+
struct cv1800_priv *priv = pctrl->priv_ctrl;
73
+
74
+
if (domain >= pctrl->data->npds)
60
75
return -ENOTSUPP;
61
76
62
-
if (pctrl->power_cfg[domain] && pctrl->power_cfg[domain] != cfg)
77
+
if (priv->power_cfg[domain] && priv->power_cfg[domain] != cfg)
63
78
return -EINVAL;
64
79
65
-
pctrl->power_cfg[domain] = cfg;
80
+
priv->power_cfg[domain] = cfg;
66
81
67
82
return 0;
68
83
}
69
84
70
-
static int cv1800_get_power_cfg(struct cv1800_pinctrl *pctrl,
85
+
static int cv1800_get_power_cfg(struct sophgo_pinctrl *pctrl,
71
86
u8 domain)
72
87
{
73
-
return pctrl->power_cfg[domain];
74
-
}
88
+
struct cv1800_priv *priv = pctrl->priv_ctrl;
75
89
76
-
static struct cv1800_pin *cv1800_get_pin(struct cv1800_pinctrl *pctrl,
77
-
unsigned long pin)
78
-
{
79
-
return bsearch((void *)pin, pctrl->data->pindata, pctrl->data->npins,
80
-
sizeof(struct cv1800_pin), cv1800_cmp_pin);
90
+
return priv->power_cfg[domain];
81
91
}
82
92
83
93
#define PIN_BGA_ID_OFFSET 8
···
78
112
"ETH"
79
113
};
80
114
81
-
static const char *cv1800_get_power_cfg_desc(struct cv1800_pinctrl *pctrl,
115
+
static const char *cv1800_get_power_cfg_desc(struct sophgo_pinctrl *pctrl,
82
116
u8 domain)
83
117
{
84
118
return pctrl->data->pdnames[domain];
···
87
121
static void cv1800_pctrl_dbg_show(struct pinctrl_dev *pctldev,
88
122
struct seq_file *seq, unsigned int pin_id)
89
123
{
90
-
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
91
-
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
124
+
struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
125
+
struct cv1800_priv *priv = pctrl->priv_ctrl;
126
+
const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id);
127
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
92
128
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
129
+
u32 pin_hwid = pin->pin.id;
93
130
u32 value;
94
131
void __iomem *reg;
95
132
96
-
if (pin->pin >> PIN_BGA_ID_OFFSET)
133
+
if (pin_hwid >> PIN_BGA_ID_OFFSET)
97
134
seq_printf(seq, "pos: %c%u ",
98
-
'A' + (pin->pin >> PIN_BGA_ID_OFFSET) - 1,
99
-
pin->pin & PIN_BGA_ID_MASK);
135
+
'A' + (pin_hwid >> PIN_BGA_ID_OFFSET) - 1,
136
+
pin_hwid & PIN_BGA_ID_MASK);
100
137
else
101
-
seq_printf(seq, "pos: %u ", pin->pin);
138
+
seq_printf(seq, "pos: %u ", pin_hwid);
102
139
103
140
seq_printf(seq, "power-domain: %s ",
104
141
cv1800_get_power_cfg_desc(pctrl, pin->power_domain));
105
142
seq_printf(seq, "type: %s ", io_type_desc[type]);
106
143
107
-
reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux);
144
+
reg = cv1800_pinctrl_get_component_addr(priv, &pin->mux);
108
145
value = readl(reg);
109
146
seq_printf(seq, "mux: 0x%08x ", value);
110
147
111
-
if (pin->flags & CV1800_PIN_HAVE_MUX2) {
112
-
reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux2);
148
+
if (pin->pin.flags & CV1800_PIN_HAVE_MUX2) {
149
+
reg = cv1800_pinctrl_get_component_addr(priv, &pin->mux2);
113
150
value = readl(reg);
114
151
seq_printf(seq, "mux2: 0x%08x ", value);
115
152
}
116
153
117
154
if (type == IO_TYPE_1V8_ONLY || type == IO_TYPE_1V8_OR_3V3) {
118
-
reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->conf);
155
+
reg = cv1800_pinctrl_get_component_addr(priv, &pin->conf);
119
156
value = readl(reg);
120
157
seq_printf(seq, "conf: 0x%08x ", value);
121
158
}
122
159
}
123
160
124
-
static int cv1800_verify_pinmux_config(const struct cv1800_pin_mux_config *config)
161
+
static int cv1800_verify_pinmux_config(const struct sophgo_pin_mux_config *config)
125
162
{
163
+
struct cv1800_pin *pin = sophgo_to_cv1800_pin(config->pin);
126
164
unsigned int mux = cv1800_dt_get_pin_mux(config->config);
127
165
unsigned int mux2 = cv1800_dt_get_pin_mux2(config->config);
128
166
129
-
if (mux > config->pin->mux.max)
167
+
if (mux > pin->mux.max)
130
168
return -EINVAL;
131
169
132
-
if (config->pin->flags & CV1800_PIN_HAVE_MUX2) {
133
-
if (mux != config->pin->mux2.pfunc)
170
+
if (pin->pin.flags & CV1800_PIN_HAVE_MUX2) {
171
+
if (mux != pin->mux2.pfunc)
134
172
return -EINVAL;
135
173
136
-
if (mux2 > config->pin->mux2.max)
174
+
if (mux2 > pin->mux2.max)
137
175
return -EINVAL;
138
176
} else {
139
177
if (mux2 != PIN_MUX_INVALD)
···
147
177
return 0;
148
178
}
149
179
150
-
static int cv1800_verify_pin_group(const struct cv1800_pin_mux_config *mux,
151
-
unsigned long npins)
180
+
static int cv1800_verify_pin_group(const struct sophgo_pin_mux_config *mux,
181
+
unsigned int npins)
152
182
{
183
+
struct cv1800_pin *pin;
153
184
enum cv1800_pin_io_type type;
154
185
u8 power_domain;
155
186
int i;
···
158
187
if (npins == 1)
159
188
return 0;
160
189
161
-
type = cv1800_pin_io_type(mux[0].pin);
162
-
power_domain = mux[0].pin->power_domain;
190
+
pin = sophgo_to_cv1800_pin(mux[0].pin);
191
+
type = cv1800_pin_io_type(pin);
192
+
power_domain = pin->power_domain;
163
193
164
194
for (i = 0; i < npins; i++) {
165
-
if (type != cv1800_pin_io_type(mux[i].pin) ||
166
-
power_domain != mux[i].pin->power_domain)
195
+
pin = sophgo_to_cv1800_pin(mux[i].pin);
196
+
197
+
if (type != cv1800_pin_io_type(pin) ||
198
+
power_domain != pin->power_domain)
167
199
return -ENOTSUPP;
168
200
}
169
201
170
202
return 0;
171
203
}
172
204
173
-
static int cv1800_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
174
-
struct device_node *np,
175
-
struct pinctrl_map **maps,
176
-
unsigned int *num_maps)
205
+
static int cv1800_dt_node_to_map_post(struct device_node *cur,
206
+
struct sophgo_pinctrl *pctrl,
207
+
struct sophgo_pin_mux_config *pinmuxs,
208
+
unsigned int npins)
177
209
{
178
-
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
179
-
struct device *dev = pctrl->dev;
180
-
struct device_node *child;
181
-
struct pinctrl_map *map;
182
-
const char **grpnames;
183
-
const char *grpname;
184
-
int ngroups = 0;
185
-
int nmaps = 0;
210
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(pinmuxs[0].pin);
211
+
u32 power;
186
212
int ret;
187
213
188
-
for_each_available_child_of_node(np, child)
189
-
ngroups += 1;
214
+
ret = of_property_read_u32(cur, "power-source", &power);
215
+
if (ret)
216
+
return ret;
190
217
191
-
grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL);
192
-
if (!grpnames)
193
-
return -ENOMEM;
218
+
if (!(power == PIN_POWER_STATE_3V3 || power == PIN_POWER_STATE_1V8))
219
+
return -ENOTSUPP;
194
220
195
-
map = kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL);
196
-
if (!map)
197
-
return -ENOMEM;
198
-
199
-
ngroups = 0;
200
-
mutex_lock(&pctrl->mutex);
201
-
for_each_available_child_of_node(np, child) {
202
-
int npins = of_property_count_u32_elems(child, "pinmux");
203
-
unsigned int *pins;
204
-
struct cv1800_pin_mux_config *pinmuxs;
205
-
u32 config, power;
206
-
int i;
207
-
208
-
if (npins < 1) {
209
-
dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n",
210
-
np, child);
211
-
ret = -EINVAL;
212
-
goto dt_failed;
213
-
}
214
-
215
-
grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn",
216
-
np, child);
217
-
if (!grpname) {
218
-
ret = -ENOMEM;
219
-
goto dt_failed;
220
-
}
221
-
222
-
grpnames[ngroups++] = grpname;
223
-
224
-
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
225
-
if (!pins) {
226
-
ret = -ENOMEM;
227
-
goto dt_failed;
228
-
}
229
-
230
-
pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL);
231
-
if (!pinmuxs) {
232
-
ret = -ENOMEM;
233
-
goto dt_failed;
234
-
}
235
-
236
-
for (i = 0; i < npins; i++) {
237
-
ret = of_property_read_u32_index(child, "pinmux",
238
-
i, &config);
239
-
if (ret)
240
-
goto dt_failed;
241
-
242
-
pins[i] = cv1800_dt_get_pin(config);
243
-
pinmuxs[i].config = config;
244
-
pinmuxs[i].pin = cv1800_get_pin(pctrl, pins[i]);
245
-
246
-
if (!pinmuxs[i].pin) {
247
-
dev_err(dev, "failed to get pin %d\n", pins[i]);
248
-
ret = -ENODEV;
249
-
goto dt_failed;
250
-
}
251
-
252
-
ret = cv1800_verify_pinmux_config(&pinmuxs[i]);
253
-
if (ret) {
254
-
dev_err(dev, "group %s pin %d is invalid\n",
255
-
grpname, i);
256
-
goto dt_failed;
257
-
}
258
-
}
259
-
260
-
ret = cv1800_verify_pin_group(pinmuxs, npins);
261
-
if (ret) {
262
-
dev_err(dev, "group %s is invalid\n", grpname);
263
-
goto dt_failed;
264
-
}
265
-
266
-
ret = of_property_read_u32(child, "power-source", &power);
267
-
if (ret)
268
-
goto dt_failed;
269
-
270
-
if (!(power == PIN_POWER_STATE_3V3 || power == PIN_POWER_STATE_1V8)) {
271
-
dev_err(dev, "group %s have unsupported power: %u\n",
272
-
grpname, power);
273
-
ret = -ENOTSUPP;
274
-
goto dt_failed;
275
-
}
276
-
277
-
ret = cv1800_set_power_cfg(pctrl, pinmuxs[0].pin->power_domain,
278
-
power);
279
-
if (ret)
280
-
goto dt_failed;
281
-
282
-
map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
283
-
map[nmaps].data.mux.function = np->name;
284
-
map[nmaps].data.mux.group = grpname;
285
-
nmaps += 1;
286
-
287
-
ret = pinconf_generic_parse_dt_config(child, pctldev,
288
-
&map[nmaps].data.configs.configs,
289
-
&map[nmaps].data.configs.num_configs);
290
-
if (ret) {
291
-
dev_err(dev, "failed to parse pin config of group %s: %d\n",
292
-
grpname, ret);
293
-
goto dt_failed;
294
-
}
295
-
296
-
ret = pinctrl_generic_add_group(pctldev, grpname,
297
-
pins, npins, pinmuxs);
298
-
if (ret < 0) {
299
-
dev_err(dev, "failed to add group %s: %d\n", grpname, ret);
300
-
goto dt_failed;
301
-
}
302
-
303
-
/* don't create a map if there are no pinconf settings */
304
-
if (map[nmaps].data.configs.num_configs == 0)
305
-
continue;
306
-
307
-
map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
308
-
map[nmaps].data.configs.group_or_pin = grpname;
309
-
nmaps += 1;
310
-
}
311
-
312
-
ret = pinmux_generic_add_function(pctldev, np->name,
313
-
grpnames, ngroups, NULL);
314
-
if (ret < 0) {
315
-
dev_err(dev, "error adding function %s: %d\n", np->name, ret);
316
-
goto function_failed;
317
-
}
318
-
319
-
*maps = map;
320
-
*num_maps = nmaps;
321
-
mutex_unlock(&pctrl->mutex);
322
-
323
-
return 0;
324
-
325
-
dt_failed:
326
-
of_node_put(child);
327
-
function_failed:
328
-
pinctrl_utils_free_map(pctldev, map, nmaps);
329
-
mutex_unlock(&pctrl->mutex);
330
-
return ret;
221
+
return cv1800_set_power_cfg(pctrl, pin->power_domain, power);
331
222
}
332
223
333
-
static const struct pinctrl_ops cv1800_pctrl_ops = {
224
+
const struct pinctrl_ops cv1800_pctrl_ops = {
334
225
.get_groups_count = pinctrl_generic_get_group_count,
335
226
.get_group_name = pinctrl_generic_get_group_name,
336
227
.get_group_pins = pinctrl_generic_get_group_pins,
337
228
.pin_dbg_show = cv1800_pctrl_dbg_show,
338
-
.dt_node_to_map = cv1800_pctrl_dt_node_to_map,
229
+
.dt_node_to_map = sophgo_pctrl_dt_node_to_map,
339
230
.dt_free_map = pinctrl_utils_free_map,
340
231
};
232
+
EXPORT_SYMBOL_GPL(cv1800_pctrl_ops);
341
233
342
-
static int cv1800_pmx_set_mux(struct pinctrl_dev *pctldev,
343
-
unsigned int fsel, unsigned int gsel)
234
+
static void cv1800_set_pinmux_config(struct sophgo_pinctrl *pctrl,
235
+
const struct sophgo_pin *sp, u32 config)
344
236
{
345
-
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
346
-
const struct group_desc *group;
347
-
const struct cv1800_pin_mux_config *configs;
348
-
unsigned int i;
237
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
238
+
struct cv1800_priv *priv = pctrl->priv_ctrl;
239
+
void __iomem *reg_mux;
240
+
void __iomem *reg_mux2;
241
+
u32 mux;
242
+
u32 mux2;
349
243
350
-
group = pinctrl_generic_get_group(pctldev, gsel);
351
-
if (!group)
352
-
return -EINVAL;
244
+
reg_mux = cv1800_pinctrl_get_component_addr(priv, &pin->mux);
245
+
reg_mux2 = cv1800_pinctrl_get_component_addr(priv, &pin->mux2);
246
+
mux = cv1800_dt_get_pin_mux(config);
247
+
mux2 = cv1800_dt_get_pin_mux2(config);
353
248
354
-
configs = group->data;
355
-
356
-
for (i = 0; i < group->grp.npins; i++) {
357
-
const struct cv1800_pin *pin = configs[i].pin;
358
-
u32 value = configs[i].config;
359
-
void __iomem *reg_mux;
360
-
void __iomem *reg_mux2;
361
-
unsigned long flags;
362
-
u32 mux;
363
-
u32 mux2;
364
-
365
-
reg_mux = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux);
366
-
reg_mux2 = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux2);
367
-
mux = cv1800_dt_get_pin_mux(value);
368
-
mux2 = cv1800_dt_get_pin_mux2(value);
369
-
370
-
raw_spin_lock_irqsave(&pctrl->lock, flags);
371
-
writel_relaxed(mux, reg_mux);
372
-
if (mux2 != PIN_MUX_INVALD)
373
-
writel_relaxed(mux2, reg_mux2);
374
-
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
375
-
}
376
-
377
-
return 0;
249
+
writel_relaxed(mux, reg_mux);
250
+
if (mux2 != PIN_MUX_INVALD)
251
+
writel_relaxed(mux2, reg_mux2);
378
252
}
379
253
380
-
static const struct pinmux_ops cv1800_pmx_ops = {
254
+
const struct pinmux_ops cv1800_pmx_ops = {
381
255
.get_functions_count = pinmux_generic_get_function_count,
382
256
.get_function_name = pinmux_generic_get_function_name,
383
257
.get_function_groups = pinmux_generic_get_function_groups,
384
-
.set_mux = cv1800_pmx_set_mux,
258
+
.set_mux = sophgo_pmx_set_mux,
385
259
.strict = true,
386
260
};
261
+
EXPORT_SYMBOL_GPL(cv1800_pmx_ops);
387
262
388
263
#define PIN_IO_PULLUP BIT(2)
389
264
#define PIN_IO_PULLDOWN BIT(3)
···
238
421
#define PIN_IO_BUS_HOLD BIT(10)
239
422
#define PIN_IO_OUT_FAST_SLEW BIT(11)
240
423
241
-
static u32 cv1800_pull_down_typical_resistor(struct cv1800_pinctrl *pctrl,
242
-
struct cv1800_pin *pin)
243
-
{
244
-
return pctrl->data->vddio_ops->get_pull_down(pin, pctrl->power_cfg);
245
-
}
246
-
247
-
static u32 cv1800_pull_up_typical_resistor(struct cv1800_pinctrl *pctrl,
248
-
struct cv1800_pin *pin)
249
-
{
250
-
return pctrl->data->vddio_ops->get_pull_up(pin, pctrl->power_cfg);
251
-
}
252
-
253
-
static int cv1800_pinctrl_oc2reg(struct cv1800_pinctrl *pctrl,
254
-
struct cv1800_pin *pin, u32 target)
255
-
{
256
-
const u32 *map;
257
-
int i, len;
258
-
259
-
len = pctrl->data->vddio_ops->get_oc_map(pin, pctrl->power_cfg, &map);
260
-
if (len < 0)
261
-
return len;
262
-
263
-
for (i = 0; i < len; i++) {
264
-
if (map[i] >= target)
265
-
return i;
266
-
}
267
-
268
-
return -EINVAL;
269
-
}
270
-
271
-
static int cv1800_pinctrl_reg2oc(struct cv1800_pinctrl *pctrl,
272
-
struct cv1800_pin *pin, u32 reg)
273
-
{
274
-
const u32 *map;
275
-
int len;
276
-
277
-
len = pctrl->data->vddio_ops->get_oc_map(pin, pctrl->power_cfg, &map);
278
-
if (len < 0)
279
-
return len;
280
-
281
-
if (reg >= len)
282
-
return -EINVAL;
283
-
284
-
return map[reg];
285
-
}
286
-
287
-
static int cv1800_pinctrl_schmitt2reg(struct cv1800_pinctrl *pctrl,
288
-
struct cv1800_pin *pin, u32 target)
289
-
{
290
-
const u32 *map;
291
-
int i, len;
292
-
293
-
len = pctrl->data->vddio_ops->get_schmitt_map(pin, pctrl->power_cfg,
294
-
&map);
295
-
if (len < 0)
296
-
return len;
297
-
298
-
for (i = 0; i < len; i++) {
299
-
if (map[i] == target)
300
-
return i;
301
-
}
302
-
303
-
return -EINVAL;
304
-
}
305
-
306
-
static int cv1800_pinctrl_reg2schmitt(struct cv1800_pinctrl *pctrl,
307
-
struct cv1800_pin *pin, u32 reg)
308
-
{
309
-
const u32 *map;
310
-
int len;
311
-
312
-
len = pctrl->data->vddio_ops->get_schmitt_map(pin, pctrl->power_cfg,
313
-
&map);
314
-
if (len < 0)
315
-
return len;
316
-
317
-
if (reg >= len)
318
-
return -EINVAL;
319
-
320
-
return map[reg];
321
-
}
322
-
323
424
static int cv1800_pconf_get(struct pinctrl_dev *pctldev,
324
425
unsigned int pin_id, unsigned long *config)
325
426
{
326
-
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
427
+
struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
428
+
struct cv1800_priv *priv = pctrl->priv_ctrl;
327
429
int param = pinconf_to_config_param(*config);
328
-
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
430
+
const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id);
431
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
329
432
enum cv1800_pin_io_type type;
330
433
u32 value;
331
434
u32 arg;
···
259
522
if (type == IO_TYPE_ETH || type == IO_TYPE_AUDIO)
260
523
return -ENOTSUPP;
261
524
262
-
value = readl(cv1800_pinctrl_get_component_addr(pctrl, &pin->conf));
525
+
value = readl(cv1800_pinctrl_get_component_addr(priv, &pin->conf));
263
526
264
527
switch (param) {
265
528
case PIN_CONFIG_BIAS_PULL_DOWN:
266
529
enabled = FIELD_GET(PIN_IO_PULLDOWN, value);
267
-
arg = cv1800_pull_down_typical_resistor(pctrl, pin);
530
+
arg = sophgo_pinctrl_typical_pull_down(pctrl, sp, priv->power_cfg);
268
531
break;
269
532
case PIN_CONFIG_BIAS_PULL_UP:
270
533
enabled = FIELD_GET(PIN_IO_PULLUP, value);
271
-
arg = cv1800_pull_up_typical_resistor(pctrl, pin);
534
+
arg = sophgo_pinctrl_typical_pull_up(pctrl, sp, priv->power_cfg);
272
535
break;
273
536
case PIN_CONFIG_DRIVE_STRENGTH_UA:
274
537
enabled = true;
275
538
arg = FIELD_GET(PIN_IO_DRIVE, value);
276
-
ret = cv1800_pinctrl_reg2oc(pctrl, pin, arg);
539
+
ret = sophgo_pinctrl_reg2oc(pctrl, sp, priv->power_cfg, arg);
277
540
if (ret < 0)
278
541
return ret;
279
542
arg = ret;
280
543
break;
281
544
case PIN_CONFIG_INPUT_SCHMITT_UV:
282
545
arg = FIELD_GET(PIN_IO_SCHMITT, value);
283
-
ret = cv1800_pinctrl_reg2schmitt(pctrl, pin, arg);
546
+
ret = sophgo_pinctrl_reg2schmitt(pctrl, sp, priv->power_cfg, arg);
284
547
if (ret < 0)
285
548
return ret;
286
549
arg = ret;
···
307
570
return enabled ? 0 : -EINVAL;
308
571
}
309
572
310
-
static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl,
311
-
struct cv1800_pin *pin,
573
+
static int cv1800_pinconf_compute_config(struct sophgo_pinctrl *pctrl,
574
+
const struct sophgo_pin *sp,
312
575
unsigned long *configs,
313
576
unsigned int num_configs,
314
-
u32 *value)
577
+
u32 *value, u32 *mask)
315
578
{
579
+
struct cv1800_priv *priv = pctrl->priv_ctrl;
580
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
316
581
int i;
317
-
u32 v = 0;
582
+
u32 v = 0, m = 0;
318
583
enum cv1800_pin_io_type type;
319
584
int ret;
320
585
···
335
596
case PIN_CONFIG_BIAS_PULL_DOWN:
336
597
v &= ~PIN_IO_PULLDOWN;
337
598
v |= FIELD_PREP(PIN_IO_PULLDOWN, arg);
599
+
m |= PIN_IO_PULLDOWN;
338
600
break;
339
601
case PIN_CONFIG_BIAS_PULL_UP:
340
602
v &= ~PIN_IO_PULLUP;
341
603
v |= FIELD_PREP(PIN_IO_PULLUP, arg);
604
+
m |= PIN_IO_PULLUP;
342
605
break;
343
606
case PIN_CONFIG_DRIVE_STRENGTH_UA:
344
-
ret = cv1800_pinctrl_oc2reg(pctrl, pin, arg);
607
+
ret = sophgo_pinctrl_oc2reg(pctrl, sp,
608
+
priv->power_cfg, arg);
345
609
if (ret < 0)
346
610
return ret;
347
611
v &= ~PIN_IO_DRIVE;
348
612
v |= FIELD_PREP(PIN_IO_DRIVE, ret);
613
+
m |= PIN_IO_DRIVE;
349
614
break;
350
615
case PIN_CONFIG_INPUT_SCHMITT_UV:
351
-
ret = cv1800_pinctrl_schmitt2reg(pctrl, pin, arg);
616
+
ret = sophgo_pinctrl_schmitt2reg(pctrl, sp,
617
+
priv->power_cfg, arg);
352
618
if (ret < 0)
353
619
return ret;
354
620
v &= ~PIN_IO_SCHMITT;
355
621
v |= FIELD_PREP(PIN_IO_SCHMITT, ret);
622
+
m |= PIN_IO_SCHMITT;
356
623
break;
357
624
case PIN_CONFIG_POWER_SOURCE:
358
625
/* Ignore power source as it is always fixed */
···
366
621
case PIN_CONFIG_SLEW_RATE:
367
622
v &= ~PIN_IO_OUT_FAST_SLEW;
368
623
v |= FIELD_PREP(PIN_IO_OUT_FAST_SLEW, arg);
624
+
m |= PIN_IO_OUT_FAST_SLEW;
369
625
break;
370
626
case PIN_CONFIG_BIAS_BUS_HOLD:
371
627
v &= ~PIN_IO_BUS_HOLD;
372
628
v |= FIELD_PREP(PIN_IO_BUS_HOLD, arg);
629
+
m |= PIN_IO_BUS_HOLD;
373
630
break;
374
631
default:
375
632
return -ENOTSUPP;
···
379
632
}
380
633
381
634
*value = v;
635
+
*mask = m;
382
636
383
637
return 0;
384
638
}
385
639
386
-
static int cv1800_pin_set_config(struct cv1800_pinctrl *pctrl,
387
-
unsigned int pin_id,
388
-
u32 value)
640
+
static int cv1800_set_pinconf_config(struct sophgo_pinctrl *pctrl,
641
+
const struct sophgo_pin *sp,
642
+
u32 value, u32 mask)
389
643
{
390
-
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
391
-
unsigned long flags;
644
+
struct cv1800_priv *priv = pctrl->priv_ctrl;
645
+
struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
392
646
void __iomem *addr;
647
+
u32 reg;
393
648
394
-
if (!pin)
395
-
return -EINVAL;
649
+
addr = cv1800_pinctrl_get_component_addr(priv, &pin->conf);
396
650
397
-
addr = cv1800_pinctrl_get_component_addr(pctrl, &pin->conf);
398
-
399
-
raw_spin_lock_irqsave(&pctrl->lock, flags);
400
-
writel(value, addr);
401
-
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
402
-
403
-
return 0;
404
-
}
405
-
406
-
static int cv1800_pconf_set(struct pinctrl_dev *pctldev,
407
-
unsigned int pin_id, unsigned long *configs,
408
-
unsigned int num_configs)
409
-
{
410
-
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
411
-
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
412
-
u32 value;
413
-
414
-
if (!pin)
415
-
return -ENODEV;
416
-
417
-
if (cv1800_pinconf_compute_config(pctrl, pin,
418
-
configs, num_configs, &value))
419
-
return -ENOTSUPP;
420
-
421
-
return cv1800_pin_set_config(pctrl, pin_id, value);
422
-
}
423
-
424
-
static int cv1800_pconf_group_set(struct pinctrl_dev *pctldev,
425
-
unsigned int gsel,
426
-
unsigned long *configs,
427
-
unsigned int num_configs)
428
-
{
429
-
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
430
-
const struct group_desc *group;
431
-
const struct cv1800_pin_mux_config *pinmuxs;
432
-
u32 value;
433
-
int i;
434
-
435
-
group = pinctrl_generic_get_group(pctldev, gsel);
436
-
if (!group)
437
-
return -EINVAL;
438
-
439
-
pinmuxs = group->data;
440
-
441
-
if (cv1800_pinconf_compute_config(pctrl, pinmuxs[0].pin,
442
-
configs, num_configs, &value))
443
-
return -ENOTSUPP;
444
-
445
-
for (i = 0; i < group->grp.npins; i++)
446
-
cv1800_pin_set_config(pctrl, group->grp.pins[i], value);
651
+
reg = readl(addr);
652
+
reg &= ~mask;
653
+
reg |= value;
654
+
writel(reg, addr);
447
655
448
656
return 0;
449
657
}
450
658
451
-
static const struct pinconf_ops cv1800_pconf_ops = {
659
+
const struct pinconf_ops cv1800_pconf_ops = {
452
660
.pin_config_get = cv1800_pconf_get,
453
-
.pin_config_set = cv1800_pconf_set,
454
-
.pin_config_group_set = cv1800_pconf_group_set,
661
+
.pin_config_set = sophgo_pconf_set,
662
+
.pin_config_group_set = sophgo_pconf_group_set,
455
663
.is_generic = true,
456
664
};
665
+
EXPORT_SYMBOL_GPL(cv1800_pconf_ops);
457
666
458
-
int cv1800_pinctrl_probe(struct platform_device *pdev)
667
+
static int cv1800_pinctrl_init(struct platform_device *pdev,
668
+
struct sophgo_pinctrl *pctrl)
459
669
{
460
-
struct device *dev = &pdev->dev;
461
-
struct cv1800_pinctrl *pctrl;
462
-
const struct cv1800_pinctrl_data *pctrl_data;
463
-
int ret;
670
+
const struct sophgo_pinctrl_data *pctrl_data = pctrl->data;
671
+
struct cv1800_priv *priv;
464
672
465
-
pctrl_data = device_get_match_data(dev);
466
-
if (!pctrl_data)
467
-
return -ENODEV;
468
-
469
-
if (pctrl_data->npins == 0 || pctrl_data->npd == 0)
470
-
return dev_err_probe(dev, -EINVAL, "invalid pin data\n");
471
-
472
-
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
473
-
if (!pctrl)
673
+
priv = devm_kzalloc(&pdev->dev, sizeof(struct cv1800_priv), GFP_KERNEL);
674
+
if (!priv)
474
675
return -ENOMEM;
475
676
476
-
pctrl->power_cfg = devm_kcalloc(dev, pctrl_data->npd,
477
-
sizeof(u32), GFP_KERNEL);
478
-
if (!pctrl->power_cfg)
677
+
priv->power_cfg = devm_kcalloc(&pdev->dev, pctrl_data->npds,
678
+
sizeof(u32), GFP_KERNEL);
679
+
if (!priv->power_cfg)
479
680
return -ENOMEM;
480
681
481
-
pctrl->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys");
482
-
if (IS_ERR(pctrl->regs[0]))
483
-
return PTR_ERR(pctrl->regs[0]);
682
+
priv->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys");
683
+
if (IS_ERR(priv->regs[0]))
684
+
return PTR_ERR(priv->regs[0]);
484
685
485
-
pctrl->regs[1] = devm_platform_ioremap_resource_byname(pdev, "rtc");
486
-
if (IS_ERR(pctrl->regs[1]))
487
-
return PTR_ERR(pctrl->regs[1]);
686
+
priv->regs[1] = devm_platform_ioremap_resource_byname(pdev, "rtc");
687
+
if (IS_ERR(priv->regs[1]))
688
+
return PTR_ERR(priv->regs[1]);
488
689
489
-
pctrl->pdesc.name = dev_name(dev);
490
-
pctrl->pdesc.pins = pctrl_data->pins;
491
-
pctrl->pdesc.npins = pctrl_data->npins;
492
-
pctrl->pdesc.pctlops = &cv1800_pctrl_ops;
493
-
pctrl->pdesc.pmxops = &cv1800_pmx_ops;
494
-
pctrl->pdesc.confops = &cv1800_pconf_ops;
495
-
pctrl->pdesc.owner = THIS_MODULE;
690
+
pctrl->priv_ctrl = priv;
496
691
497
-
pctrl->data = pctrl_data;
498
-
pctrl->dev = dev;
499
-
raw_spin_lock_init(&pctrl->lock);
500
-
mutex_init(&pctrl->mutex);
501
-
502
-
platform_set_drvdata(pdev, pctrl);
503
-
504
-
ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc,
505
-
pctrl, &pctrl->pctl_dev);
506
-
if (ret)
507
-
return dev_err_probe(dev, ret,
508
-
"fail to register pinctrl driver\n");
509
-
510
-
return pinctrl_enable(pctrl->pctl_dev);
692
+
return 0;
511
693
}
512
-
EXPORT_SYMBOL_GPL(cv1800_pinctrl_probe);
694
+
695
+
const struct sophgo_cfg_ops cv1800_cfg_ops = {
696
+
.pctrl_init = cv1800_pinctrl_init,
697
+
.verify_pinmux_config = cv1800_verify_pinmux_config,
698
+
.verify_pin_group = cv1800_verify_pin_group,
699
+
.dt_node_to_map_post = cv1800_dt_node_to_map_post,
700
+
.compute_pinconf_config = cv1800_pinconf_compute_config,
701
+
.set_pinconf_config = cv1800_set_pinconf_config,
702
+
.set_pinmux_config = cv1800_set_pinmux_config,
703
+
};
704
+
EXPORT_SYMBOL_GPL(cv1800_cfg_ops);
+25
-41
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
+25
-41
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
···
8
8
9
9
#include <linux/bits.h>
10
10
#include <linux/bitfield.h>
11
-
#include <linux/device.h>
12
11
#include <linux/mutex.h>
13
12
#include <linux/spinlock.h>
14
13
#include <linux/platform_device.h>
15
14
#include <linux/pinctrl/pinctrl.h>
16
15
#include <linux/pinctrl/pinconf.h>
16
+
17
+
#include "pinctrl-sophgo.h"
17
18
18
19
enum cv1800_pin_io_type {
19
20
IO_TYPE_1V8_ONLY = 0,
···
50
49
#define CV1800_PIN_FLAG_IO_TYPE(type) \
51
50
FIELD_PREP_CONST(CV1800_PIN_IO_TYPE, type)
52
51
struct cv1800_pin {
53
-
u16 pin;
54
-
u16 flags;
52
+
struct sophgo_pin pin;
55
53
u8 power_domain;
56
54
struct cv1800_pinmux mux;
57
55
struct cv1800_pinmux2 mux2;
58
56
struct cv1800_pinconf conf;
59
57
};
60
58
59
+
#define sophgo_to_cv1800_pin(_pin) \
60
+
container_of((_pin), struct cv1800_pin, pin)
61
+
61
62
#define PIN_POWER_STATE_1V8 1800
62
63
#define PIN_POWER_STATE_3V3 3300
63
64
64
-
/**
65
-
* struct cv1800_vddio_cfg_ops - pin vddio operations
66
-
*
67
-
* @get_pull_up: get resistor for pull up;
68
-
* @get_pull_down: get resistor for pull down.
69
-
* @get_oc_map: get mapping for typical low level output current value to
70
-
* register value map.
71
-
* @get_schmitt_map: get mapping for register value to typical schmitt
72
-
* threshold.
73
-
*/
74
-
struct cv1800_vddio_cfg_ops {
75
-
int (*get_pull_up)(struct cv1800_pin *pin, const u32 *psmap);
76
-
int (*get_pull_down)(struct cv1800_pin *pin, const u32 *psmap);
77
-
int (*get_oc_map)(struct cv1800_pin *pin, const u32 *psmap,
78
-
const u32 **map);
79
-
int (*get_schmitt_map)(struct cv1800_pin *pin, const u32 *psmap,
80
-
const u32 **map);
81
-
};
82
-
83
-
struct cv1800_pinctrl_data {
84
-
const struct pinctrl_pin_desc *pins;
85
-
const struct cv1800_pin *pindata;
86
-
const char * const *pdnames;
87
-
const struct cv1800_vddio_cfg_ops *vddio_ops;
88
-
u16 npins;
89
-
u16 npd;
90
-
};
91
-
92
-
static inline enum cv1800_pin_io_type cv1800_pin_io_type(struct cv1800_pin *pin)
65
+
static inline enum cv1800_pin_io_type cv1800_pin_io_type(const struct cv1800_pin *pin)
93
66
{
94
-
return FIELD_GET(CV1800_PIN_IO_TYPE, pin->flags);
67
+
return FIELD_GET(CV1800_PIN_IO_TYPE, pin->pin.flags);
95
68
};
96
69
97
-
int cv1800_pinctrl_probe(struct platform_device *pdev);
70
+
extern const struct pinctrl_ops cv1800_pctrl_ops;
71
+
extern const struct pinmux_ops cv1800_pmx_ops;
72
+
extern const struct pinconf_ops cv1800_pconf_ops;
73
+
extern const struct sophgo_cfg_ops cv1800_cfg_ops;
98
74
99
75
#define CV1800_FUNC_PIN(_id, _power_domain, _type, \
100
76
_mux_area, _mux_offset, _mux_func_max) \
101
77
{ \
102
-
.pin = (_id), \
78
+
.pin = { \
79
+
.id = (_id), \
80
+
.flags = CV1800_PIN_FLAG_IO_TYPE(_type), \
81
+
}, \
103
82
.power_domain = (_power_domain), \
104
-
.flags = CV1800_PIN_FLAG_IO_TYPE(_type), \
105
83
.mux = { \
106
84
.area = (_mux_area), \
107
85
.offset = (_mux_offset), \
···
92
112
_mux_area, _mux_offset, _mux_func_max, \
93
113
_conf_area, _conf_offset) \
94
114
{ \
95
-
.pin = (_id), \
115
+
.pin = { \
116
+
.id = (_id), \
117
+
.flags = CV1800_PIN_FLAG_IO_TYPE(_type), \
118
+
}, \
96
119
.power_domain = (_power_domain), \
97
-
.flags = CV1800_PIN_FLAG_IO_TYPE(_type), \
98
120
.mux = { \
99
121
.area = (_mux_area), \
100
122
.offset = (_mux_offset), \
···
114
132
_mux2_func_max, \
115
133
_conf_area, _conf_offset) \
116
134
{ \
117
-
.pin = (_id), \
135
+
.pin = { \
136
+
.id = (_id), \
137
+
.flags = CV1800_PIN_FLAG_IO_TYPE(_type) | \
138
+
CV1800_PIN_HAVE_MUX2, \
139
+
}, \
118
140
.power_domain = (_power_domain), \
119
-
.flags = CV1800_PIN_FLAG_IO_TYPE(_type) | \
120
-
CV1800_PIN_HAVE_MUX2, \
121
141
.mux = { \
122
142
.area = (_mux_area), \
123
143
.offset = (_mux_offset), \
+18
-9
drivers/pinctrl/sophgo/pinctrl-sg2000.c
+18
-9
drivers/pinctrl/sophgo/pinctrl-sg2000.c
···
40
40
[VDDIO_VIVO] = "VDDIO_VIVO",
41
41
};
42
42
43
-
static int sg2000_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
43
+
static int sg2000_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap)
44
44
{
45
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
45
46
u32 pstate = psmap[pin->power_domain];
46
47
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
47
48
···
61
60
return -ENOTSUPP;
62
61
}
63
62
64
-
static int sg2000_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
63
+
static int sg2000_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap)
65
64
{
65
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
66
66
u32 pstate = psmap[pin->power_domain];
67
67
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
68
68
···
116
114
17800
117
115
};
118
116
119
-
static int sg2000_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
117
+
static int sg2000_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap,
120
118
const u32 **map)
121
119
{
120
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
122
121
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
123
122
u32 pstate = psmap[pin->power_domain];
124
123
···
162
159
1100000
163
160
};
164
161
165
-
static int sg2000_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
162
+
static int sg2000_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap,
166
163
const u32 **map)
167
164
{
165
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
168
166
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
169
167
u32 pstate = psmap[pin->power_domain];
170
168
···
187
183
return -ENOTSUPP;
188
184
}
189
185
190
-
static const struct cv1800_vddio_cfg_ops sg2000_vddio_cfg_ops = {
186
+
static const struct sophgo_vddio_cfg_ops sg2000_vddio_cfg_ops = {
191
187
.get_pull_up = sg2000_get_pull_up,
192
188
.get_pull_down = sg2000_get_pull_down,
193
189
.get_oc_map = sg2000_get_oc_map,
194
-
.get_schmitt_map = sg2000_get_schmitt_map,
190
+
.get_schmitt_map = sg2000_get_schmitt_map,
195
191
};
196
192
197
193
static const struct pinctrl_pin_desc sg2000_pins[] = {
···
746
742
CV1800_PINCONF_AREA_RTC, 0x028),
747
743
};
748
744
749
-
static const struct cv1800_pinctrl_data sg2000_pindata = {
745
+
static const struct sophgo_pinctrl_data sg2000_pindata = {
750
746
.pins = sg2000_pins,
751
747
.pindata = sg2000_pin_data,
752
748
.pdnames = sg2000_power_domain_desc,
753
749
.vddio_ops = &sg2000_vddio_cfg_ops,
750
+
.cfg_ops = &cv1800_cfg_ops,
751
+
.pctl_ops = &cv1800_pctrl_ops,
752
+
.pmx_ops = &cv1800_pmx_ops,
753
+
.pconf_ops = &cv1800_pconf_ops,
754
754
.npins = ARRAY_SIZE(sg2000_pins),
755
-
.npd = ARRAY_SIZE(sg2000_power_domain_desc),
755
+
.npds = ARRAY_SIZE(sg2000_power_domain_desc),
756
+
.pinsize = sizeof(struct cv1800_pin),
756
757
};
757
758
758
759
static const struct of_device_id sg2000_pinctrl_ids[] = {
···
767
758
MODULE_DEVICE_TABLE(of, sg2000_pinctrl_ids);
768
759
769
760
static struct platform_driver sg2000_pinctrl_driver = {
770
-
.probe = cv1800_pinctrl_probe,
761
+
.probe = sophgo_pinctrl_probe,
771
762
.driver = {
772
763
.name = "sg2000-pinctrl",
773
764
.suppress_bind_attrs = true,
+18
-9
drivers/pinctrl/sophgo/pinctrl-sg2002.c
+18
-9
drivers/pinctrl/sophgo/pinctrl-sg2002.c
···
34
34
[VDDIO_SD1] = "VDDIO_SD1",
35
35
};
36
36
37
-
static int sg2002_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
37
+
static int sg2002_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap)
38
38
{
39
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
39
40
u32 pstate = psmap[pin->power_domain];
40
41
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
41
42
···
55
54
return -ENOTSUPP;
56
55
}
57
56
58
-
static int sg2002_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
57
+
static int sg2002_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap)
59
58
{
59
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
60
60
u32 pstate = psmap[pin->power_domain];
61
61
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
62
62
···
110
108
17800
111
109
};
112
110
113
-
static int sg2002_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
111
+
static int sg2002_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap,
114
112
const u32 **map)
115
113
{
114
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
116
115
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
117
116
u32 pstate = psmap[pin->power_domain];
118
117
···
156
153
1100000
157
154
};
158
155
159
-
static int sg2002_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
156
+
static int sg2002_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap,
160
157
const u32 **map)
161
158
{
159
+
const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
162
160
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
163
161
u32 pstate = psmap[pin->power_domain];
164
162
···
181
177
return -ENOTSUPP;
182
178
}
183
179
184
-
static const struct cv1800_vddio_cfg_ops sg2002_vddio_cfg_ops = {
180
+
static const struct sophgo_vddio_cfg_ops sg2002_vddio_cfg_ops = {
185
181
.get_pull_up = sg2002_get_pull_up,
186
182
.get_pull_down = sg2002_get_pull_down,
187
183
.get_oc_map = sg2002_get_oc_map,
188
-
.get_schmitt_map = sg2002_get_schmitt_map,
184
+
.get_schmitt_map = sg2002_get_schmitt_map,
189
185
};
190
186
191
187
static const struct pinctrl_pin_desc sg2002_pins[] = {
···
517
513
CV1800_PINCONF_AREA_SYS, 0xc84),
518
514
};
519
515
520
-
static const struct cv1800_pinctrl_data sg2002_pindata = {
516
+
static const struct sophgo_pinctrl_data sg2002_pindata = {
521
517
.pins = sg2002_pins,
522
518
.pindata = sg2002_pin_data,
523
519
.pdnames = sg2002_power_domain_desc,
524
520
.vddio_ops = &sg2002_vddio_cfg_ops,
521
+
.cfg_ops = &cv1800_cfg_ops,
522
+
.pctl_ops = &cv1800_pctrl_ops,
523
+
.pmx_ops = &cv1800_pmx_ops,
524
+
.pconf_ops = &cv1800_pconf_ops,
525
525
.npins = ARRAY_SIZE(sg2002_pins),
526
-
.npd = ARRAY_SIZE(sg2002_power_domain_desc),
526
+
.npds = ARRAY_SIZE(sg2002_power_domain_desc),
527
+
.pinsize = sizeof(struct cv1800_pin),
527
528
};
528
529
529
530
static const struct of_device_id sg2002_pinctrl_ids[] = {
···
538
529
MODULE_DEVICE_TABLE(of, sg2002_pinctrl_ids);
539
530
540
531
static struct platform_driver sg2002_pinctrl_driver = {
541
-
.probe = cv1800_pinctrl_probe,
532
+
.probe = sophgo_pinctrl_probe,
542
533
.driver = {
543
534
.name = "sg2002-pinctrl",
544
535
.suppress_bind_attrs = true,
+296
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
+296
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo sg2042 SoCs pinctrl driver.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*
7
+
*/
8
+
9
+
#include <linux/bitfield.h>
10
+
#include <linux/bits.h>
11
+
#include <linux/cleanup.h>
12
+
#include <linux/export.h>
13
+
#include <linux/io.h>
14
+
#include <linux/of.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/seq_file.h>
17
+
#include <linux/spinlock.h>
18
+
19
+
#include <linux/pinctrl/pinconf-generic.h>
20
+
#include <linux/pinctrl/pinconf.h>
21
+
#include <linux/pinctrl/pinctrl.h>
22
+
#include <linux/pinctrl/pinmux.h>
23
+
24
+
#include "../pinctrl-utils.h"
25
+
#include "../pinmux.h"
26
+
27
+
#include "pinctrl-sg2042.h"
28
+
29
+
#define PIN_IO_PULL_ONE_ENABLE BIT(0)
30
+
#define PIN_IO_PULL_DIR_UP (BIT(1) | PIN_IO_PULL_ONE_ENABLE)
31
+
#define PIN_IO_PULL_DIR_DOWN (0 | PIN_IO_PULL_ONE_ENABLE)
32
+
#define PIN_IO_PULL_ONE_MASK GENMASK(1, 0)
33
+
34
+
#define PIN_IO_PULL_UP BIT(2)
35
+
#define PIN_IO_PULL_UP_DONW BIT(3)
36
+
#define PIN_IO_PULL_UP_MASK GENMASK(3, 2)
37
+
38
+
#define PIN_IO_MUX GENMASK(5, 4)
39
+
#define PIN_IO_DRIVE GENMASK(9, 6)
40
+
#define PIN_IO_SCHMITT_ENABLE BIT(10)
41
+
#define PIN_IO_OUTPUT_ENABLE BIT(11)
42
+
43
+
struct sg2042_priv {
44
+
void __iomem *regs;
45
+
};
46
+
47
+
static u8 sg2042_dt_get_pin_mux(u32 value)
48
+
{
49
+
return value >> 16;
50
+
}
51
+
52
+
static inline u32 sg2042_get_pin_reg(struct sophgo_pinctrl *pctrl,
53
+
const struct sophgo_pin *sp)
54
+
{
55
+
struct sg2042_priv *priv = pctrl->priv_ctrl;
56
+
const struct sg2042_pin *pin = sophgo_to_sg2042_pin(sp);
57
+
void __iomem *reg = priv->regs + pin->offset;
58
+
59
+
if (sp->flags & PIN_FLAG_WRITE_HIGH)
60
+
return readl(reg) >> 16;
61
+
else
62
+
return readl(reg) & 0xffff;
63
+
}
64
+
65
+
static int sg2042_set_pin_reg(struct sophgo_pinctrl *pctrl,
66
+
const struct sophgo_pin *sp,
67
+
u32 value, u32 mask)
68
+
{
69
+
struct sg2042_priv *priv = pctrl->priv_ctrl;
70
+
const struct sg2042_pin *pin = sophgo_to_sg2042_pin(sp);
71
+
void __iomem *reg = priv->regs + pin->offset;
72
+
u32 v = readl(reg);
73
+
74
+
if (sp->flags & PIN_FLAG_WRITE_HIGH) {
75
+
v &= ~(mask << 16);
76
+
v |= value << 16;
77
+
} else {
78
+
v &= ~mask;
79
+
v |= value;
80
+
}
81
+
82
+
writel(v, reg);
83
+
84
+
return 0;
85
+
}
86
+
87
+
static void sg2042_pctrl_dbg_show(struct pinctrl_dev *pctldev,
88
+
struct seq_file *seq, unsigned int pin_id)
89
+
{
90
+
struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
91
+
const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id);
92
+
u32 value, mux;
93
+
94
+
value = sg2042_get_pin_reg(pctrl, sp);
95
+
mux = FIELD_GET(PIN_IO_MUX, value);
96
+
seq_printf(seq, "mux:%u reg:0x%04x ", mux, value);
97
+
}
98
+
99
+
const struct pinctrl_ops sg2042_pctrl_ops = {
100
+
.get_groups_count = pinctrl_generic_get_group_count,
101
+
.get_group_name = pinctrl_generic_get_group_name,
102
+
.get_group_pins = pinctrl_generic_get_group_pins,
103
+
.pin_dbg_show = sg2042_pctrl_dbg_show,
104
+
.dt_node_to_map = sophgo_pctrl_dt_node_to_map,
105
+
.dt_free_map = pinctrl_utils_free_map,
106
+
};
107
+
EXPORT_SYMBOL_GPL(sg2042_pctrl_ops);
108
+
109
+
static void sg2042_set_pinmux_config(struct sophgo_pinctrl *pctrl,
110
+
const struct sophgo_pin *sp, u32 config)
111
+
{
112
+
u32 mux = sg2042_dt_get_pin_mux(config);
113
+
114
+
if (!(sp->flags & PIN_FLAG_NO_PINMUX))
115
+
sg2042_set_pin_reg(pctrl, sp, mux, PIN_IO_MUX);
116
+
}
117
+
118
+
const struct pinmux_ops sg2042_pmx_ops = {
119
+
.get_functions_count = pinmux_generic_get_function_count,
120
+
.get_function_name = pinmux_generic_get_function_name,
121
+
.get_function_groups = pinmux_generic_get_function_groups,
122
+
.set_mux = sophgo_pmx_set_mux,
123
+
.strict = true,
124
+
};
125
+
EXPORT_SYMBOL_GPL(sg2042_pmx_ops);
126
+
127
+
static int sg2042_pconf_get(struct pinctrl_dev *pctldev,
128
+
unsigned int pin_id, unsigned long *config)
129
+
{
130
+
struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
131
+
int param = pinconf_to_config_param(*config);
132
+
const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id);
133
+
u32 value;
134
+
u32 arg;
135
+
bool enabled;
136
+
int ret;
137
+
138
+
if (!sp)
139
+
return -EINVAL;
140
+
141
+
value = sg2042_get_pin_reg(pctrl, sp);
142
+
143
+
switch (param) {
144
+
case PIN_CONFIG_BIAS_DISABLE:
145
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL)
146
+
arg = FIELD_GET(PIN_IO_PULL_ONE_ENABLE, value);
147
+
else
148
+
arg = FIELD_GET(PIN_IO_PULL_UP_MASK, value);
149
+
enabled = arg == 0;
150
+
break;
151
+
case PIN_CONFIG_BIAS_PULL_DOWN:
152
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
153
+
arg = FIELD_GET(PIN_IO_PULL_ONE_MASK, value);
154
+
enabled = arg == PIN_IO_PULL_DIR_DOWN;
155
+
} else {
156
+
enabled = FIELD_GET(PIN_IO_PULL_UP_DONW, value) != 0;
157
+
}
158
+
arg = sophgo_pinctrl_typical_pull_down(pctrl, sp, NULL);
159
+
break;
160
+
case PIN_CONFIG_BIAS_PULL_UP:
161
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
162
+
arg = FIELD_GET(PIN_IO_PULL_ONE_MASK, value);
163
+
enabled = arg == PIN_IO_PULL_DIR_UP;
164
+
} else {
165
+
enabled = FIELD_GET(PIN_IO_PULL_UP, value) != 0;
166
+
}
167
+
arg = sophgo_pinctrl_typical_pull_up(pctrl, sp, NULL);
168
+
break;
169
+
case PIN_CONFIG_DRIVE_STRENGTH_UA:
170
+
enabled = FIELD_GET(PIN_IO_OUTPUT_ENABLE, value) != 0;
171
+
arg = FIELD_GET(PIN_IO_DRIVE, value);
172
+
ret = sophgo_pinctrl_reg2oc(pctrl, sp, NULL, arg);
173
+
if (ret < 0)
174
+
return ret;
175
+
arg = ret;
176
+
break;
177
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
178
+
arg = FIELD_GET(PIN_IO_SCHMITT_ENABLE, value);
179
+
enabled = arg != 0;
180
+
break;
181
+
default:
182
+
return -ENOTSUPP;
183
+
}
184
+
185
+
*config = pinconf_to_config_packed(param, arg);
186
+
187
+
return enabled ? 0 : -EINVAL;
188
+
}
189
+
190
+
static int sg2042_pinconf_compute_config(struct sophgo_pinctrl *pctrl,
191
+
const struct sophgo_pin *sp,
192
+
unsigned long *configs,
193
+
unsigned int num_configs,
194
+
u32 *value, u32 *mask)
195
+
{
196
+
int i;
197
+
u16 v = 0, m = 0;
198
+
int ret;
199
+
200
+
if (!sp)
201
+
return -EINVAL;
202
+
203
+
for (i = 0; i < num_configs; i++) {
204
+
int param = pinconf_to_config_param(configs[i]);
205
+
u32 arg = pinconf_to_config_argument(configs[i]);
206
+
207
+
switch (param) {
208
+
case PIN_CONFIG_BIAS_DISABLE:
209
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
210
+
v &= ~PIN_IO_PULL_ONE_ENABLE;
211
+
m |= PIN_IO_PULL_ONE_ENABLE;
212
+
} else {
213
+
v &= ~PIN_IO_PULL_UP_MASK;
214
+
m |= PIN_IO_PULL_UP_MASK;
215
+
}
216
+
break;
217
+
case PIN_CONFIG_BIAS_PULL_DOWN:
218
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
219
+
v &= ~PIN_IO_PULL_ONE_MASK;
220
+
v |= PIN_IO_PULL_DIR_DOWN;
221
+
m |= PIN_IO_PULL_ONE_MASK;
222
+
} else {
223
+
v |= PIN_IO_PULL_UP_DONW;
224
+
m |= PIN_IO_PULL_UP_DONW;
225
+
}
226
+
break;
227
+
case PIN_CONFIG_BIAS_PULL_UP:
228
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
229
+
v &= ~PIN_IO_PULL_ONE_MASK;
230
+
v |= PIN_IO_PULL_DIR_UP;
231
+
m |= PIN_IO_PULL_ONE_MASK;
232
+
} else {
233
+
v |= PIN_IO_PULL_UP;
234
+
m |= PIN_IO_PULL_UP;
235
+
}
236
+
break;
237
+
case PIN_CONFIG_DRIVE_STRENGTH_UA:
238
+
v &= ~(PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE);
239
+
if (arg != 0) {
240
+
ret = sophgo_pinctrl_oc2reg(pctrl, sp, NULL, arg);
241
+
if (ret < 0)
242
+
return ret;
243
+
if (!(sp->flags & PIN_FLAG_NO_OEX_EN))
244
+
v |= PIN_IO_OUTPUT_ENABLE;
245
+
v |= FIELD_PREP(PIN_IO_DRIVE, ret);
246
+
}
247
+
m |= PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE;
248
+
break;
249
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
250
+
v |= PIN_IO_SCHMITT_ENABLE;
251
+
m |= PIN_IO_SCHMITT_ENABLE;
252
+
break;
253
+
default:
254
+
return -ENOTSUPP;
255
+
}
256
+
}
257
+
258
+
*value = v;
259
+
*mask = m;
260
+
261
+
return 0;
262
+
}
263
+
264
+
const struct pinconf_ops sg2042_pconf_ops = {
265
+
.pin_config_get = sg2042_pconf_get,
266
+
.pin_config_set = sophgo_pconf_set,
267
+
.pin_config_group_set = sophgo_pconf_group_set,
268
+
.is_generic = true,
269
+
};
270
+
EXPORT_SYMBOL_GPL(sg2042_pconf_ops);
271
+
272
+
static int sophgo_pinctrl_init(struct platform_device *pdev,
273
+
struct sophgo_pinctrl *pctrl)
274
+
{
275
+
struct sg2042_priv *priv;
276
+
277
+
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
278
+
if (!priv)
279
+
return -ENOMEM;
280
+
281
+
priv->regs = devm_platform_ioremap_resource(pdev, 0);
282
+
if (IS_ERR(priv->regs))
283
+
return PTR_ERR(priv->regs);
284
+
285
+
pctrl->priv_ctrl = priv;
286
+
287
+
return 0;
288
+
}
289
+
290
+
const struct sophgo_cfg_ops sg2042_cfg_ops = {
291
+
.pctrl_init = sophgo_pinctrl_init,
292
+
.compute_pinconf_config = sg2042_pinconf_compute_config,
293
+
.set_pinconf_config = sg2042_set_pin_reg,
294
+
.set_pinmux_config = sg2042_set_pinmux_config,
295
+
};
296
+
EXPORT_SYMBOL_GPL(sg2042_cfg_ops);
+655
drivers/pinctrl/sophgo/pinctrl-sg2042.c
+655
drivers/pinctrl/sophgo/pinctrl-sg2042.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo SG2042 SoC pinctrl driver.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*/
7
+
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/of.h>
11
+
12
+
#include <linux/pinctrl/pinctrl.h>
13
+
#include <linux/pinctrl/pinmux.h>
14
+
15
+
#include <dt-bindings/pinctrl/pinctrl-sg2042.h>
16
+
17
+
#include "pinctrl-sg2042.h"
18
+
19
+
static int sg2042_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap)
20
+
{
21
+
return 35000;
22
+
}
23
+
24
+
static int sg2042_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap)
25
+
{
26
+
return 28000;
27
+
}
28
+
29
+
static const u32 sg2042_oc_map[] = {
30
+
5400, 8100, 10700, 13400,
31
+
16100, 18800, 21400, 24100,
32
+
26800, 29400, 32100, 34800,
33
+
37400, 40100, 42800, 45400
34
+
};
35
+
36
+
static int sg2042_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap,
37
+
const u32 **map)
38
+
{
39
+
*map = sg2042_oc_map;
40
+
return ARRAY_SIZE(sg2042_oc_map);
41
+
}
42
+
43
+
static const struct sophgo_vddio_cfg_ops sg2042_vddio_cfg_ops = {
44
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.get_pull_up = sg2042_get_pull_up,
45
+
.get_pull_down = sg2042_get_pull_down,
46
+
.get_oc_map = sg2042_get_oc_map,
47
+
};
48
+
49
+
static const struct pinctrl_pin_desc sg2042_pins[] = {
50
+
PINCTRL_PIN(PIN_LPC_LCLK, "lpc_lclk"),
51
+
PINCTRL_PIN(PIN_LPC_LFRAME, "lpc_lframe"),
52
+
PINCTRL_PIN(PIN_LPC_LAD0, "lpc_lad0"),
53
+
PINCTRL_PIN(PIN_LPC_LAD1, "lpc_lad1"),
54
+
PINCTRL_PIN(PIN_LPC_LAD2, "lpc_lad2"),
55
+
PINCTRL_PIN(PIN_LPC_LAD3, "lpc_lad3"),
56
+
PINCTRL_PIN(PIN_LPC_LDRQ0, "lpc_ldrq0"),
57
+
PINCTRL_PIN(PIN_LPC_LDRQ1, "lpc_ldrq1"),
58
+
PINCTRL_PIN(PIN_LPC_SERIRQ, "lpc_serirq"),
59
+
PINCTRL_PIN(PIN_LPC_CLKRUN, "lpc_clkrun"),
60
+
PINCTRL_PIN(PIN_LPC_LPME, "lpc_lpme"),
61
+
PINCTRL_PIN(PIN_LPC_LPCPD, "lpc_lpcpd"),
62
+
PINCTRL_PIN(PIN_LPC_LSMI, "lpc_lsmi"),
63
+
PINCTRL_PIN(PIN_PCIE0_L0_RESET, "pcie0_l0_reset"),
64
+
PINCTRL_PIN(PIN_PCIE0_L1_RESET, "pcie0_l1_reset"),
65
+
PINCTRL_PIN(PIN_PCIE0_L0_WAKEUP, "pcie0_l0_wakeup"),
66
+
PINCTRL_PIN(PIN_PCIE0_L1_WAKEUP, "pcie0_l1_wakeup"),
67
+
PINCTRL_PIN(PIN_PCIE0_L0_CLKREQ_IN, "pcie0_l0_clkreq_in"),
68
+
PINCTRL_PIN(PIN_PCIE0_L1_CLKREQ_IN, "pcie0_l1_clkreq_in"),
69
+
PINCTRL_PIN(PIN_PCIE1_L0_RESET, "pcie1_l0_reset"),
70
+
PINCTRL_PIN(PIN_PCIE1_L1_RESET, "pcie1_l1_reset"),
71
+
PINCTRL_PIN(PIN_PCIE1_L0_WAKEUP, "pcie1_l0_wakeup"),
72
+
PINCTRL_PIN(PIN_PCIE1_L1_WAKEUP, "pcie1_l1_wakeup"),
73
+
PINCTRL_PIN(PIN_PCIE1_L0_CLKREQ_IN, "pcie1_l0_clkreq_in"),
74
+
PINCTRL_PIN(PIN_PCIE1_L1_CLKREQ_IN, "pcie1_l1_clkreq_in"),
75
+
PINCTRL_PIN(PIN_SPIF0_CLK_SEL1, "spif0_clk_sel1"),
76
+
PINCTRL_PIN(PIN_SPIF0_CLK_SEL0, "spif0_clk_sel0"),
77
+
PINCTRL_PIN(PIN_SPIF0_WP, "spif0_wp"),
78
+
PINCTRL_PIN(PIN_SPIF0_HOLD, "spif0_hold"),
79
+
PINCTRL_PIN(PIN_SPIF0_SDI, "spif0_sdi"),
80
+
PINCTRL_PIN(PIN_SPIF0_CS, "spif0_cs"),
81
+
PINCTRL_PIN(PIN_SPIF0_SCK, "spif0_sck"),
82
+
PINCTRL_PIN(PIN_SPIF0_SDO, "spif0_sdo"),
83
+
PINCTRL_PIN(PIN_SPIF1_CLK_SEL1, "spif1_clk_sel1"),
84
+
PINCTRL_PIN(PIN_SPIF1_CLK_SEL0, "spif1_clk_sel0"),
85
+
PINCTRL_PIN(PIN_SPIF1_WP, "spif1_wp"),
86
+
PINCTRL_PIN(PIN_SPIF1_HOLD, "spif1_hold"),
87
+
PINCTRL_PIN(PIN_SPIF1_SDI, "spif1_sdi"),
88
+
PINCTRL_PIN(PIN_SPIF1_CS, "spif1_cs"),
89
+
PINCTRL_PIN(PIN_SPIF1_SCK, "spif1_sck"),
90
+
PINCTRL_PIN(PIN_SPIF1_SDO, "spif1_sdo"),
91
+
PINCTRL_PIN(PIN_EMMC_WP, "emmc_wp"),
92
+
PINCTRL_PIN(PIN_EMMC_CD, "emmc_cd"),
93
+
PINCTRL_PIN(PIN_EMMC_RST, "emmc_rst"),
94
+
PINCTRL_PIN(PIN_EMMC_PWR_EN, "emmc_pwr_en"),
95
+
PINCTRL_PIN(PIN_SDIO_CD, "sdio_cd"),
96
+
PINCTRL_PIN(PIN_SDIO_WP, "sdio_wp"),
97
+
PINCTRL_PIN(PIN_SDIO_RST, "sdio_rst"),
98
+
PINCTRL_PIN(PIN_SDIO_PWR_EN, "sdio_pwr_en"),
99
+
PINCTRL_PIN(PIN_RGMII0_TXD0, "rgmii0_txd0"),
100
+
PINCTRL_PIN(PIN_RGMII0_TXD1, "rgmii0_txd1"),
101
+
PINCTRL_PIN(PIN_RGMII0_TXD2, "rgmii0_txd2"),
102
+
PINCTRL_PIN(PIN_RGMII0_TXD3, "rgmii0_txd3"),
103
+
PINCTRL_PIN(PIN_RGMII0_TXCTRL, "rgmii0_txctrl"),
104
+
PINCTRL_PIN(PIN_RGMII0_RXD0, "rgmii0_rxd0"),
105
+
PINCTRL_PIN(PIN_RGMII0_RXD1, "rgmii0_rxd1"),
106
+
PINCTRL_PIN(PIN_RGMII0_RXD2, "rgmii0_rxd2"),
107
+
PINCTRL_PIN(PIN_RGMII0_RXD3, "rgmii0_rxd3"),
108
+
PINCTRL_PIN(PIN_RGMII0_RXCTRL, "rgmii0_rxctrl"),
109
+
PINCTRL_PIN(PIN_RGMII0_TXC, "rgmii0_txc"),
110
+
PINCTRL_PIN(PIN_RGMII0_RXC, "rgmii0_rxc"),
111
+
PINCTRL_PIN(PIN_RGMII0_REFCLKO, "rgmii0_refclko"),
112
+
PINCTRL_PIN(PIN_RGMII0_IRQ, "rgmii0_irq"),
113
+
PINCTRL_PIN(PIN_RGMII0_MDC, "rgmii0_mdc"),
114
+
PINCTRL_PIN(PIN_RGMII0_MDIO, "rgmii0_mdio"),
115
+
PINCTRL_PIN(PIN_PWM0, "pwm0"),
116
+
PINCTRL_PIN(PIN_PWM1, "pwm1"),
117
+
PINCTRL_PIN(PIN_PWM2, "pwm2"),
118
+
PINCTRL_PIN(PIN_PWM3, "pwm3"),
119
+
PINCTRL_PIN(PIN_FAN0, "fan0"),
120
+
PINCTRL_PIN(PIN_FAN1, "fan1"),
121
+
PINCTRL_PIN(PIN_FAN2, "fan2"),
122
+
PINCTRL_PIN(PIN_FAN3, "fan3"),
123
+
PINCTRL_PIN(PIN_IIC0_SDA, "iic0_sda"),
124
+
PINCTRL_PIN(PIN_IIC0_SCL, "iic0_scl"),
125
+
PINCTRL_PIN(PIN_IIC1_SDA, "iic1_sda"),
126
+
PINCTRL_PIN(PIN_IIC1_SCL, "iic1_scl"),
127
+
PINCTRL_PIN(PIN_IIC2_SDA, "iic2_sda"),
128
+
PINCTRL_PIN(PIN_IIC2_SCL, "iic2_scl"),
129
+
PINCTRL_PIN(PIN_IIC3_SDA, "iic3_sda"),
130
+
PINCTRL_PIN(PIN_IIC3_SCL, "iic3_scl"),
131
+
PINCTRL_PIN(PIN_UART0_TX, "uart0_tx"),
132
+
PINCTRL_PIN(PIN_UART0_RX, "uart0_rx"),
133
+
PINCTRL_PIN(PIN_UART0_RTS, "uart0_rts"),
134
+
PINCTRL_PIN(PIN_UART0_CTS, "uart0_cts"),
135
+
PINCTRL_PIN(PIN_UART1_TX, "uart1_tx"),
136
+
PINCTRL_PIN(PIN_UART1_RX, "uart1_rx"),
137
+
PINCTRL_PIN(PIN_UART1_RTS, "uart1_rts"),
138
+
PINCTRL_PIN(PIN_UART1_CTS, "uart1_cts"),
139
+
PINCTRL_PIN(PIN_UART2_TX, "uart2_tx"),
140
+
PINCTRL_PIN(PIN_UART2_RX, "uart2_rx"),
141
+
PINCTRL_PIN(PIN_UART2_RTS, "uart2_rts"),
142
+
PINCTRL_PIN(PIN_UART2_CTS, "uart2_cts"),
143
+
PINCTRL_PIN(PIN_UART3_TX, "uart3_tx"),
144
+
PINCTRL_PIN(PIN_UART3_RX, "uart3_rx"),
145
+
PINCTRL_PIN(PIN_UART3_RTS, "uart3_rts"),
146
+
PINCTRL_PIN(PIN_UART3_CTS, "uart3_cts"),
147
+
PINCTRL_PIN(PIN_SPI0_CS0, "spi0_cs0"),
148
+
PINCTRL_PIN(PIN_SPI0_CS1, "spi0_cs1"),
149
+
PINCTRL_PIN(PIN_SPI0_SDI, "spi0_sdi"),
150
+
PINCTRL_PIN(PIN_SPI0_SDO, "spi0_sdo"),
151
+
PINCTRL_PIN(PIN_SPI0_SCK, "spi0_sck"),
152
+
PINCTRL_PIN(PIN_SPI1_CS0, "spi1_cs0"),
153
+
PINCTRL_PIN(PIN_SPI1_CS1, "spi1_cs1"),
154
+
PINCTRL_PIN(PIN_SPI1_SDI, "spi1_sdi"),
155
+
PINCTRL_PIN(PIN_SPI1_SDO, "spi1_sdo"),
156
+
PINCTRL_PIN(PIN_SPI1_SCK, "spi1_sck"),
157
+
PINCTRL_PIN(PIN_JTAG0_TDO, "jtag0_tdo"),
158
+
PINCTRL_PIN(PIN_JTAG0_TCK, "jtag0_tck"),
159
+
PINCTRL_PIN(PIN_JTAG0_TDI, "jtag0_tdi"),
160
+
PINCTRL_PIN(PIN_JTAG0_TMS, "jtag0_tms"),
161
+
PINCTRL_PIN(PIN_JTAG0_TRST, "jtag0_trst"),
162
+
PINCTRL_PIN(PIN_JTAG0_SRST, "jtag0_srst"),
163
+
PINCTRL_PIN(PIN_JTAG1_TDO, "jtag1_tdo"),
164
+
PINCTRL_PIN(PIN_JTAG1_TCK, "jtag1_tck"),
165
+
PINCTRL_PIN(PIN_JTAG1_TDI, "jtag1_tdi"),
166
+
PINCTRL_PIN(PIN_JTAG1_TMS, "jtag1_tms"),
167
+
PINCTRL_PIN(PIN_JTAG1_TRST, "jtag1_trst"),
168
+
PINCTRL_PIN(PIN_JTAG1_SRST, "jtag1_srst"),
169
+
PINCTRL_PIN(PIN_JTAG2_TDO, "jtag2_tdo"),
170
+
PINCTRL_PIN(PIN_JTAG2_TCK, "jtag2_tck"),
171
+
PINCTRL_PIN(PIN_JTAG2_TDI, "jtag2_tdi"),
172
+
PINCTRL_PIN(PIN_JTAG2_TMS, "jtag2_tms"),
173
+
PINCTRL_PIN(PIN_JTAG2_TRST, "jtag2_trst"),
174
+
PINCTRL_PIN(PIN_JTAG2_SRST, "jtag2_srst"),
175
+
PINCTRL_PIN(PIN_GPIO0, "gpio0"),
176
+
PINCTRL_PIN(PIN_GPIO1, "gpio1"),
177
+
PINCTRL_PIN(PIN_GPIO2, "gpio2"),
178
+
PINCTRL_PIN(PIN_GPIO3, "gpio3"),
179
+
PINCTRL_PIN(PIN_GPIO4, "gpio4"),
180
+
PINCTRL_PIN(PIN_GPIO5, "gpio5"),
181
+
PINCTRL_PIN(PIN_GPIO6, "gpio6"),
182
+
PINCTRL_PIN(PIN_GPIO7, "gpio7"),
183
+
PINCTRL_PIN(PIN_GPIO8, "gpio8"),
184
+
PINCTRL_PIN(PIN_GPIO9, "gpio9"),
185
+
PINCTRL_PIN(PIN_GPIO10, "gpio10"),
186
+
PINCTRL_PIN(PIN_GPIO11, "gpio11"),
187
+
PINCTRL_PIN(PIN_GPIO12, "gpio12"),
188
+
PINCTRL_PIN(PIN_GPIO13, "gpio13"),
189
+
PINCTRL_PIN(PIN_GPIO14, "gpio14"),
190
+
PINCTRL_PIN(PIN_GPIO15, "gpio15"),
191
+
PINCTRL_PIN(PIN_GPIO16, "gpio16"),
192
+
PINCTRL_PIN(PIN_GPIO17, "gpio17"),
193
+
PINCTRL_PIN(PIN_GPIO18, "gpio18"),
194
+
PINCTRL_PIN(PIN_GPIO19, "gpio19"),
195
+
PINCTRL_PIN(PIN_GPIO20, "gpio20"),
196
+
PINCTRL_PIN(PIN_GPIO21, "gpio21"),
197
+
PINCTRL_PIN(PIN_GPIO22, "gpio22"),
198
+
PINCTRL_PIN(PIN_GPIO23, "gpio23"),
199
+
PINCTRL_PIN(PIN_GPIO24, "gpio24"),
200
+
PINCTRL_PIN(PIN_GPIO25, "gpio25"),
201
+
PINCTRL_PIN(PIN_GPIO26, "gpio26"),
202
+
PINCTRL_PIN(PIN_GPIO27, "gpio27"),
203
+
PINCTRL_PIN(PIN_GPIO28, "gpio28"),
204
+
PINCTRL_PIN(PIN_GPIO29, "gpio29"),
205
+
PINCTRL_PIN(PIN_GPIO30, "gpio30"),
206
+
PINCTRL_PIN(PIN_GPIO31, "gpio31"),
207
+
PINCTRL_PIN(PIN_MODE_SEL0, "mode_sel0"),
208
+
PINCTRL_PIN(PIN_MODE_SEL1, "mode_sel1"),
209
+
PINCTRL_PIN(PIN_MODE_SEL2, "mode_sel2"),
210
+
PINCTRL_PIN(PIN_BOOT_SEL0, "boot_sel0"),
211
+
PINCTRL_PIN(PIN_BOOT_SEL1, "boot_sel1"),
212
+
PINCTRL_PIN(PIN_BOOT_SEL2, "boot_sel2"),
213
+
PINCTRL_PIN(PIN_BOOT_SEL3, "boot_sel3"),
214
+
PINCTRL_PIN(PIN_BOOT_SEL4, "boot_sel4"),
215
+
PINCTRL_PIN(PIN_BOOT_SEL5, "boot_sel5"),
216
+
PINCTRL_PIN(PIN_BOOT_SEL6, "boot_sel6"),
217
+
PINCTRL_PIN(PIN_BOOT_SEL7, "boot_sel7"),
218
+
PINCTRL_PIN(PIN_MULTI_SCKT, "multi_sckt"),
219
+
PINCTRL_PIN(PIN_SCKT_ID0, "sckt_id0"),
220
+
PINCTRL_PIN(PIN_SCKT_ID1, "sckt_id1"),
221
+
PINCTRL_PIN(PIN_PLL_CLK_IN_MAIN, "pll_clk_in_main"),
222
+
PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_L, "pll_clk_in_ddr_l"),
223
+
PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_R, "pll_clk_in_ddr_r"),
224
+
PINCTRL_PIN(PIN_XTAL_32K, "xtal_32k"),
225
+
PINCTRL_PIN(PIN_SYS_RST, "sys_rst"),
226
+
PINCTRL_PIN(PIN_PWR_BUTTON, "pwr_button"),
227
+
PINCTRL_PIN(PIN_TEST_EN, "test_en"),
228
+
PINCTRL_PIN(PIN_TEST_MODE_MBIST, "test_mode_mbist"),
229
+
PINCTRL_PIN(PIN_TEST_MODE_SCAN, "test_mode_scan"),
230
+
PINCTRL_PIN(PIN_TEST_MODE_BSD, "test_mode_bsd"),
231
+
PINCTRL_PIN(PIN_BISR_BYP, "bisr_byp"),
232
+
};
233
+
234
+
static const struct sg2042_pin sg2042_pin_data[ARRAY_SIZE(sg2042_pins)] = {
235
+
SG2042_GENERAL_PIN(PIN_LPC_LCLK, 0x000,
236
+
PIN_FLAG_ONLY_ONE_PULL),
237
+
SG2042_GENERAL_PIN(PIN_LPC_LFRAME, 0x000,
238
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
239
+
SG2042_GENERAL_PIN(PIN_LPC_LAD0, 0x004,
240
+
PIN_FLAG_ONLY_ONE_PULL),
241
+
SG2042_GENERAL_PIN(PIN_LPC_LAD1, 0x004,
242
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
243
+
SG2042_GENERAL_PIN(PIN_LPC_LAD2, 0x008,
244
+
PIN_FLAG_ONLY_ONE_PULL),
245
+
SG2042_GENERAL_PIN(PIN_LPC_LAD3, 0x008,
246
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
247
+
SG2042_GENERAL_PIN(PIN_LPC_LDRQ0, 0x00c,
248
+
PIN_FLAG_ONLY_ONE_PULL),
249
+
SG2042_GENERAL_PIN(PIN_LPC_LDRQ1, 0x00c,
250
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
251
+
SG2042_GENERAL_PIN(PIN_LPC_SERIRQ, 0x010,
252
+
PIN_FLAG_ONLY_ONE_PULL),
253
+
SG2042_GENERAL_PIN(PIN_LPC_CLKRUN, 0x010,
254
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
255
+
SG2042_GENERAL_PIN(PIN_LPC_LPME, 0x014,
256
+
PIN_FLAG_ONLY_ONE_PULL),
257
+
SG2042_GENERAL_PIN(PIN_LPC_LPCPD, 0x014,
258
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
259
+
SG2042_GENERAL_PIN(PIN_LPC_LSMI, 0x018,
260
+
PIN_FLAG_ONLY_ONE_PULL),
261
+
SG2042_GENERAL_PIN(PIN_PCIE0_L0_RESET, 0x018,
262
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
263
+
SG2042_GENERAL_PIN(PIN_PCIE0_L1_RESET, 0x01c,
264
+
PIN_FLAG_ONLY_ONE_PULL),
265
+
SG2042_GENERAL_PIN(PIN_PCIE0_L0_WAKEUP, 0x01c,
266
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
267
+
SG2042_GENERAL_PIN(PIN_PCIE0_L1_WAKEUP, 0x020,
268
+
PIN_FLAG_ONLY_ONE_PULL),
269
+
SG2042_GENERAL_PIN(PIN_PCIE0_L0_CLKREQ_IN, 0x020,
270
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
271
+
SG2042_GENERAL_PIN(PIN_PCIE0_L1_CLKREQ_IN, 0x024,
272
+
PIN_FLAG_ONLY_ONE_PULL),
273
+
SG2042_GENERAL_PIN(PIN_PCIE1_L0_RESET, 0x024,
274
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
275
+
SG2042_GENERAL_PIN(PIN_PCIE1_L1_RESET, 0x028,
276
+
PIN_FLAG_ONLY_ONE_PULL),
277
+
SG2042_GENERAL_PIN(PIN_PCIE1_L0_WAKEUP, 0x028,
278
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
279
+
SG2042_GENERAL_PIN(PIN_PCIE1_L1_WAKEUP, 0x02c,
280
+
PIN_FLAG_ONLY_ONE_PULL),
281
+
SG2042_GENERAL_PIN(PIN_PCIE1_L0_CLKREQ_IN, 0x02c,
282
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
283
+
SG2042_GENERAL_PIN(PIN_PCIE1_L1_CLKREQ_IN, 0x030,
284
+
PIN_FLAG_ONLY_ONE_PULL),
285
+
SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL1, 0x030,
286
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
287
+
SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL0, 0x034,
288
+
PIN_FLAG_ONLY_ONE_PULL),
289
+
SG2042_GENERAL_PIN(PIN_SPIF0_WP, 0x034,
290
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
291
+
SG2042_GENERAL_PIN(PIN_SPIF0_HOLD, 0x038,
292
+
PIN_FLAG_ONLY_ONE_PULL),
293
+
SG2042_GENERAL_PIN(PIN_SPIF0_SDI, 0x038,
294
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
295
+
SG2042_GENERAL_PIN(PIN_SPIF0_CS, 0x03c,
296
+
PIN_FLAG_ONLY_ONE_PULL),
297
+
SG2042_GENERAL_PIN(PIN_SPIF0_SCK, 0x03c,
298
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
299
+
SG2042_GENERAL_PIN(PIN_SPIF0_SDO, 0x040,
300
+
PIN_FLAG_ONLY_ONE_PULL),
301
+
SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL1, 0x040,
302
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
303
+
SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL0, 0x044,
304
+
PIN_FLAG_ONLY_ONE_PULL),
305
+
SG2042_GENERAL_PIN(PIN_SPIF1_WP, 0x044,
306
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
307
+
SG2042_GENERAL_PIN(PIN_SPIF1_HOLD, 0x048,
308
+
PIN_FLAG_ONLY_ONE_PULL),
309
+
SG2042_GENERAL_PIN(PIN_SPIF1_SDI, 0x048,
310
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
311
+
SG2042_GENERAL_PIN(PIN_SPIF1_CS, 0x04c,
312
+
PIN_FLAG_ONLY_ONE_PULL),
313
+
SG2042_GENERAL_PIN(PIN_SPIF1_SCK, 0x04c,
314
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
315
+
SG2042_GENERAL_PIN(PIN_SPIF1_SDO, 0x050,
316
+
PIN_FLAG_ONLY_ONE_PULL),
317
+
SG2042_GENERAL_PIN(PIN_EMMC_WP, 0x050,
318
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
319
+
SG2042_GENERAL_PIN(PIN_EMMC_CD, 0x054,
320
+
PIN_FLAG_ONLY_ONE_PULL),
321
+
SG2042_GENERAL_PIN(PIN_EMMC_RST, 0x054,
322
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
323
+
SG2042_GENERAL_PIN(PIN_EMMC_PWR_EN, 0x058,
324
+
PIN_FLAG_ONLY_ONE_PULL),
325
+
SG2042_GENERAL_PIN(PIN_SDIO_CD, 0x058,
326
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
327
+
SG2042_GENERAL_PIN(PIN_SDIO_WP, 0x05c,
328
+
PIN_FLAG_ONLY_ONE_PULL),
329
+
SG2042_GENERAL_PIN(PIN_SDIO_RST, 0x05c,
330
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
331
+
SG2042_GENERAL_PIN(PIN_SDIO_PWR_EN, 0x060,
332
+
PIN_FLAG_ONLY_ONE_PULL),
333
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD0, 0x060,
334
+
PIN_FLAG_WRITE_HIGH),
335
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD1, 0x064,
336
+
PIN_FLAG_DEFAULT),
337
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD2, 0x064,
338
+
PIN_FLAG_WRITE_HIGH),
339
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD3, 0x068,
340
+
PIN_FLAG_DEFAULT),
341
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXCTRL, 0x068,
342
+
PIN_FLAG_WRITE_HIGH),
343
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD0, 0x06c,
344
+
PIN_FLAG_DEFAULT),
345
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD1, 0x06c,
346
+
PIN_FLAG_WRITE_HIGH),
347
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD2, 0x070,
348
+
PIN_FLAG_DEFAULT),
349
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD3, 0x070,
350
+
PIN_FLAG_WRITE_HIGH),
351
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXCTRL, 0x074,
352
+
PIN_FLAG_DEFAULT),
353
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXC, 0x074,
354
+
PIN_FLAG_WRITE_HIGH),
355
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXC, 0x078,
356
+
PIN_FLAG_DEFAULT),
357
+
SG2042_GENERAL_PIN(PIN_RGMII0_REFCLKO, 0x078,
358
+
PIN_FLAG_WRITE_HIGH),
359
+
SG2042_GENERAL_PIN(PIN_RGMII0_IRQ, 0x07c,
360
+
PIN_FLAG_DEFAULT),
361
+
SG2042_GENERAL_PIN(PIN_RGMII0_MDC, 0x07c,
362
+
PIN_FLAG_WRITE_HIGH),
363
+
SG2042_GENERAL_PIN(PIN_RGMII0_MDIO, 0x080,
364
+
PIN_FLAG_DEFAULT),
365
+
SG2042_GENERAL_PIN(PIN_PWM0, 0x080,
366
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
367
+
SG2042_GENERAL_PIN(PIN_PWM1, 0x084,
368
+
PIN_FLAG_ONLY_ONE_PULL),
369
+
SG2042_GENERAL_PIN(PIN_PWM2, 0x084,
370
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
371
+
SG2042_GENERAL_PIN(PIN_PWM3, 0x088,
372
+
PIN_FLAG_ONLY_ONE_PULL),
373
+
SG2042_GENERAL_PIN(PIN_FAN0, 0x088,
374
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
375
+
SG2042_GENERAL_PIN(PIN_FAN1, 0x08c,
376
+
PIN_FLAG_ONLY_ONE_PULL),
377
+
SG2042_GENERAL_PIN(PIN_FAN2, 0x08c,
378
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
379
+
SG2042_GENERAL_PIN(PIN_FAN3, 0x090,
380
+
PIN_FLAG_ONLY_ONE_PULL),
381
+
SG2042_GENERAL_PIN(PIN_IIC0_SDA, 0x090,
382
+
PIN_FLAG_WRITE_HIGH),
383
+
SG2042_GENERAL_PIN(PIN_IIC0_SCL, 0x094,
384
+
PIN_FLAG_DEFAULT),
385
+
SG2042_GENERAL_PIN(PIN_IIC1_SDA, 0x094,
386
+
PIN_FLAG_WRITE_HIGH),
387
+
SG2042_GENERAL_PIN(PIN_IIC1_SCL, 0x098,
388
+
PIN_FLAG_DEFAULT),
389
+
SG2042_GENERAL_PIN(PIN_IIC2_SDA, 0x098,
390
+
PIN_FLAG_WRITE_HIGH),
391
+
SG2042_GENERAL_PIN(PIN_IIC2_SCL, 0x09c,
392
+
PIN_FLAG_DEFAULT),
393
+
SG2042_GENERAL_PIN(PIN_IIC3_SDA, 0x09c,
394
+
PIN_FLAG_WRITE_HIGH),
395
+
SG2042_GENERAL_PIN(PIN_IIC3_SCL, 0x0a0,
396
+
PIN_FLAG_DEFAULT),
397
+
SG2042_GENERAL_PIN(PIN_UART0_TX, 0x0a0,
398
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
399
+
SG2042_GENERAL_PIN(PIN_UART0_RX, 0x0a4,
400
+
PIN_FLAG_ONLY_ONE_PULL),
401
+
SG2042_GENERAL_PIN(PIN_UART0_RTS, 0x0a4,
402
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
403
+
SG2042_GENERAL_PIN(PIN_UART0_CTS, 0x0a8,
404
+
PIN_FLAG_ONLY_ONE_PULL),
405
+
SG2042_GENERAL_PIN(PIN_UART1_TX, 0x0a8,
406
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
407
+
SG2042_GENERAL_PIN(PIN_UART1_RX, 0x0ac,
408
+
PIN_FLAG_ONLY_ONE_PULL),
409
+
SG2042_GENERAL_PIN(PIN_UART1_RTS, 0x0ac,
410
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
411
+
SG2042_GENERAL_PIN(PIN_UART1_CTS, 0x0b0,
412
+
PIN_FLAG_ONLY_ONE_PULL),
413
+
SG2042_GENERAL_PIN(PIN_UART2_TX, 0x0b0,
414
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
415
+
SG2042_GENERAL_PIN(PIN_UART2_RX, 0x0b4,
416
+
PIN_FLAG_ONLY_ONE_PULL),
417
+
SG2042_GENERAL_PIN(PIN_UART2_RTS, 0x0b4,
418
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
419
+
SG2042_GENERAL_PIN(PIN_UART2_CTS, 0x0b8,
420
+
PIN_FLAG_ONLY_ONE_PULL),
421
+
SG2042_GENERAL_PIN(PIN_UART3_TX, 0x0b8,
422
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
423
+
SG2042_GENERAL_PIN(PIN_UART3_RX, 0x0bc,
424
+
PIN_FLAG_ONLY_ONE_PULL),
425
+
SG2042_GENERAL_PIN(PIN_UART3_RTS, 0x0bc,
426
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
427
+
SG2042_GENERAL_PIN(PIN_UART3_CTS, 0x0c0,
428
+
PIN_FLAG_ONLY_ONE_PULL),
429
+
SG2042_GENERAL_PIN(PIN_SPI0_CS0, 0x0c0,
430
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
431
+
SG2042_GENERAL_PIN(PIN_SPI0_CS1, 0x0c4,
432
+
PIN_FLAG_ONLY_ONE_PULL),
433
+
SG2042_GENERAL_PIN(PIN_SPI0_SDI, 0x0c4,
434
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
435
+
SG2042_GENERAL_PIN(PIN_SPI0_SDO, 0x0c8,
436
+
PIN_FLAG_ONLY_ONE_PULL),
437
+
SG2042_GENERAL_PIN(PIN_SPI0_SCK, 0x0c8,
438
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
439
+
SG2042_GENERAL_PIN(PIN_SPI1_CS0, 0x0cc,
440
+
PIN_FLAG_ONLY_ONE_PULL),
441
+
SG2042_GENERAL_PIN(PIN_SPI1_CS1, 0x0cc,
442
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
443
+
SG2042_GENERAL_PIN(PIN_SPI1_SDI, 0x0d0,
444
+
PIN_FLAG_ONLY_ONE_PULL),
445
+
SG2042_GENERAL_PIN(PIN_SPI1_SDO, 0x0d0,
446
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
447
+
SG2042_GENERAL_PIN(PIN_SPI1_SCK, 0x0d4,
448
+
PIN_FLAG_ONLY_ONE_PULL),
449
+
SG2042_GENERAL_PIN(PIN_JTAG0_TDO, 0x0d4,
450
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
451
+
SG2042_GENERAL_PIN(PIN_JTAG0_TCK, 0x0d8,
452
+
PIN_FLAG_ONLY_ONE_PULL),
453
+
SG2042_GENERAL_PIN(PIN_JTAG0_TDI, 0x0d8,
454
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
455
+
SG2042_GENERAL_PIN(PIN_JTAG0_TMS, 0x0dc,
456
+
PIN_FLAG_ONLY_ONE_PULL),
457
+
SG2042_GENERAL_PIN(PIN_JTAG0_TRST, 0x0dc,
458
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
459
+
SG2042_GENERAL_PIN(PIN_JTAG0_SRST, 0x0e0,
460
+
PIN_FLAG_ONLY_ONE_PULL),
461
+
SG2042_GENERAL_PIN(PIN_JTAG1_TDO, 0x0e0,
462
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
463
+
SG2042_GENERAL_PIN(PIN_JTAG1_TCK, 0x0e4,
464
+
PIN_FLAG_ONLY_ONE_PULL),
465
+
SG2042_GENERAL_PIN(PIN_JTAG1_TDI, 0x0e4,
466
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
467
+
SG2042_GENERAL_PIN(PIN_JTAG1_TMS, 0x0e8,
468
+
PIN_FLAG_ONLY_ONE_PULL),
469
+
SG2042_GENERAL_PIN(PIN_JTAG1_TRST, 0x0e8,
470
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
471
+
SG2042_GENERAL_PIN(PIN_JTAG1_SRST, 0x0ec,
472
+
PIN_FLAG_ONLY_ONE_PULL),
473
+
SG2042_GENERAL_PIN(PIN_JTAG2_TDO, 0x0ec,
474
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
475
+
SG2042_GENERAL_PIN(PIN_JTAG2_TCK, 0x0f0,
476
+
PIN_FLAG_ONLY_ONE_PULL),
477
+
SG2042_GENERAL_PIN(PIN_JTAG2_TDI, 0x0f0,
478
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
479
+
SG2042_GENERAL_PIN(PIN_JTAG2_TMS, 0x0f4,
480
+
PIN_FLAG_ONLY_ONE_PULL),
481
+
SG2042_GENERAL_PIN(PIN_JTAG2_TRST, 0x0f4,
482
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
483
+
SG2042_GENERAL_PIN(PIN_JTAG2_SRST, 0x0f8,
484
+
PIN_FLAG_ONLY_ONE_PULL),
485
+
SG2042_GENERAL_PIN(PIN_GPIO0, 0x0f8,
486
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
487
+
SG2042_GENERAL_PIN(PIN_GPIO1, 0x0fc,
488
+
PIN_FLAG_ONLY_ONE_PULL),
489
+
SG2042_GENERAL_PIN(PIN_GPIO2, 0x0fc,
490
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
491
+
SG2042_GENERAL_PIN(PIN_GPIO3, 0x100,
492
+
PIN_FLAG_ONLY_ONE_PULL),
493
+
SG2042_GENERAL_PIN(PIN_GPIO4, 0x100,
494
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
495
+
SG2042_GENERAL_PIN(PIN_GPIO5, 0x104,
496
+
PIN_FLAG_ONLY_ONE_PULL),
497
+
SG2042_GENERAL_PIN(PIN_GPIO6, 0x104,
498
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
499
+
SG2042_GENERAL_PIN(PIN_GPIO7, 0x108,
500
+
PIN_FLAG_ONLY_ONE_PULL),
501
+
SG2042_GENERAL_PIN(PIN_GPIO8, 0x108,
502
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
503
+
SG2042_GENERAL_PIN(PIN_GPIO9, 0x10c,
504
+
PIN_FLAG_ONLY_ONE_PULL),
505
+
SG2042_GENERAL_PIN(PIN_GPIO10, 0x10c,
506
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
507
+
SG2042_GENERAL_PIN(PIN_GPIO11, 0x110,
508
+
PIN_FLAG_ONLY_ONE_PULL),
509
+
SG2042_GENERAL_PIN(PIN_GPIO12, 0x110,
510
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
511
+
SG2042_GENERAL_PIN(PIN_GPIO13, 0x114,
512
+
PIN_FLAG_ONLY_ONE_PULL),
513
+
SG2042_GENERAL_PIN(PIN_GPIO14, 0x114,
514
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
515
+
SG2042_GENERAL_PIN(PIN_GPIO15, 0x118,
516
+
PIN_FLAG_ONLY_ONE_PULL),
517
+
SG2042_GENERAL_PIN(PIN_GPIO16, 0x118,
518
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
519
+
SG2042_GENERAL_PIN(PIN_GPIO17, 0x11c,
520
+
PIN_FLAG_ONLY_ONE_PULL),
521
+
SG2042_GENERAL_PIN(PIN_GPIO18, 0x11c,
522
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
523
+
SG2042_GENERAL_PIN(PIN_GPIO19, 0x120,
524
+
PIN_FLAG_ONLY_ONE_PULL),
525
+
SG2042_GENERAL_PIN(PIN_GPIO20, 0x120,
526
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
527
+
SG2042_GENERAL_PIN(PIN_GPIO21, 0x124,
528
+
PIN_FLAG_ONLY_ONE_PULL),
529
+
SG2042_GENERAL_PIN(PIN_GPIO22, 0x124,
530
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
531
+
SG2042_GENERAL_PIN(PIN_GPIO23, 0x128,
532
+
PIN_FLAG_ONLY_ONE_PULL),
533
+
SG2042_GENERAL_PIN(PIN_GPIO24, 0x128,
534
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
535
+
SG2042_GENERAL_PIN(PIN_GPIO25, 0x12c,
536
+
PIN_FLAG_ONLY_ONE_PULL),
537
+
SG2042_GENERAL_PIN(PIN_GPIO26, 0x12c,
538
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
539
+
SG2042_GENERAL_PIN(PIN_GPIO27, 0x130,
540
+
PIN_FLAG_ONLY_ONE_PULL),
541
+
SG2042_GENERAL_PIN(PIN_GPIO28, 0x130,
542
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
543
+
SG2042_GENERAL_PIN(PIN_GPIO29, 0x134,
544
+
PIN_FLAG_ONLY_ONE_PULL),
545
+
SG2042_GENERAL_PIN(PIN_GPIO30, 0x134,
546
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
547
+
SG2042_GENERAL_PIN(PIN_GPIO31, 0x138,
548
+
PIN_FLAG_ONLY_ONE_PULL),
549
+
SG2042_GENERAL_PIN(PIN_MODE_SEL0, 0x138,
550
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
551
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
552
+
SG2042_GENERAL_PIN(PIN_MODE_SEL1, 0x13c,
553
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
554
+
PIN_FLAG_NO_OEX_EN),
555
+
SG2042_GENERAL_PIN(PIN_MODE_SEL2, 0x13c,
556
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
557
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
558
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL0, 0x140,
559
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
560
+
PIN_FLAG_NO_OEX_EN),
561
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL1, 0x140,
562
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
563
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
564
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL2, 0x144,
565
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
566
+
PIN_FLAG_NO_OEX_EN),
567
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL3, 0x144,
568
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
569
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
570
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL4, 0x148,
571
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
572
+
PIN_FLAG_NO_OEX_EN),
573
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL5, 0x148,
574
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
575
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
576
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL6, 0x14c,
577
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
578
+
PIN_FLAG_NO_OEX_EN),
579
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL7, 0x14c,
580
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
581
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
582
+
SG2042_GENERAL_PIN(PIN_MULTI_SCKT, 0x150,
583
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
584
+
PIN_FLAG_NO_OEX_EN),
585
+
SG2042_GENERAL_PIN(PIN_SCKT_ID0, 0x150,
586
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
587
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
588
+
SG2042_GENERAL_PIN(PIN_SCKT_ID1, 0x154,
589
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
590
+
PIN_FLAG_NO_OEX_EN),
591
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_MAIN, 0x154,
592
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
593
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
594
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_L, 0x158,
595
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
596
+
PIN_FLAG_NO_OEX_EN),
597
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_R, 0x158,
598
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
599
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
600
+
SG2042_GENERAL_PIN(PIN_XTAL_32K, 0x15c,
601
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
602
+
PIN_FLAG_NO_OEX_EN),
603
+
SG2042_GENERAL_PIN(PIN_SYS_RST, 0x15c,
604
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
605
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
606
+
SG2042_GENERAL_PIN(PIN_PWR_BUTTON, 0x160,
607
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
608
+
PIN_FLAG_NO_OEX_EN),
609
+
SG2042_GENERAL_PIN(PIN_TEST_EN, 0x160,
610
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
611
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
612
+
SG2042_GENERAL_PIN(PIN_TEST_MODE_MBIST, 0x164,
613
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
614
+
PIN_FLAG_NO_OEX_EN),
615
+
SG2042_GENERAL_PIN(PIN_TEST_MODE_SCAN, 0x164,
616
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
617
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
618
+
SG2042_GENERAL_PIN(PIN_TEST_MODE_BSD, 0x168,
619
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
620
+
PIN_FLAG_NO_OEX_EN),
621
+
SG2042_GENERAL_PIN(PIN_BISR_BYP, 0x168,
622
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
623
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
624
+
};
625
+
626
+
static const struct sophgo_pinctrl_data sg2042_pindata = {
627
+
.pins = sg2042_pins,
628
+
.pindata = sg2042_pin_data,
629
+
.vddio_ops = &sg2042_vddio_cfg_ops,
630
+
.cfg_ops = &sg2042_cfg_ops,
631
+
.pctl_ops = &sg2042_pctrl_ops,
632
+
.pmx_ops = &sg2042_pmx_ops,
633
+
.pconf_ops = &sg2042_pconf_ops,
634
+
.npins = ARRAY_SIZE(sg2042_pins),
635
+
.pinsize = sizeof(struct sg2042_pin),
636
+
};
637
+
638
+
static const struct of_device_id sg2042_pinctrl_ids[] = {
639
+
{ .compatible = "sophgo,sg2042-pinctrl", .data = &sg2042_pindata },
640
+
{ }
641
+
};
642
+
MODULE_DEVICE_TABLE(of, sg2042_pinctrl_ids);
643
+
644
+
static struct platform_driver sg2042_pinctrl_driver = {
645
+
.probe = sophgo_pinctrl_probe,
646
+
.driver = {
647
+
.name = "sg2042-pinctrl",
648
+
.suppress_bind_attrs = true,
649
+
.of_match_table = sg2042_pinctrl_ids,
650
+
},
651
+
};
652
+
module_platform_driver(sg2042_pinctrl_driver);
653
+
654
+
MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC");
655
+
MODULE_LICENSE("GPL");
+49
drivers/pinctrl/sophgo/pinctrl-sg2042.h
+49
drivers/pinctrl/sophgo/pinctrl-sg2042.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#ifndef _PINCTRL_SOPHGO_SG2042_H
7
+
#define _PINCTRL_SOPHGO_SG2042_H
8
+
9
+
#include <linux/bits.h>
10
+
#include <linux/bitfield.h>
11
+
#include <linux/device.h>
12
+
#include <linux/mutex.h>
13
+
#include <linux/spinlock.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/pinctrl/pinctrl.h>
16
+
#include <linux/pinctrl/pinconf.h>
17
+
18
+
#include "pinctrl-sophgo.h"
19
+
20
+
#define PIN_FLAG_DEFAULT 0
21
+
#define PIN_FLAG_WRITE_HIGH BIT(0)
22
+
#define PIN_FLAG_ONLY_ONE_PULL BIT(1)
23
+
#define PIN_FLAG_NO_PINMUX BIT(2)
24
+
#define PIN_FLAG_NO_OEX_EN BIT(3)
25
+
#define PIN_FLAG_IS_ETH BIT(4)
26
+
27
+
struct sg2042_pin {
28
+
struct sophgo_pin pin;
29
+
u16 offset;
30
+
};
31
+
32
+
#define sophgo_to_sg2042_pin(_pin) \
33
+
container_of((_pin), struct sg2042_pin, pin)
34
+
35
+
extern const struct pinctrl_ops sg2042_pctrl_ops;
36
+
extern const struct pinmux_ops sg2042_pmx_ops;
37
+
extern const struct pinconf_ops sg2042_pconf_ops;
38
+
extern const struct sophgo_cfg_ops sg2042_cfg_ops;
39
+
40
+
#define SG2042_GENERAL_PIN(_id, _offset, _flag) \
41
+
{ \
42
+
.pin = { \
43
+
.id = (_id), \
44
+
.flags = (_flag), \
45
+
}, \
46
+
.offset = (_offset), \
47
+
}
48
+
49
+
#endif
+718
drivers/pinctrl/sophgo/pinctrl-sg2044.c
+718
drivers/pinctrl/sophgo/pinctrl-sg2044.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo SG2042 SoC pinctrl driver.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*/
7
+
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/of.h>
11
+
12
+
#include <linux/pinctrl/pinctrl.h>
13
+
#include <linux/pinctrl/pinmux.h>
14
+
15
+
#include <dt-bindings/pinctrl/pinctrl-sg2044.h>
16
+
17
+
#include "pinctrl-sg2042.h"
18
+
19
+
static int sg2044_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap)
20
+
{
21
+
return 19500;
22
+
}
23
+
24
+
static int sg2044_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap)
25
+
{
26
+
return 23200;
27
+
}
28
+
29
+
static const u32 sg2044_oc_map[] = {
30
+
3200, 6400, 9600, 12700,
31
+
15900, 19100, 22200, 25300,
32
+
29500, 32700, 35900, 39000,
33
+
42000, 45200, 48300, 51400
34
+
};
35
+
36
+
static int sg2044_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap,
37
+
const u32 **map)
38
+
{
39
+
*map = sg2044_oc_map;
40
+
return ARRAY_SIZE(sg2044_oc_map);
41
+
}
42
+
43
+
static const struct sophgo_vddio_cfg_ops sg2044_vddio_cfg_ops = {
44
+
.get_pull_up = sg2044_get_pull_up,
45
+
.get_pull_down = sg2044_get_pull_down,
46
+
.get_oc_map = sg2044_get_oc_map,
47
+
};
48
+
49
+
static const struct pinctrl_pin_desc sg2044_pins[] = {
50
+
PINCTRL_PIN(PIN_IIC0_SMBSUS_IN, "iic0_smbsus_in"),
51
+
PINCTRL_PIN(PIN_IIC0_SMBSUS_OUT, "iic0_smbsus_out"),
52
+
PINCTRL_PIN(PIN_IIC0_SMBALERT, "iic0_smbalert"),
53
+
PINCTRL_PIN(PIN_IIC1_SMBSUS_IN, "iic1_smbsus_in"),
54
+
PINCTRL_PIN(PIN_IIC1_SMBSUS_OUT, "iic1_smbsus_out"),
55
+
PINCTRL_PIN(PIN_IIC1_SMBALERT, "iic1_smbalert"),
56
+
PINCTRL_PIN(PIN_IIC2_SMBSUS_IN, "iic2_smbsus_in"),
57
+
PINCTRL_PIN(PIN_IIC2_SMBSUS_OUT, "iic2_smbsus_out"),
58
+
PINCTRL_PIN(PIN_IIC2_SMBALERT, "iic2_smbalert"),
59
+
PINCTRL_PIN(PIN_IIC3_SMBSUS_IN, "iic3_smbsus_in"),
60
+
PINCTRL_PIN(PIN_IIC3_SMBSUS_OUT, "iic3_smbsus_out"),
61
+
PINCTRL_PIN(PIN_IIC3_SMBALERT, "iic3_smbalert"),
62
+
PINCTRL_PIN(PIN_PCIE0_L0_RESET, "pcie0_l0_reset"),
63
+
PINCTRL_PIN(PIN_PCIE0_L1_RESET, "pcie0_l1_reset"),
64
+
PINCTRL_PIN(PIN_PCIE0_L0_WAKEUP, "pcie0_l0_wakeup"),
65
+
PINCTRL_PIN(PIN_PCIE0_L1_WAKEUP, "pcie0_l1_wakeup"),
66
+
PINCTRL_PIN(PIN_PCIE0_L0_CLKREQ_IN, "pcie0_l0_clkreq_in"),
67
+
PINCTRL_PIN(PIN_PCIE0_L1_CLKREQ_IN, "pcie0_l1_clkreq_in"),
68
+
PINCTRL_PIN(PIN_PCIE1_L0_RESET, "pcie1_l0_reset"),
69
+
PINCTRL_PIN(PIN_PCIE1_L1_RESET, "pcie1_l1_reset"),
70
+
PINCTRL_PIN(PIN_PCIE1_L0_WAKEUP, "pcie1_l0_wakeup"),
71
+
PINCTRL_PIN(PIN_PCIE1_L1_WAKEUP, "pcie1_l1_wakeup"),
72
+
PINCTRL_PIN(PIN_PCIE1_L0_CLKREQ_IN, "pcie1_l0_clkreq_in"),
73
+
PINCTRL_PIN(PIN_PCIE1_L1_CLKREQ_IN, "pcie1_l1_clkreq_in"),
74
+
PINCTRL_PIN(PIN_PCIE2_L0_RESET, "pcie2_l0_reset"),
75
+
PINCTRL_PIN(PIN_PCIE2_L1_RESET, "pcie2_l1_reset"),
76
+
PINCTRL_PIN(PIN_PCIE2_L0_WAKEUP, "pcie2_l0_wakeup"),
77
+
PINCTRL_PIN(PIN_PCIE2_L1_WAKEUP, "pcie2_l1_wakeup"),
78
+
PINCTRL_PIN(PIN_PCIE2_L0_CLKREQ_IN, "pcie2_l0_clkreq_in"),
79
+
PINCTRL_PIN(PIN_PCIE2_L1_CLKREQ_IN, "pcie2_l1_clkreq_in"),
80
+
PINCTRL_PIN(PIN_PCIE3_L0_RESET, "pcie3_l0_reset"),
81
+
PINCTRL_PIN(PIN_PCIE3_L1_RESET, "pcie3_l1_reset"),
82
+
PINCTRL_PIN(PIN_PCIE3_L0_WAKEUP, "pcie3_l0_wakeup"),
83
+
PINCTRL_PIN(PIN_PCIE3_L1_WAKEUP, "pcie3_l1_wakeup"),
84
+
PINCTRL_PIN(PIN_PCIE3_L0_CLKREQ_IN, "pcie3_l0_clkreq_in"),
85
+
PINCTRL_PIN(PIN_PCIE3_L1_CLKREQ_IN, "pcie3_l1_clkreq_in"),
86
+
PINCTRL_PIN(PIN_PCIE4_L0_RESET, "pcie4_l0_reset"),
87
+
PINCTRL_PIN(PIN_PCIE4_L1_RESET, "pcie4_l1_reset"),
88
+
PINCTRL_PIN(PIN_PCIE4_L0_WAKEUP, "pcie4_l0_wakeup"),
89
+
PINCTRL_PIN(PIN_PCIE4_L1_WAKEUP, "pcie4_l1_wakeup"),
90
+
PINCTRL_PIN(PIN_PCIE4_L0_CLKREQ_IN, "pcie4_l0_clkreq_in"),
91
+
PINCTRL_PIN(PIN_PCIE4_L1_CLKREQ_IN, "pcie4_l1_clkreq_in"),
92
+
PINCTRL_PIN(PIN_SPIF0_CLK_SEL1, "spif0_clk_sel1"),
93
+
PINCTRL_PIN(PIN_SPIF0_CLK_SEL0, "spif0_clk_sel0"),
94
+
PINCTRL_PIN(PIN_SPIF0_WP, "spif0_wp"),
95
+
PINCTRL_PIN(PIN_SPIF0_HOLD, "spif0_hold"),
96
+
PINCTRL_PIN(PIN_SPIF0_SDI, "spif0_sdi"),
97
+
PINCTRL_PIN(PIN_SPIF0_CS, "spif0_cs"),
98
+
PINCTRL_PIN(PIN_SPIF0_SCK, "spif0_sck"),
99
+
PINCTRL_PIN(PIN_SPIF0_SDO, "spif0_sdo"),
100
+
PINCTRL_PIN(PIN_SPIF1_CLK_SEL1, "spif1_clk_sel1"),
101
+
PINCTRL_PIN(PIN_SPIF1_CLK_SEL0, "spif1_clk_sel0"),
102
+
PINCTRL_PIN(PIN_SPIF1_WP, "spif1_wp"),
103
+
PINCTRL_PIN(PIN_SPIF1_HOLD, "spif1_hold"),
104
+
PINCTRL_PIN(PIN_SPIF1_SDI, "spif1_sdi"),
105
+
PINCTRL_PIN(PIN_SPIF1_CS, "spif1_cs"),
106
+
PINCTRL_PIN(PIN_SPIF1_SCK, "spif1_sck"),
107
+
PINCTRL_PIN(PIN_SPIF1_SDO, "spif1_sdo"),
108
+
PINCTRL_PIN(PIN_EMMC_WP, "emmc_wp"),
109
+
PINCTRL_PIN(PIN_EMMC_CD, "emmc_cd"),
110
+
PINCTRL_PIN(PIN_EMMC_RST, "emmc_rst"),
111
+
PINCTRL_PIN(PIN_EMMC_PWR_EN, "emmc_pwr_en"),
112
+
PINCTRL_PIN(PIN_SDIO_CD, "sdio_cd"),
113
+
PINCTRL_PIN(PIN_SDIO_WP, "sdio_wp"),
114
+
PINCTRL_PIN(PIN_SDIO_RST, "sdio_rst"),
115
+
PINCTRL_PIN(PIN_SDIO_PWR_EN, "sdio_pwr_en"),
116
+
PINCTRL_PIN(PIN_RGMII0_TXD0, "rgmii0_txd0"),
117
+
PINCTRL_PIN(PIN_RGMII0_TXD1, "rgmii0_txd1"),
118
+
PINCTRL_PIN(PIN_RGMII0_TXD2, "rgmii0_txd2"),
119
+
PINCTRL_PIN(PIN_RGMII0_TXD3, "rgmii0_txd3"),
120
+
PINCTRL_PIN(PIN_RGMII0_TXCTRL, "rgmii0_txctrl"),
121
+
PINCTRL_PIN(PIN_RGMII0_RXD0, "rgmii0_rxd0"),
122
+
PINCTRL_PIN(PIN_RGMII0_RXD1, "rgmii0_rxd1"),
123
+
PINCTRL_PIN(PIN_RGMII0_RXD2, "rgmii0_rxd2"),
124
+
PINCTRL_PIN(PIN_RGMII0_RXD3, "rgmii0_rxd3"),
125
+
PINCTRL_PIN(PIN_RGMII0_RXCTRL, "rgmii0_rxctrl"),
126
+
PINCTRL_PIN(PIN_RGMII0_TXC, "rgmii0_txc"),
127
+
PINCTRL_PIN(PIN_RGMII0_RXC, "rgmii0_rxc"),
128
+
PINCTRL_PIN(PIN_RGMII0_REFCLKO, "rgmii0_refclko"),
129
+
PINCTRL_PIN(PIN_RGMII0_IRQ, "rgmii0_irq"),
130
+
PINCTRL_PIN(PIN_RGMII0_MDC, "rgmii0_mdc"),
131
+
PINCTRL_PIN(PIN_RGMII0_MDIO, "rgmii0_mdio"),
132
+
PINCTRL_PIN(PIN_PWM0, "pwm0"),
133
+
PINCTRL_PIN(PIN_PWM1, "pwm1"),
134
+
PINCTRL_PIN(PIN_PWM2, "pwm2"),
135
+
PINCTRL_PIN(PIN_PWM3, "pwm3"),
136
+
PINCTRL_PIN(PIN_FAN0, "fan0"),
137
+
PINCTRL_PIN(PIN_FAN1, "fan1"),
138
+
PINCTRL_PIN(PIN_FAN2, "fan2"),
139
+
PINCTRL_PIN(PIN_FAN3, "fan3"),
140
+
PINCTRL_PIN(PIN_IIC0_SDA, "iic0_sda"),
141
+
PINCTRL_PIN(PIN_IIC0_SCL, "iic0_scl"),
142
+
PINCTRL_PIN(PIN_IIC1_SDA, "iic1_sda"),
143
+
PINCTRL_PIN(PIN_IIC1_SCL, "iic1_scl"),
144
+
PINCTRL_PIN(PIN_IIC2_SDA, "iic2_sda"),
145
+
PINCTRL_PIN(PIN_IIC2_SCL, "iic2_scl"),
146
+
PINCTRL_PIN(PIN_IIC3_SDA, "iic3_sda"),
147
+
PINCTRL_PIN(PIN_IIC3_SCL, "iic3_scl"),
148
+
PINCTRL_PIN(PIN_UART0_TX, "uart0_tx"),
149
+
PINCTRL_PIN(PIN_UART0_RX, "uart0_rx"),
150
+
PINCTRL_PIN(PIN_UART0_RTS, "uart0_rts"),
151
+
PINCTRL_PIN(PIN_UART0_CTS, "uart0_cts"),
152
+
PINCTRL_PIN(PIN_UART1_TX, "uart1_tx"),
153
+
PINCTRL_PIN(PIN_UART1_RX, "uart1_rx"),
154
+
PINCTRL_PIN(PIN_UART1_RTS, "uart1_rts"),
155
+
PINCTRL_PIN(PIN_UART1_CTS, "uart1_cts"),
156
+
PINCTRL_PIN(PIN_UART2_TX, "uart2_tx"),
157
+
PINCTRL_PIN(PIN_UART2_RX, "uart2_rx"),
158
+
PINCTRL_PIN(PIN_UART2_RTS, "uart2_rts"),
159
+
PINCTRL_PIN(PIN_UART2_CTS, "uart2_cts"),
160
+
PINCTRL_PIN(PIN_UART3_TX, "uart3_tx"),
161
+
PINCTRL_PIN(PIN_UART3_RX, "uart3_rx"),
162
+
PINCTRL_PIN(PIN_UART3_RTS, "uart3_rts"),
163
+
PINCTRL_PIN(PIN_UART3_CTS, "uart3_cts"),
164
+
PINCTRL_PIN(PIN_SPI0_CS0, "spi0_cs0"),
165
+
PINCTRL_PIN(PIN_SPI0_CS1, "spi0_cs1"),
166
+
PINCTRL_PIN(PIN_SPI0_SDI, "spi0_sdi"),
167
+
PINCTRL_PIN(PIN_SPI0_SDO, "spi0_sdo"),
168
+
PINCTRL_PIN(PIN_SPI0_SCK, "spi0_sck"),
169
+
PINCTRL_PIN(PIN_SPI1_CS0, "spi1_cs0"),
170
+
PINCTRL_PIN(PIN_SPI1_CS1, "spi1_cs1"),
171
+
PINCTRL_PIN(PIN_SPI1_SDI, "spi1_sdi"),
172
+
PINCTRL_PIN(PIN_SPI1_SDO, "spi1_sdo"),
173
+
PINCTRL_PIN(PIN_SPI1_SCK, "spi1_sck"),
174
+
PINCTRL_PIN(PIN_JTAG0_TDO, "jtag0_tdo"),
175
+
PINCTRL_PIN(PIN_JTAG0_TCK, "jtag0_tck"),
176
+
PINCTRL_PIN(PIN_JTAG0_TDI, "jtag0_tdi"),
177
+
PINCTRL_PIN(PIN_JTAG0_TMS, "jtag0_tms"),
178
+
PINCTRL_PIN(PIN_JTAG0_TRST, "jtag0_trst"),
179
+
PINCTRL_PIN(PIN_JTAG0_SRST, "jtag0_srst"),
180
+
PINCTRL_PIN(PIN_JTAG1_TDO, "jtag1_tdo"),
181
+
PINCTRL_PIN(PIN_JTAG1_TCK, "jtag1_tck"),
182
+
PINCTRL_PIN(PIN_JTAG1_TDI, "jtag1_tdi"),
183
+
PINCTRL_PIN(PIN_JTAG1_TMS, "jtag1_tms"),
184
+
PINCTRL_PIN(PIN_JTAG1_TRST, "jtag1_trst"),
185
+
PINCTRL_PIN(PIN_JTAG1_SRST, "jtag1_srst"),
186
+
PINCTRL_PIN(PIN_JTAG2_TDO, "jtag2_tdo"),
187
+
PINCTRL_PIN(PIN_JTAG2_TCK, "jtag2_tck"),
188
+
PINCTRL_PIN(PIN_JTAG2_TDI, "jtag2_tdi"),
189
+
PINCTRL_PIN(PIN_JTAG2_TMS, "jtag2_tms"),
190
+
PINCTRL_PIN(PIN_JTAG2_TRST, "jtag2_trst"),
191
+
PINCTRL_PIN(PIN_JTAG2_SRST, "jtag2_srst"),
192
+
PINCTRL_PIN(PIN_JTAG3_TDO, "jtag3_tdo"),
193
+
PINCTRL_PIN(PIN_JTAG3_TCK, "jtag3_tck"),
194
+
PINCTRL_PIN(PIN_JTAG3_TDI, "jtag3_tdi"),
195
+
PINCTRL_PIN(PIN_JTAG3_TMS, "jtag3_tms"),
196
+
PINCTRL_PIN(PIN_JTAG3_TRST, "jtag3_trst"),
197
+
PINCTRL_PIN(PIN_JTAG3_SRST, "jtag3_srst"),
198
+
PINCTRL_PIN(PIN_GPIO0, "gpio0"),
199
+
PINCTRL_PIN(PIN_GPIO1, "gpio1"),
200
+
PINCTRL_PIN(PIN_GPIO2, "gpio2"),
201
+
PINCTRL_PIN(PIN_GPIO3, "gpio3"),
202
+
PINCTRL_PIN(PIN_GPIO4, "gpio4"),
203
+
PINCTRL_PIN(PIN_GPIO5, "gpio5"),
204
+
PINCTRL_PIN(PIN_GPIO6, "gpio6"),
205
+
PINCTRL_PIN(PIN_GPIO7, "gpio7"),
206
+
PINCTRL_PIN(PIN_GPIO8, "gpio8"),
207
+
PINCTRL_PIN(PIN_GPIO9, "gpio9"),
208
+
PINCTRL_PIN(PIN_GPIO10, "gpio10"),
209
+
PINCTRL_PIN(PIN_GPIO11, "gpio11"),
210
+
PINCTRL_PIN(PIN_GPIO12, "gpio12"),
211
+
PINCTRL_PIN(PIN_GPIO13, "gpio13"),
212
+
PINCTRL_PIN(PIN_GPIO14, "gpio14"),
213
+
PINCTRL_PIN(PIN_GPIO15, "gpio15"),
214
+
PINCTRL_PIN(PIN_GPIO16, "gpio16"),
215
+
PINCTRL_PIN(PIN_GPIO17, "gpio17"),
216
+
PINCTRL_PIN(PIN_GPIO18, "gpio18"),
217
+
PINCTRL_PIN(PIN_GPIO19, "gpio19"),
218
+
PINCTRL_PIN(PIN_GPIO20, "gpio20"),
219
+
PINCTRL_PIN(PIN_GPIO21, "gpio21"),
220
+
PINCTRL_PIN(PIN_GPIO22, "gpio22"),
221
+
PINCTRL_PIN(PIN_GPIO23, "gpio23"),
222
+
PINCTRL_PIN(PIN_GPIO24, "gpio24"),
223
+
PINCTRL_PIN(PIN_GPIO25, "gpio25"),
224
+
PINCTRL_PIN(PIN_GPIO26, "gpio26"),
225
+
PINCTRL_PIN(PIN_GPIO27, "gpio27"),
226
+
PINCTRL_PIN(PIN_GPIO28, "gpio28"),
227
+
PINCTRL_PIN(PIN_GPIO29, "gpio29"),
228
+
PINCTRL_PIN(PIN_GPIO30, "gpio30"),
229
+
PINCTRL_PIN(PIN_GPIO31, "gpio31"),
230
+
PINCTRL_PIN(PIN_MODE_SEL0, "mode_sel0"),
231
+
PINCTRL_PIN(PIN_MODE_SEL1, "mode_sel1"),
232
+
PINCTRL_PIN(PIN_MODE_SEL2, "mode_sel2"),
233
+
PINCTRL_PIN(PIN_BOOT_SEL0, "boot_sel0"),
234
+
PINCTRL_PIN(PIN_BOOT_SEL1, "boot_sel1"),
235
+
PINCTRL_PIN(PIN_BOOT_SEL2, "boot_sel2"),
236
+
PINCTRL_PIN(PIN_BOOT_SEL3, "boot_sel3"),
237
+
PINCTRL_PIN(PIN_BOOT_SEL4, "boot_sel4"),
238
+
PINCTRL_PIN(PIN_BOOT_SEL5, "boot_sel5"),
239
+
PINCTRL_PIN(PIN_BOOT_SEL6, "boot_sel6"),
240
+
PINCTRL_PIN(PIN_BOOT_SEL7, "boot_sel7"),
241
+
PINCTRL_PIN(PIN_MULTI_SCKT, "multi_sckt"),
242
+
PINCTRL_PIN(PIN_SCKT_ID0, "sckt_id0"),
243
+
PINCTRL_PIN(PIN_SCKT_ID1, "sckt_id1"),
244
+
PINCTRL_PIN(PIN_PLL_CLK_IN_MAIN, "pll_clk_in_main"),
245
+
PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_0, "pll_clk_in_ddr_0"),
246
+
PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_1, "pll_clk_in_ddr_1"),
247
+
PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_2, "pll_clk_in_ddr_2"),
248
+
PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_3, "pll_clk_in_ddr_3"),
249
+
PINCTRL_PIN(PIN_XTAL_32K, "xtal_32k"),
250
+
PINCTRL_PIN(PIN_SYS_RST, "sys_rst"),
251
+
PINCTRL_PIN(PIN_PWR_BUTTON, "pwr_button"),
252
+
PINCTRL_PIN(PIN_TEST_EN, "test_en"),
253
+
PINCTRL_PIN(PIN_TEST_MODE_MBIST, "test_mode_mbist"),
254
+
PINCTRL_PIN(PIN_TEST_MODE_SCAN, "test_mode_scan"),
255
+
PINCTRL_PIN(PIN_TEST_MODE_BSD, "test_mode_bsd"),
256
+
PINCTRL_PIN(PIN_BISR_BYP, "bisr_byp"),
257
+
};
258
+
259
+
static const struct sg2042_pin sg2044_pin_data[ARRAY_SIZE(sg2044_pins)] = {
260
+
SG2042_GENERAL_PIN(PIN_IIC0_SMBSUS_IN, 0x000,
261
+
PIN_FLAG_DEFAULT),
262
+
SG2042_GENERAL_PIN(PIN_IIC0_SMBSUS_OUT, 0x000,
263
+
PIN_FLAG_WRITE_HIGH),
264
+
SG2042_GENERAL_PIN(PIN_IIC0_SMBALERT, 0x004,
265
+
PIN_FLAG_DEFAULT),
266
+
SG2042_GENERAL_PIN(PIN_IIC1_SMBSUS_IN, 0x004,
267
+
PIN_FLAG_WRITE_HIGH),
268
+
SG2042_GENERAL_PIN(PIN_IIC1_SMBSUS_OUT, 0x008,
269
+
PIN_FLAG_DEFAULT),
270
+
SG2042_GENERAL_PIN(PIN_IIC1_SMBALERT, 0x008,
271
+
PIN_FLAG_WRITE_HIGH),
272
+
SG2042_GENERAL_PIN(PIN_IIC2_SMBSUS_IN, 0x00c,
273
+
PIN_FLAG_DEFAULT),
274
+
SG2042_GENERAL_PIN(PIN_IIC2_SMBSUS_OUT, 0x00c,
275
+
PIN_FLAG_WRITE_HIGH),
276
+
SG2042_GENERAL_PIN(PIN_IIC2_SMBALERT, 0x010,
277
+
PIN_FLAG_DEFAULT),
278
+
SG2042_GENERAL_PIN(PIN_IIC3_SMBSUS_IN, 0x010,
279
+
PIN_FLAG_WRITE_HIGH),
280
+
SG2042_GENERAL_PIN(PIN_IIC3_SMBSUS_OUT, 0x014,
281
+
PIN_FLAG_DEFAULT),
282
+
SG2042_GENERAL_PIN(PIN_IIC3_SMBALERT, 0x014,
283
+
PIN_FLAG_WRITE_HIGH),
284
+
SG2042_GENERAL_PIN(PIN_PCIE0_L0_RESET, 0x018,
285
+
PIN_FLAG_DEFAULT),
286
+
SG2042_GENERAL_PIN(PIN_PCIE0_L1_RESET, 0x018,
287
+
PIN_FLAG_WRITE_HIGH),
288
+
SG2042_GENERAL_PIN(PIN_PCIE0_L0_WAKEUP, 0x01c,
289
+
PIN_FLAG_DEFAULT),
290
+
SG2042_GENERAL_PIN(PIN_PCIE0_L1_WAKEUP, 0x01c,
291
+
PIN_FLAG_WRITE_HIGH),
292
+
SG2042_GENERAL_PIN(PIN_PCIE0_L0_CLKREQ_IN, 0x020,
293
+
PIN_FLAG_DEFAULT),
294
+
SG2042_GENERAL_PIN(PIN_PCIE0_L1_CLKREQ_IN, 0x020,
295
+
PIN_FLAG_WRITE_HIGH),
296
+
SG2042_GENERAL_PIN(PIN_PCIE1_L0_RESET, 0x024,
297
+
PIN_FLAG_DEFAULT),
298
+
SG2042_GENERAL_PIN(PIN_PCIE1_L1_RESET, 0x024,
299
+
PIN_FLAG_WRITE_HIGH),
300
+
SG2042_GENERAL_PIN(PIN_PCIE1_L0_WAKEUP, 0x028,
301
+
PIN_FLAG_DEFAULT),
302
+
SG2042_GENERAL_PIN(PIN_PCIE1_L1_WAKEUP, 0x028,
303
+
PIN_FLAG_WRITE_HIGH),
304
+
SG2042_GENERAL_PIN(PIN_PCIE1_L0_CLKREQ_IN, 0x02c,
305
+
PIN_FLAG_DEFAULT),
306
+
SG2042_GENERAL_PIN(PIN_PCIE1_L1_CLKREQ_IN, 0x02c,
307
+
PIN_FLAG_WRITE_HIGH),
308
+
SG2042_GENERAL_PIN(PIN_PCIE2_L0_RESET, 0x030,
309
+
PIN_FLAG_DEFAULT),
310
+
SG2042_GENERAL_PIN(PIN_PCIE2_L1_RESET, 0x030,
311
+
PIN_FLAG_WRITE_HIGH),
312
+
SG2042_GENERAL_PIN(PIN_PCIE2_L0_WAKEUP, 0x034,
313
+
PIN_FLAG_DEFAULT),
314
+
SG2042_GENERAL_PIN(PIN_PCIE2_L1_WAKEUP, 0x034,
315
+
PIN_FLAG_WRITE_HIGH),
316
+
SG2042_GENERAL_PIN(PIN_PCIE2_L0_CLKREQ_IN, 0x038,
317
+
PIN_FLAG_DEFAULT),
318
+
SG2042_GENERAL_PIN(PIN_PCIE2_L1_CLKREQ_IN, 0x038,
319
+
PIN_FLAG_WRITE_HIGH),
320
+
SG2042_GENERAL_PIN(PIN_PCIE3_L0_RESET, 0x03c,
321
+
PIN_FLAG_DEFAULT),
322
+
SG2042_GENERAL_PIN(PIN_PCIE3_L1_RESET, 0x03c,
323
+
PIN_FLAG_WRITE_HIGH),
324
+
SG2042_GENERAL_PIN(PIN_PCIE3_L0_WAKEUP, 0x040,
325
+
PIN_FLAG_DEFAULT),
326
+
SG2042_GENERAL_PIN(PIN_PCIE3_L1_WAKEUP, 0x040,
327
+
PIN_FLAG_WRITE_HIGH),
328
+
SG2042_GENERAL_PIN(PIN_PCIE3_L0_CLKREQ_IN, 0x044,
329
+
PIN_FLAG_DEFAULT),
330
+
SG2042_GENERAL_PIN(PIN_PCIE3_L1_CLKREQ_IN, 0x044,
331
+
PIN_FLAG_WRITE_HIGH),
332
+
SG2042_GENERAL_PIN(PIN_PCIE4_L0_RESET, 0x048,
333
+
PIN_FLAG_DEFAULT),
334
+
SG2042_GENERAL_PIN(PIN_PCIE4_L1_RESET, 0x048,
335
+
PIN_FLAG_WRITE_HIGH),
336
+
SG2042_GENERAL_PIN(PIN_PCIE4_L0_WAKEUP, 0x04c,
337
+
PIN_FLAG_DEFAULT),
338
+
SG2042_GENERAL_PIN(PIN_PCIE4_L1_WAKEUP, 0x04c,
339
+
PIN_FLAG_WRITE_HIGH),
340
+
SG2042_GENERAL_PIN(PIN_PCIE4_L0_CLKREQ_IN, 0x050,
341
+
PIN_FLAG_DEFAULT),
342
+
SG2042_GENERAL_PIN(PIN_PCIE4_L1_CLKREQ_IN, 0x050,
343
+
PIN_FLAG_WRITE_HIGH),
344
+
SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL1, 0x054,
345
+
PIN_FLAG_DEFAULT),
346
+
SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL0, 0x054,
347
+
PIN_FLAG_WRITE_HIGH),
348
+
SG2042_GENERAL_PIN(PIN_SPIF0_WP, 0x058,
349
+
PIN_FLAG_DEFAULT),
350
+
SG2042_GENERAL_PIN(PIN_SPIF0_HOLD, 0x058,
351
+
PIN_FLAG_WRITE_HIGH),
352
+
SG2042_GENERAL_PIN(PIN_SPIF0_SDI, 0x05c,
353
+
PIN_FLAG_DEFAULT),
354
+
SG2042_GENERAL_PIN(PIN_SPIF0_CS, 0x05c,
355
+
PIN_FLAG_WRITE_HIGH),
356
+
SG2042_GENERAL_PIN(PIN_SPIF0_SCK, 0x060,
357
+
PIN_FLAG_DEFAULT),
358
+
SG2042_GENERAL_PIN(PIN_SPIF0_SDO, 0x060,
359
+
PIN_FLAG_WRITE_HIGH),
360
+
SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL1, 0x064,
361
+
PIN_FLAG_DEFAULT),
362
+
SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL0, 0x064,
363
+
PIN_FLAG_WRITE_HIGH),
364
+
SG2042_GENERAL_PIN(PIN_SPIF1_WP, 0x068,
365
+
PIN_FLAG_DEFAULT),
366
+
SG2042_GENERAL_PIN(PIN_SPIF1_HOLD, 0x068,
367
+
PIN_FLAG_WRITE_HIGH),
368
+
SG2042_GENERAL_PIN(PIN_SPIF1_SDI, 0x06c,
369
+
PIN_FLAG_DEFAULT),
370
+
SG2042_GENERAL_PIN(PIN_SPIF1_CS, 0x06c,
371
+
PIN_FLAG_WRITE_HIGH),
372
+
SG2042_GENERAL_PIN(PIN_SPIF1_SCK, 0x070,
373
+
PIN_FLAG_DEFAULT),
374
+
SG2042_GENERAL_PIN(PIN_SPIF1_SDO, 0x070,
375
+
PIN_FLAG_WRITE_HIGH),
376
+
SG2042_GENERAL_PIN(PIN_EMMC_WP, 0x074,
377
+
PIN_FLAG_DEFAULT),
378
+
SG2042_GENERAL_PIN(PIN_EMMC_CD, 0x074,
379
+
PIN_FLAG_WRITE_HIGH),
380
+
SG2042_GENERAL_PIN(PIN_EMMC_RST, 0x078,
381
+
PIN_FLAG_DEFAULT),
382
+
SG2042_GENERAL_PIN(PIN_EMMC_PWR_EN, 0x078,
383
+
PIN_FLAG_WRITE_HIGH),
384
+
SG2042_GENERAL_PIN(PIN_SDIO_CD, 0x07c,
385
+
PIN_FLAG_DEFAULT),
386
+
SG2042_GENERAL_PIN(PIN_SDIO_WP, 0x07c,
387
+
PIN_FLAG_WRITE_HIGH),
388
+
SG2042_GENERAL_PIN(PIN_SDIO_RST, 0x080,
389
+
PIN_FLAG_DEFAULT),
390
+
SG2042_GENERAL_PIN(PIN_SDIO_PWR_EN, 0x080,
391
+
PIN_FLAG_WRITE_HIGH),
392
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD0, 0x084,
393
+
PIN_FLAG_DEFAULT),
394
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD1, 0x084,
395
+
PIN_FLAG_WRITE_HIGH),
396
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD2, 0x088,
397
+
PIN_FLAG_DEFAULT),
398
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD3, 0x088,
399
+
PIN_FLAG_WRITE_HIGH),
400
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXCTRL, 0x08c,
401
+
PIN_FLAG_DEFAULT),
402
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD0, 0x08c,
403
+
PIN_FLAG_WRITE_HIGH),
404
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD1, 0x090,
405
+
PIN_FLAG_DEFAULT),
406
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD2, 0x090,
407
+
PIN_FLAG_WRITE_HIGH),
408
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD3, 0x094,
409
+
PIN_FLAG_DEFAULT),
410
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXCTRL, 0x094,
411
+
PIN_FLAG_WRITE_HIGH),
412
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXC, 0x098,
413
+
PIN_FLAG_DEFAULT),
414
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXC, 0x098,
415
+
PIN_FLAG_WRITE_HIGH),
416
+
SG2042_GENERAL_PIN(PIN_RGMII0_REFCLKO, 0x09c,
417
+
PIN_FLAG_DEFAULT),
418
+
SG2042_GENERAL_PIN(PIN_RGMII0_IRQ, 0x09c,
419
+
PIN_FLAG_WRITE_HIGH),
420
+
SG2042_GENERAL_PIN(PIN_RGMII0_MDC, 0x0a0,
421
+
PIN_FLAG_DEFAULT),
422
+
SG2042_GENERAL_PIN(PIN_RGMII0_MDIO, 0x0a0,
423
+
PIN_FLAG_WRITE_HIGH),
424
+
SG2042_GENERAL_PIN(PIN_PWM0, 0x0a4,
425
+
PIN_FLAG_DEFAULT),
426
+
SG2042_GENERAL_PIN(PIN_PWM1, 0x0a4,
427
+
PIN_FLAG_WRITE_HIGH),
428
+
SG2042_GENERAL_PIN(PIN_PWM2, 0x0a8,
429
+
PIN_FLAG_DEFAULT),
430
+
SG2042_GENERAL_PIN(PIN_PWM3, 0x0a8,
431
+
PIN_FLAG_WRITE_HIGH),
432
+
SG2042_GENERAL_PIN(PIN_FAN0, 0x0ac,
433
+
PIN_FLAG_DEFAULT),
434
+
SG2042_GENERAL_PIN(PIN_FAN1, 0x0ac,
435
+
PIN_FLAG_WRITE_HIGH),
436
+
SG2042_GENERAL_PIN(PIN_FAN2, 0x0b0,
437
+
PIN_FLAG_DEFAULT),
438
+
SG2042_GENERAL_PIN(PIN_FAN3, 0x0b0,
439
+
PIN_FLAG_WRITE_HIGH),
440
+
SG2042_GENERAL_PIN(PIN_IIC0_SDA, 0x0b4,
441
+
PIN_FLAG_DEFAULT),
442
+
SG2042_GENERAL_PIN(PIN_IIC0_SCL, 0x0b4,
443
+
PIN_FLAG_WRITE_HIGH),
444
+
SG2042_GENERAL_PIN(PIN_IIC1_SDA, 0x0b8,
445
+
PIN_FLAG_DEFAULT),
446
+
SG2042_GENERAL_PIN(PIN_IIC1_SCL, 0x0b8,
447
+
PIN_FLAG_WRITE_HIGH),
448
+
SG2042_GENERAL_PIN(PIN_IIC2_SDA, 0x0bc,
449
+
PIN_FLAG_DEFAULT),
450
+
SG2042_GENERAL_PIN(PIN_IIC2_SCL, 0x0bc,
451
+
PIN_FLAG_WRITE_HIGH),
452
+
SG2042_GENERAL_PIN(PIN_IIC3_SDA, 0x0c0,
453
+
PIN_FLAG_DEFAULT),
454
+
SG2042_GENERAL_PIN(PIN_IIC3_SCL, 0x0c0,
455
+
PIN_FLAG_WRITE_HIGH),
456
+
SG2042_GENERAL_PIN(PIN_UART0_TX, 0x0c4,
457
+
PIN_FLAG_DEFAULT),
458
+
SG2042_GENERAL_PIN(PIN_UART0_RX, 0x0c4,
459
+
PIN_FLAG_WRITE_HIGH),
460
+
SG2042_GENERAL_PIN(PIN_UART0_RTS, 0x0c8,
461
+
PIN_FLAG_DEFAULT),
462
+
SG2042_GENERAL_PIN(PIN_UART0_CTS, 0x0c8,
463
+
PIN_FLAG_WRITE_HIGH),
464
+
SG2042_GENERAL_PIN(PIN_UART1_TX, 0x0cc,
465
+
PIN_FLAG_DEFAULT),
466
+
SG2042_GENERAL_PIN(PIN_UART1_RX, 0x0cc,
467
+
PIN_FLAG_WRITE_HIGH),
468
+
SG2042_GENERAL_PIN(PIN_UART1_RTS, 0x0d0,
469
+
PIN_FLAG_DEFAULT),
470
+
SG2042_GENERAL_PIN(PIN_UART1_CTS, 0x0d0,
471
+
PIN_FLAG_WRITE_HIGH),
472
+
SG2042_GENERAL_PIN(PIN_UART2_TX, 0x0d4,
473
+
PIN_FLAG_DEFAULT),
474
+
SG2042_GENERAL_PIN(PIN_UART2_RX, 0x0d4,
475
+
PIN_FLAG_WRITE_HIGH),
476
+
SG2042_GENERAL_PIN(PIN_UART2_RTS, 0x0d8,
477
+
PIN_FLAG_DEFAULT),
478
+
SG2042_GENERAL_PIN(PIN_UART2_CTS, 0x0d8,
479
+
PIN_FLAG_WRITE_HIGH),
480
+
SG2042_GENERAL_PIN(PIN_UART3_TX, 0x0dc,
481
+
PIN_FLAG_DEFAULT),
482
+
SG2042_GENERAL_PIN(PIN_UART3_RX, 0x0dc,
483
+
PIN_FLAG_WRITE_HIGH),
484
+
SG2042_GENERAL_PIN(PIN_UART3_RTS, 0x0e0,
485
+
PIN_FLAG_DEFAULT),
486
+
SG2042_GENERAL_PIN(PIN_UART3_CTS, 0x0e0,
487
+
PIN_FLAG_WRITE_HIGH),
488
+
SG2042_GENERAL_PIN(PIN_SPI0_CS0, 0x0e4,
489
+
PIN_FLAG_DEFAULT),
490
+
SG2042_GENERAL_PIN(PIN_SPI0_CS1, 0x0e4,
491
+
PIN_FLAG_WRITE_HIGH),
492
+
SG2042_GENERAL_PIN(PIN_SPI0_SDI, 0x0e8,
493
+
PIN_FLAG_DEFAULT),
494
+
SG2042_GENERAL_PIN(PIN_SPI0_SDO, 0x0e8,
495
+
PIN_FLAG_WRITE_HIGH),
496
+
SG2042_GENERAL_PIN(PIN_SPI0_SCK, 0x0ec,
497
+
PIN_FLAG_DEFAULT),
498
+
SG2042_GENERAL_PIN(PIN_SPI1_CS0, 0x0ec,
499
+
PIN_FLAG_WRITE_HIGH),
500
+
SG2042_GENERAL_PIN(PIN_SPI1_CS1, 0x0f0,
501
+
PIN_FLAG_DEFAULT),
502
+
SG2042_GENERAL_PIN(PIN_SPI1_SDI, 0x0f0,
503
+
PIN_FLAG_WRITE_HIGH),
504
+
SG2042_GENERAL_PIN(PIN_SPI1_SDO, 0x0f4,
505
+
PIN_FLAG_DEFAULT),
506
+
SG2042_GENERAL_PIN(PIN_SPI1_SCK, 0x0f4,
507
+
PIN_FLAG_WRITE_HIGH),
508
+
SG2042_GENERAL_PIN(PIN_JTAG0_TDO, 0x0f8,
509
+
PIN_FLAG_DEFAULT),
510
+
SG2042_GENERAL_PIN(PIN_JTAG0_TCK, 0x0f8,
511
+
PIN_FLAG_WRITE_HIGH),
512
+
SG2042_GENERAL_PIN(PIN_JTAG0_TDI, 0x0fc,
513
+
PIN_FLAG_DEFAULT),
514
+
SG2042_GENERAL_PIN(PIN_JTAG0_TMS, 0x0fc,
515
+
PIN_FLAG_WRITE_HIGH),
516
+
SG2042_GENERAL_PIN(PIN_JTAG0_TRST, 0x100,
517
+
PIN_FLAG_DEFAULT),
518
+
SG2042_GENERAL_PIN(PIN_JTAG0_SRST, 0x100,
519
+
PIN_FLAG_WRITE_HIGH),
520
+
SG2042_GENERAL_PIN(PIN_JTAG1_TDO, 0x104,
521
+
PIN_FLAG_DEFAULT),
522
+
SG2042_GENERAL_PIN(PIN_JTAG1_TCK, 0x104,
523
+
PIN_FLAG_WRITE_HIGH),
524
+
SG2042_GENERAL_PIN(PIN_JTAG1_TDI, 0x108,
525
+
PIN_FLAG_DEFAULT),
526
+
SG2042_GENERAL_PIN(PIN_JTAG1_TMS, 0x108,
527
+
PIN_FLAG_WRITE_HIGH),
528
+
SG2042_GENERAL_PIN(PIN_JTAG1_TRST, 0x10c,
529
+
PIN_FLAG_DEFAULT),
530
+
SG2042_GENERAL_PIN(PIN_JTAG1_SRST, 0x10c,
531
+
PIN_FLAG_WRITE_HIGH),
532
+
SG2042_GENERAL_PIN(PIN_JTAG2_TDO, 0x110,
533
+
PIN_FLAG_DEFAULT),
534
+
SG2042_GENERAL_PIN(PIN_JTAG2_TCK, 0x110,
535
+
PIN_FLAG_WRITE_HIGH),
536
+
SG2042_GENERAL_PIN(PIN_JTAG2_TDI, 0x114,
537
+
PIN_FLAG_DEFAULT),
538
+
SG2042_GENERAL_PIN(PIN_JTAG2_TMS, 0x114,
539
+
PIN_FLAG_WRITE_HIGH),
540
+
SG2042_GENERAL_PIN(PIN_JTAG2_TRST, 0x118,
541
+
PIN_FLAG_DEFAULT),
542
+
SG2042_GENERAL_PIN(PIN_JTAG2_SRST, 0x118,
543
+
PIN_FLAG_WRITE_HIGH),
544
+
SG2042_GENERAL_PIN(PIN_JTAG3_TDO, 0x11c,
545
+
PIN_FLAG_DEFAULT),
546
+
SG2042_GENERAL_PIN(PIN_JTAG3_TCK, 0x11c,
547
+
PIN_FLAG_WRITE_HIGH),
548
+
SG2042_GENERAL_PIN(PIN_JTAG3_TDI, 0x120,
549
+
PIN_FLAG_DEFAULT),
550
+
SG2042_GENERAL_PIN(PIN_JTAG3_TMS, 0x120,
551
+
PIN_FLAG_WRITE_HIGH),
552
+
SG2042_GENERAL_PIN(PIN_JTAG3_TRST, 0x124,
553
+
PIN_FLAG_DEFAULT),
554
+
SG2042_GENERAL_PIN(PIN_JTAG3_SRST, 0x124,
555
+
PIN_FLAG_WRITE_HIGH),
556
+
SG2042_GENERAL_PIN(PIN_GPIO0, 0x128,
557
+
PIN_FLAG_DEFAULT),
558
+
SG2042_GENERAL_PIN(PIN_GPIO1, 0x128,
559
+
PIN_FLAG_WRITE_HIGH),
560
+
SG2042_GENERAL_PIN(PIN_GPIO2, 0x12c,
561
+
PIN_FLAG_DEFAULT),
562
+
SG2042_GENERAL_PIN(PIN_GPIO3, 0x12c,
563
+
PIN_FLAG_WRITE_HIGH),
564
+
SG2042_GENERAL_PIN(PIN_GPIO4, 0x130,
565
+
PIN_FLAG_DEFAULT),
566
+
SG2042_GENERAL_PIN(PIN_GPIO5, 0x130,
567
+
PIN_FLAG_WRITE_HIGH),
568
+
SG2042_GENERAL_PIN(PIN_GPIO6, 0x134,
569
+
PIN_FLAG_DEFAULT),
570
+
SG2042_GENERAL_PIN(PIN_GPIO7, 0x134,
571
+
PIN_FLAG_WRITE_HIGH),
572
+
SG2042_GENERAL_PIN(PIN_GPIO8, 0x138,
573
+
PIN_FLAG_DEFAULT),
574
+
SG2042_GENERAL_PIN(PIN_GPIO9, 0x138,
575
+
PIN_FLAG_WRITE_HIGH),
576
+
SG2042_GENERAL_PIN(PIN_GPIO10, 0x13c,
577
+
PIN_FLAG_DEFAULT),
578
+
SG2042_GENERAL_PIN(PIN_GPIO11, 0x13c,
579
+
PIN_FLAG_WRITE_HIGH),
580
+
SG2042_GENERAL_PIN(PIN_GPIO12, 0x140,
581
+
PIN_FLAG_DEFAULT),
582
+
SG2042_GENERAL_PIN(PIN_GPIO13, 0x140,
583
+
PIN_FLAG_WRITE_HIGH),
584
+
SG2042_GENERAL_PIN(PIN_GPIO14, 0x144,
585
+
PIN_FLAG_DEFAULT),
586
+
SG2042_GENERAL_PIN(PIN_GPIO15, 0x144,
587
+
PIN_FLAG_WRITE_HIGH),
588
+
SG2042_GENERAL_PIN(PIN_GPIO16, 0x148,
589
+
PIN_FLAG_DEFAULT),
590
+
SG2042_GENERAL_PIN(PIN_GPIO17, 0x148,
591
+
PIN_FLAG_WRITE_HIGH),
592
+
SG2042_GENERAL_PIN(PIN_GPIO18, 0x14c,
593
+
PIN_FLAG_DEFAULT),
594
+
SG2042_GENERAL_PIN(PIN_GPIO19, 0x14c,
595
+
PIN_FLAG_WRITE_HIGH),
596
+
SG2042_GENERAL_PIN(PIN_GPIO20, 0x150,
597
+
PIN_FLAG_DEFAULT),
598
+
SG2042_GENERAL_PIN(PIN_GPIO21, 0x150,
599
+
PIN_FLAG_WRITE_HIGH),
600
+
SG2042_GENERAL_PIN(PIN_GPIO22, 0x154,
601
+
PIN_FLAG_DEFAULT),
602
+
SG2042_GENERAL_PIN(PIN_GPIO23, 0x154,
603
+
PIN_FLAG_WRITE_HIGH),
604
+
SG2042_GENERAL_PIN(PIN_GPIO24, 0x158,
605
+
PIN_FLAG_DEFAULT),
606
+
SG2042_GENERAL_PIN(PIN_GPIO25, 0x158,
607
+
PIN_FLAG_WRITE_HIGH),
608
+
SG2042_GENERAL_PIN(PIN_GPIO26, 0x15c,
609
+
PIN_FLAG_DEFAULT),
610
+
SG2042_GENERAL_PIN(PIN_GPIO27, 0x15c,
611
+
PIN_FLAG_WRITE_HIGH),
612
+
SG2042_GENERAL_PIN(PIN_GPIO28, 0x160,
613
+
PIN_FLAG_DEFAULT),
614
+
SG2042_GENERAL_PIN(PIN_GPIO29, 0x160,
615
+
PIN_FLAG_WRITE_HIGH),
616
+
SG2042_GENERAL_PIN(PIN_GPIO30, 0x164,
617
+
PIN_FLAG_DEFAULT),
618
+
SG2042_GENERAL_PIN(PIN_GPIO31, 0x164,
619
+
PIN_FLAG_WRITE_HIGH),
620
+
SG2042_GENERAL_PIN(PIN_MODE_SEL0, 0x168,
621
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
622
+
SG2042_GENERAL_PIN(PIN_MODE_SEL1, 0x168,
623
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
624
+
PIN_FLAG_NO_OEX_EN),
625
+
SG2042_GENERAL_PIN(PIN_MODE_SEL2, 0x16c,
626
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
627
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL0, 0x16c,
628
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
629
+
PIN_FLAG_NO_OEX_EN),
630
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL1, 0x170,
631
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
632
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL2, 0x170,
633
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
634
+
PIN_FLAG_NO_OEX_EN),
635
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL3, 0x174,
636
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
637
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL4, 0x174,
638
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
639
+
PIN_FLAG_NO_OEX_EN),
640
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL5, 0x178,
641
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
642
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL6, 0x178,
643
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
644
+
PIN_FLAG_NO_OEX_EN),
645
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL7, 0x17c,
646
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
647
+
SG2042_GENERAL_PIN(PIN_MULTI_SCKT, 0x17c,
648
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
649
+
PIN_FLAG_NO_OEX_EN),
650
+
SG2042_GENERAL_PIN(PIN_SCKT_ID0, 0x180,
651
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
652
+
SG2042_GENERAL_PIN(PIN_SCKT_ID1, 0x180,
653
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
654
+
PIN_FLAG_NO_OEX_EN),
655
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_MAIN, 0x184,
656
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
657
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_0, 0x184,
658
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
659
+
PIN_FLAG_NO_OEX_EN),
660
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_1, 0x188,
661
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
662
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_2, 0x188,
663
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
664
+
PIN_FLAG_NO_OEX_EN),
665
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_3, 0x18c,
666
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
667
+
SG2042_GENERAL_PIN(PIN_XTAL_32K, 0x18c,
668
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
669
+
PIN_FLAG_NO_OEX_EN),
670
+
SG2042_GENERAL_PIN(PIN_SYS_RST, 0x190,
671
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
672
+
SG2042_GENERAL_PIN(PIN_PWR_BUTTON, 0x190,
673
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
674
+
PIN_FLAG_NO_OEX_EN),
675
+
SG2042_GENERAL_PIN(PIN_TEST_EN, 0x194,
676
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
677
+
SG2042_GENERAL_PIN(PIN_TEST_MODE_MBIST, 0x194,
678
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
679
+
PIN_FLAG_NO_OEX_EN),
680
+
SG2042_GENERAL_PIN(PIN_TEST_MODE_SCAN, 0x198,
681
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
682
+
SG2042_GENERAL_PIN(PIN_TEST_MODE_BSD, 0x198,
683
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX |
684
+
PIN_FLAG_NO_OEX_EN),
685
+
SG2042_GENERAL_PIN(PIN_BISR_BYP, 0x19c,
686
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
687
+
};
688
+
689
+
static const struct sophgo_pinctrl_data sg2044_pindata = {
690
+
.pins = sg2044_pins,
691
+
.pindata = sg2044_pin_data,
692
+
.vddio_ops = &sg2044_vddio_cfg_ops,
693
+
.cfg_ops = &sg2042_cfg_ops,
694
+
.pctl_ops = &sg2042_pctrl_ops,
695
+
.pmx_ops = &sg2042_pmx_ops,
696
+
.pconf_ops = &sg2042_pconf_ops,
697
+
.npins = ARRAY_SIZE(sg2044_pins),
698
+
.pinsize = sizeof(struct sg2042_pin),
699
+
};
700
+
701
+
static const struct of_device_id sg2044_pinctrl_ids[] = {
702
+
{ .compatible = "sophgo,sg2044-pinctrl", .data = &sg2044_pindata },
703
+
{ }
704
+
};
705
+
MODULE_DEVICE_TABLE(of, sg2044_pinctrl_ids);
706
+
707
+
static struct platform_driver sg2044_pinctrl_driver = {
708
+
.probe = sophgo_pinctrl_probe,
709
+
.driver = {
710
+
.name = "sg2044-pinctrl",
711
+
.suppress_bind_attrs = true,
712
+
.of_match_table = sg2044_pinctrl_ids,
713
+
},
714
+
};
715
+
module_platform_driver(sg2044_pinctrl_driver);
716
+
717
+
MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC");
718
+
MODULE_LICENSE("GPL");
+451
drivers/pinctrl/sophgo/pinctrl-sophgo-common.c
+451
drivers/pinctrl/sophgo/pinctrl-sophgo-common.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo SoCs pinctrl common ops.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*
7
+
*/
8
+
9
+
#include <linux/bsearch.h>
10
+
#include <linux/cleanup.h>
11
+
#include <linux/export.h>
12
+
#include <linux/io.h>
13
+
#include <linux/of.h>
14
+
#include <linux/module.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/seq_file.h>
17
+
#include <linux/spinlock.h>
18
+
19
+
#include <linux/pinctrl/pinconf-generic.h>
20
+
#include <linux/pinctrl/pinctrl.h>
21
+
22
+
#include "../pinctrl-utils.h"
23
+
#include "../pinconf.h"
24
+
#include "../pinmux.h"
25
+
26
+
#include "pinctrl-sophgo.h"
27
+
28
+
static u16 sophgo_dt_get_pin(u32 value)
29
+
{
30
+
return value;
31
+
}
32
+
33
+
static int sophgo_cmp_pin(const void *key, const void *pivot)
34
+
{
35
+
const struct sophgo_pin *pin = pivot;
36
+
int pin_id = (long)key;
37
+
int pivid = pin->id;
38
+
39
+
return pin_id - pivid;
40
+
}
41
+
42
+
const struct sophgo_pin *sophgo_get_pin(struct sophgo_pinctrl *pctrl,
43
+
unsigned long pin_id)
44
+
{
45
+
return bsearch((void *)pin_id, pctrl->data->pindata, pctrl->data->npins,
46
+
pctrl->data->pinsize, sophgo_cmp_pin);
47
+
}
48
+
49
+
static int sophgo_verify_pinmux_config(struct sophgo_pinctrl *pctrl,
50
+
const struct sophgo_pin_mux_config *config)
51
+
{
52
+
if (pctrl->data->cfg_ops->verify_pinmux_config)
53
+
return pctrl->data->cfg_ops->verify_pinmux_config(config);
54
+
return 0;
55
+
}
56
+
57
+
static int sophgo_verify_pin_group(struct sophgo_pinctrl *pctrl,
58
+
const struct sophgo_pin_mux_config *config,
59
+
unsigned int npins)
60
+
{
61
+
if (pctrl->data->cfg_ops->verify_pin_group)
62
+
return pctrl->data->cfg_ops->verify_pin_group(config, npins);
63
+
return 0;
64
+
}
65
+
66
+
static int sophgo_dt_node_to_map_post(struct device_node *cur,
67
+
struct sophgo_pinctrl *pctrl,
68
+
struct sophgo_pin_mux_config *config,
69
+
unsigned int npins)
70
+
{
71
+
if (pctrl->data->cfg_ops->dt_node_to_map_post)
72
+
return pctrl->data->cfg_ops->dt_node_to_map_post(cur, pctrl,
73
+
config, npins);
74
+
return 0;
75
+
}
76
+
77
+
int sophgo_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np,
78
+
struct pinctrl_map **maps, unsigned int *num_maps)
79
+
{
80
+
struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
81
+
struct device *dev = pctrl->dev;
82
+
struct device_node *child;
83
+
struct pinctrl_map *map;
84
+
const char **grpnames;
85
+
const char *grpname;
86
+
int ngroups = 0;
87
+
int nmaps = 0;
88
+
int ret;
89
+
90
+
for_each_available_child_of_node(np, child)
91
+
ngroups += 1;
92
+
93
+
grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL);
94
+
if (!grpnames)
95
+
return -ENOMEM;
96
+
97
+
map = kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL);
98
+
if (!map)
99
+
return -ENOMEM;
100
+
101
+
ngroups = 0;
102
+
guard(mutex)(&pctrl->mutex);
103
+
for_each_available_child_of_node(np, child) {
104
+
int npins = of_property_count_u32_elems(child, "pinmux");
105
+
unsigned int *pins;
106
+
struct sophgo_pin_mux_config *pinmuxs;
107
+
u32 config;
108
+
int i;
109
+
110
+
if (npins < 1) {
111
+
dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n",
112
+
np, child);
113
+
ret = -EINVAL;
114
+
goto dt_failed;
115
+
}
116
+
117
+
grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn",
118
+
np, child);
119
+
if (!grpname) {
120
+
ret = -ENOMEM;
121
+
goto dt_failed;
122
+
}
123
+
124
+
grpnames[ngroups++] = grpname;
125
+
126
+
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
127
+
if (!pins) {
128
+
ret = -ENOMEM;
129
+
goto dt_failed;
130
+
}
131
+
132
+
pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL);
133
+
if (!pinmuxs) {
134
+
ret = -ENOMEM;
135
+
goto dt_failed;
136
+
}
137
+
138
+
for (i = 0; i < npins; i++) {
139
+
ret = of_property_read_u32_index(child, "pinmux",
140
+
i, &config);
141
+
if (ret)
142
+
goto dt_failed;
143
+
144
+
pins[i] = sophgo_dt_get_pin(config);
145
+
pinmuxs[i].config = config;
146
+
pinmuxs[i].pin = sophgo_get_pin(pctrl, pins[i]);
147
+
148
+
if (!pinmuxs[i].pin) {
149
+
dev_err(dev, "failed to get pin %d\n", pins[i]);
150
+
ret = -ENODEV;
151
+
goto dt_failed;
152
+
}
153
+
154
+
ret = sophgo_verify_pinmux_config(pctrl, &pinmuxs[i]);
155
+
if (ret) {
156
+
dev_err(dev, "group %s pin %d is invalid\n",
157
+
grpname, i);
158
+
goto dt_failed;
159
+
}
160
+
}
161
+
162
+
ret = sophgo_verify_pin_group(pctrl, pinmuxs, npins);
163
+
if (ret) {
164
+
dev_err(dev, "group %s is invalid\n", grpname);
165
+
goto dt_failed;
166
+
}
167
+
168
+
ret = sophgo_dt_node_to_map_post(child, pctrl, pinmuxs, npins);
169
+
if (ret)
170
+
goto dt_failed;
171
+
172
+
map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
173
+
map[nmaps].data.mux.function = np->name;
174
+
map[nmaps].data.mux.group = grpname;
175
+
nmaps += 1;
176
+
177
+
ret = pinconf_generic_parse_dt_config(child, pctldev,
178
+
&map[nmaps].data.configs.configs,
179
+
&map[nmaps].data.configs.num_configs);
180
+
if (ret) {
181
+
dev_err(dev, "failed to parse pin config of group %s: %d\n",
182
+
grpname, ret);
183
+
goto dt_failed;
184
+
}
185
+
186
+
ret = pinctrl_generic_add_group(pctldev, grpname,
187
+
pins, npins, pinmuxs);
188
+
if (ret < 0) {
189
+
dev_err(dev, "failed to add group %s: %d\n", grpname, ret);
190
+
goto dt_failed;
191
+
}
192
+
193
+
/* don't create a map if there are no pinconf settings */
194
+
if (map[nmaps].data.configs.num_configs == 0)
195
+
continue;
196
+
197
+
map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
198
+
map[nmaps].data.configs.group_or_pin = grpname;
199
+
nmaps += 1;
200
+
}
201
+
202
+
ret = pinmux_generic_add_function(pctldev, np->name,
203
+
grpnames, ngroups, NULL);
204
+
if (ret < 0) {
205
+
dev_err(dev, "error adding function %s: %d\n", np->name, ret);
206
+
goto function_failed;
207
+
}
208
+
209
+
*maps = map;
210
+
*num_maps = nmaps;
211
+
212
+
return 0;
213
+
214
+
dt_failed:
215
+
of_node_put(child);
216
+
function_failed:
217
+
pinctrl_utils_free_map(pctldev, map, nmaps);
218
+
return ret;
219
+
}
220
+
221
+
int sophgo_pmx_set_mux(struct pinctrl_dev *pctldev,
222
+
unsigned int fsel, unsigned int gsel)
223
+
{
224
+
struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
225
+
const struct group_desc *group;
226
+
const struct sophgo_pin_mux_config *configs;
227
+
unsigned int i;
228
+
229
+
group = pinctrl_generic_get_group(pctldev, gsel);
230
+
if (!group)
231
+
return -EINVAL;
232
+
233
+
configs = group->data;
234
+
235
+
for (i = 0; i < group->grp.npins; i++) {
236
+
const struct sophgo_pin *pin = configs[i].pin;
237
+
u32 value = configs[i].config;
238
+
239
+
guard(raw_spinlock_irqsave)(&pctrl->lock);
240
+
241
+
pctrl->data->cfg_ops->set_pinmux_config(pctrl, pin, value);
242
+
}
243
+
244
+
return 0;
245
+
}
246
+
247
+
static int sophgo_pin_set_config(struct sophgo_pinctrl *pctrl,
248
+
unsigned int pin_id,
249
+
u32 value, u32 mask)
250
+
{
251
+
const struct sophgo_pin *pin = sophgo_get_pin(pctrl, pin_id);
252
+
253
+
if (!pin)
254
+
return -EINVAL;
255
+
256
+
guard(raw_spinlock_irqsave)(&pctrl->lock);
257
+
258
+
return pctrl->data->cfg_ops->set_pinconf_config(pctrl, pin, value, mask);
259
+
}
260
+
261
+
int sophgo_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
262
+
unsigned long *configs, unsigned int num_configs)
263
+
{
264
+
struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
265
+
const struct sophgo_pin *pin = sophgo_get_pin(pctrl, pin_id);
266
+
u32 value, mask;
267
+
268
+
if (!pin)
269
+
return -ENODEV;
270
+
271
+
if (pctrl->data->cfg_ops->compute_pinconf_config(pctrl, pin,
272
+
configs, num_configs,
273
+
&value, &mask))
274
+
return -ENOTSUPP;
275
+
276
+
return sophgo_pin_set_config(pctrl, pin_id, value, mask);
277
+
}
278
+
279
+
int sophgo_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int gsel,
280
+
unsigned long *configs, unsigned int num_configs)
281
+
{
282
+
struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
283
+
const struct group_desc *group;
284
+
const struct sophgo_pin_mux_config *pinmuxs;
285
+
u32 value, mask;
286
+
int i;
287
+
288
+
group = pinctrl_generic_get_group(pctldev, gsel);
289
+
if (!group)
290
+
return -EINVAL;
291
+
292
+
pinmuxs = group->data;
293
+
294
+
if (pctrl->data->cfg_ops->compute_pinconf_config(pctrl, pinmuxs[0].pin,
295
+
configs, num_configs,
296
+
&value, &mask))
297
+
return -ENOTSUPP;
298
+
299
+
for (i = 0; i < group->grp.npins; i++)
300
+
sophgo_pin_set_config(pctrl, group->grp.pins[i], value, mask);
301
+
302
+
return 0;
303
+
}
304
+
305
+
u32 sophgo_pinctrl_typical_pull_down(struct sophgo_pinctrl *pctrl,
306
+
const struct sophgo_pin *pin,
307
+
const u32 *power_cfg)
308
+
{
309
+
return pctrl->data->vddio_ops->get_pull_down(pin, power_cfg);
310
+
}
311
+
312
+
u32 sophgo_pinctrl_typical_pull_up(struct sophgo_pinctrl *pctrl,
313
+
const struct sophgo_pin *pin,
314
+
const u32 *power_cfg)
315
+
{
316
+
return pctrl->data->vddio_ops->get_pull_up(pin, power_cfg);
317
+
}
318
+
319
+
int sophgo_pinctrl_oc2reg(struct sophgo_pinctrl *pctrl,
320
+
const struct sophgo_pin *pin,
321
+
const u32 *power_cfg, u32 target)
322
+
{
323
+
const u32 *map;
324
+
int i, len;
325
+
326
+
if (!pctrl->data->vddio_ops->get_oc_map)
327
+
return -ENOTSUPP;
328
+
329
+
len = pctrl->data->vddio_ops->get_oc_map(pin, power_cfg, &map);
330
+
if (len < 0)
331
+
return len;
332
+
333
+
for (i = 0; i < len; i++) {
334
+
if (map[i] >= target)
335
+
return i;
336
+
}
337
+
338
+
return -EINVAL;
339
+
}
340
+
341
+
int sophgo_pinctrl_reg2oc(struct sophgo_pinctrl *pctrl,
342
+
const struct sophgo_pin *pin,
343
+
const u32 *power_cfg, u32 reg)
344
+
{
345
+
const u32 *map;
346
+
int len;
347
+
348
+
if (!pctrl->data->vddio_ops->get_oc_map)
349
+
return -ENOTSUPP;
350
+
351
+
len = pctrl->data->vddio_ops->get_oc_map(pin, power_cfg, &map);
352
+
if (len < 0)
353
+
return len;
354
+
355
+
if (reg >= len)
356
+
return -EINVAL;
357
+
358
+
return map[reg];
359
+
}
360
+
361
+
int sophgo_pinctrl_schmitt2reg(struct sophgo_pinctrl *pctrl,
362
+
const struct sophgo_pin *pin,
363
+
const u32 *power_cfg, u32 target)
364
+
{
365
+
const u32 *map;
366
+
int i, len;
367
+
368
+
if (!pctrl->data->vddio_ops->get_schmitt_map)
369
+
return -ENOTSUPP;
370
+
371
+
len = pctrl->data->vddio_ops->get_schmitt_map(pin, power_cfg, &map);
372
+
if (len < 0)
373
+
return len;
374
+
375
+
for (i = 0; i < len; i++) {
376
+
if (map[i] == target)
377
+
return i;
378
+
}
379
+
380
+
return -EINVAL;
381
+
}
382
+
383
+
int sophgo_pinctrl_reg2schmitt(struct sophgo_pinctrl *pctrl,
384
+
const struct sophgo_pin *pin,
385
+
const u32 *power_cfg, u32 reg)
386
+
{
387
+
const u32 *map;
388
+
int len;
389
+
390
+
if (!pctrl->data->vddio_ops->get_schmitt_map)
391
+
return -ENOTSUPP;
392
+
393
+
len = pctrl->data->vddio_ops->get_schmitt_map(pin, power_cfg, &map);
394
+
if (len < 0)
395
+
return len;
396
+
397
+
if (reg >= len)
398
+
return -EINVAL;
399
+
400
+
return map[reg];
401
+
}
402
+
403
+
int sophgo_pinctrl_probe(struct platform_device *pdev)
404
+
{
405
+
struct device *dev = &pdev->dev;
406
+
struct sophgo_pinctrl *pctrl;
407
+
const struct sophgo_pinctrl_data *pctrl_data;
408
+
int ret;
409
+
410
+
pctrl_data = device_get_match_data(dev);
411
+
if (!pctrl_data)
412
+
return -ENODEV;
413
+
414
+
if (pctrl_data->npins == 0)
415
+
return dev_err_probe(dev, -EINVAL, "invalid pin data\n");
416
+
417
+
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
418
+
if (!pctrl)
419
+
return -ENOMEM;
420
+
421
+
pctrl->pdesc.name = dev_name(dev);
422
+
pctrl->pdesc.pins = pctrl_data->pins;
423
+
pctrl->pdesc.npins = pctrl_data->npins;
424
+
pctrl->pdesc.pctlops = pctrl_data->pctl_ops;
425
+
pctrl->pdesc.pmxops = pctrl_data->pmx_ops;
426
+
pctrl->pdesc.confops = pctrl_data->pconf_ops;
427
+
pctrl->pdesc.owner = THIS_MODULE;
428
+
429
+
pctrl->data = pctrl_data;
430
+
pctrl->dev = dev;
431
+
raw_spin_lock_init(&pctrl->lock);
432
+
mutex_init(&pctrl->mutex);
433
+
434
+
ret = pctrl->data->cfg_ops->pctrl_init(pdev, pctrl);
435
+
if (ret)
436
+
return ret;
437
+
438
+
platform_set_drvdata(pdev, pctrl);
439
+
440
+
ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc,
441
+
pctrl, &pctrl->pctrl_dev);
442
+
if (ret)
443
+
return dev_err_probe(dev, ret,
444
+
"fail to register pinctrl driver\n");
445
+
446
+
return pinctrl_enable(pctrl->pctrl_dev);
447
+
}
448
+
EXPORT_SYMBOL_GPL(sophgo_pinctrl_probe);
449
+
450
+
MODULE_DESCRIPTION("Common pinctrl helper function for the Sophgo SoC");
451
+
MODULE_LICENSE("GPL");
+136
drivers/pinctrl/sophgo/pinctrl-sophgo.h
+136
drivers/pinctrl/sophgo/pinctrl-sophgo.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#ifndef _PINCTRL_SOPHGO_H
7
+
#define _PINCTRL_SOPHGO_H
8
+
9
+
#include <linux/device.h>
10
+
#include <linux/mutex.h>
11
+
#include <linux/pinctrl/pinctrl.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/spinlock.h>
14
+
15
+
#include "../core.h"
16
+
17
+
struct sophgo_pinctrl;
18
+
19
+
struct sophgo_pin {
20
+
u16 id;
21
+
u16 flags;
22
+
};
23
+
24
+
struct sophgo_pin_mux_config {
25
+
const struct sophgo_pin *pin;
26
+
u32 config;
27
+
};
28
+
29
+
/**
30
+
* struct sophgo_cfg_ops - pin configuration operations
31
+
*
32
+
* @pctrl_init: soc specific init callback
33
+
* @verify_pinmux_config: verify the pinmux config for a pin
34
+
* @verify_pin_group: verify the whole pinmux group
35
+
* @dt_node_to_map_post: post init for the pinmux config map
36
+
* @compute_pinconf_config: compute pinconf config
37
+
* @set_pinconf_config: set pinconf config (the caller holds lock)
38
+
* @set_pinmux_config: set mux config (the caller holds lock)
39
+
*/
40
+
struct sophgo_cfg_ops {
41
+
int (*pctrl_init)(struct platform_device *pdev,
42
+
struct sophgo_pinctrl *pctrl);
43
+
int (*verify_pinmux_config)(const struct sophgo_pin_mux_config *config);
44
+
int (*verify_pin_group)(const struct sophgo_pin_mux_config *pinmuxs,
45
+
unsigned int npins);
46
+
int (*dt_node_to_map_post)(struct device_node *cur,
47
+
struct sophgo_pinctrl *pctrl,
48
+
struct sophgo_pin_mux_config *pinmuxs,
49
+
unsigned int npins);
50
+
int (*compute_pinconf_config)(struct sophgo_pinctrl *pctrl,
51
+
const struct sophgo_pin *sp,
52
+
unsigned long *configs,
53
+
unsigned int num_configs,
54
+
u32 *value, u32 *mask);
55
+
int (*set_pinconf_config)(struct sophgo_pinctrl *pctrl,
56
+
const struct sophgo_pin *sp,
57
+
u32 value, u32 mask);
58
+
void (*set_pinmux_config)(struct sophgo_pinctrl *pctrl,
59
+
const struct sophgo_pin *sp, u32 config);
60
+
};
61
+
62
+
/**
63
+
* struct sophgo_vddio_cfg_ops - pin vddio operations
64
+
*
65
+
* @get_pull_up: get resistor for pull up;
66
+
* @get_pull_down: get resistor for pull down.
67
+
* @get_oc_map: get mapping for typical low level output current value to
68
+
* register value map.
69
+
* @get_schmitt_map: get mapping for register value to typical schmitt
70
+
* threshold.
71
+
*/
72
+
struct sophgo_vddio_cfg_ops {
73
+
int (*get_pull_up)(const struct sophgo_pin *pin, const u32 *psmap);
74
+
int (*get_pull_down)(const struct sophgo_pin *pin, const u32 *psmap);
75
+
int (*get_oc_map)(const struct sophgo_pin *pin, const u32 *psmap,
76
+
const u32 **map);
77
+
int (*get_schmitt_map)(const struct sophgo_pin *pin, const u32 *psmap,
78
+
const u32 **map);
79
+
};
80
+
81
+
struct sophgo_pinctrl_data {
82
+
const struct pinctrl_pin_desc *pins;
83
+
const void *pindata;
84
+
const char * const *pdnames;
85
+
const struct sophgo_vddio_cfg_ops *vddio_ops;
86
+
const struct sophgo_cfg_ops *cfg_ops;
87
+
const struct pinctrl_ops *pctl_ops;
88
+
const struct pinmux_ops *pmx_ops;
89
+
const struct pinconf_ops *pconf_ops;
90
+
u16 npins;
91
+
u16 npds;
92
+
u16 pinsize;
93
+
};
94
+
95
+
struct sophgo_pinctrl {
96
+
struct device *dev;
97
+
struct pinctrl_dev *pctrl_dev;
98
+
const struct sophgo_pinctrl_data *data;
99
+
struct pinctrl_desc pdesc;
100
+
101
+
struct mutex mutex;
102
+
raw_spinlock_t lock;
103
+
void *priv_ctrl;
104
+
};
105
+
106
+
const struct sophgo_pin *sophgo_get_pin(struct sophgo_pinctrl *pctrl,
107
+
unsigned long pin_id);
108
+
int sophgo_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np,
109
+
struct pinctrl_map **maps, unsigned int *num_maps);
110
+
int sophgo_pmx_set_mux(struct pinctrl_dev *pctldev,
111
+
unsigned int fsel, unsigned int gsel);
112
+
int sophgo_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
113
+
unsigned long *configs, unsigned int num_configs);
114
+
int sophgo_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int gsel,
115
+
unsigned long *configs, unsigned int num_configs);
116
+
u32 sophgo_pinctrl_typical_pull_down(struct sophgo_pinctrl *pctrl,
117
+
const struct sophgo_pin *pin,
118
+
const u32 *power_cfg);
119
+
u32 sophgo_pinctrl_typical_pull_up(struct sophgo_pinctrl *pctrl,
120
+
const struct sophgo_pin *pin,
121
+
const u32 *power_cfg);
122
+
int sophgo_pinctrl_oc2reg(struct sophgo_pinctrl *pctrl,
123
+
const struct sophgo_pin *pin,
124
+
const u32 *power_cfg, u32 target);
125
+
int sophgo_pinctrl_reg2oc(struct sophgo_pinctrl *pctrl,
126
+
const struct sophgo_pin *pin,
127
+
const u32 *power_cfg, u32 reg);
128
+
int sophgo_pinctrl_schmitt2reg(struct sophgo_pinctrl *pctrl,
129
+
const struct sophgo_pin *pin,
130
+
const u32 *power_cfg, u32 target);
131
+
int sophgo_pinctrl_reg2schmitt(struct sophgo_pinctrl *pctrl,
132
+
const struct sophgo_pin *pin,
133
+
const u32 *power_cfg, u32 reg);
134
+
int sophgo_pinctrl_probe(struct platform_device *pdev);
135
+
136
+
#endif /* _PINCTRL_SOPHGO_H */
+196
include/dt-bindings/pinctrl/pinctrl-sg2042.h
+196
include/dt-bindings/pinctrl/pinctrl-sg2042.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
4
+
*
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_PINCTRL_SG2042_H
8
+
#define _DT_BINDINGS_PINCTRL_SG2042_H
9
+
10
+
#define PINMUX(pin, mux) \
11
+
(((pin) & 0xffff) | (((mux) & 0xff) << 16))
12
+
13
+
#define PIN_LPC_LCLK 0
14
+
#define PIN_LPC_LFRAME 1
15
+
#define PIN_LPC_LAD0 2
16
+
#define PIN_LPC_LAD1 3
17
+
#define PIN_LPC_LAD2 4
18
+
#define PIN_LPC_LAD3 5
19
+
#define PIN_LPC_LDRQ0 6
20
+
#define PIN_LPC_LDRQ1 7
21
+
#define PIN_LPC_SERIRQ 8
22
+
#define PIN_LPC_CLKRUN 9
23
+
#define PIN_LPC_LPME 10
24
+
#define PIN_LPC_LPCPD 11
25
+
#define PIN_LPC_LSMI 12
26
+
#define PIN_PCIE0_L0_RESET 13
27
+
#define PIN_PCIE0_L1_RESET 14
28
+
#define PIN_PCIE0_L0_WAKEUP 15
29
+
#define PIN_PCIE0_L1_WAKEUP 16
30
+
#define PIN_PCIE0_L0_CLKREQ_IN 17
31
+
#define PIN_PCIE0_L1_CLKREQ_IN 18
32
+
#define PIN_PCIE1_L0_RESET 19
33
+
#define PIN_PCIE1_L1_RESET 20
34
+
#define PIN_PCIE1_L0_WAKEUP 21
35
+
#define PIN_PCIE1_L1_WAKEUP 22
36
+
#define PIN_PCIE1_L0_CLKREQ_IN 23
37
+
#define PIN_PCIE1_L1_CLKREQ_IN 24
38
+
#define PIN_SPIF0_CLK_SEL1 25
39
+
#define PIN_SPIF0_CLK_SEL0 26
40
+
#define PIN_SPIF0_WP 27
41
+
#define PIN_SPIF0_HOLD 28
42
+
#define PIN_SPIF0_SDI 29
43
+
#define PIN_SPIF0_CS 30
44
+
#define PIN_SPIF0_SCK 31
45
+
#define PIN_SPIF0_SDO 32
46
+
#define PIN_SPIF1_CLK_SEL1 33
47
+
#define PIN_SPIF1_CLK_SEL0 34
48
+
#define PIN_SPIF1_WP 35
49
+
#define PIN_SPIF1_HOLD 36
50
+
#define PIN_SPIF1_SDI 37
51
+
#define PIN_SPIF1_CS 38
52
+
#define PIN_SPIF1_SCK 39
53
+
#define PIN_SPIF1_SDO 40
54
+
#define PIN_EMMC_WP 41
55
+
#define PIN_EMMC_CD 42
56
+
#define PIN_EMMC_RST 43
57
+
#define PIN_EMMC_PWR_EN 44
58
+
#define PIN_SDIO_CD 45
59
+
#define PIN_SDIO_WP 46
60
+
#define PIN_SDIO_RST 47
61
+
#define PIN_SDIO_PWR_EN 48
62
+
#define PIN_RGMII0_TXD0 49
63
+
#define PIN_RGMII0_TXD1 50
64
+
#define PIN_RGMII0_TXD2 51
65
+
#define PIN_RGMII0_TXD3 52
66
+
#define PIN_RGMII0_TXCTRL 53
67
+
#define PIN_RGMII0_RXD0 54
68
+
#define PIN_RGMII0_RXD1 55
69
+
#define PIN_RGMII0_RXD2 56
70
+
#define PIN_RGMII0_RXD3 57
71
+
#define PIN_RGMII0_RXCTRL 58
72
+
#define PIN_RGMII0_TXC 59
73
+
#define PIN_RGMII0_RXC 60
74
+
#define PIN_RGMII0_REFCLKO 61
75
+
#define PIN_RGMII0_IRQ 62
76
+
#define PIN_RGMII0_MDC 63
77
+
#define PIN_RGMII0_MDIO 64
78
+
#define PIN_PWM0 65
79
+
#define PIN_PWM1 66
80
+
#define PIN_PWM2 67
81
+
#define PIN_PWM3 68
82
+
#define PIN_FAN0 69
83
+
#define PIN_FAN1 70
84
+
#define PIN_FAN2 71
85
+
#define PIN_FAN3 72
86
+
#define PIN_IIC0_SDA 73
87
+
#define PIN_IIC0_SCL 74
88
+
#define PIN_IIC1_SDA 75
89
+
#define PIN_IIC1_SCL 76
90
+
#define PIN_IIC2_SDA 77
91
+
#define PIN_IIC2_SCL 78
92
+
#define PIN_IIC3_SDA 79
93
+
#define PIN_IIC3_SCL 80
94
+
#define PIN_UART0_TX 81
95
+
#define PIN_UART0_RX 82
96
+
#define PIN_UART0_RTS 83
97
+
#define PIN_UART0_CTS 84
98
+
#define PIN_UART1_TX 85
99
+
#define PIN_UART1_RX 86
100
+
#define PIN_UART1_RTS 87
101
+
#define PIN_UART1_CTS 88
102
+
#define PIN_UART2_TX 89
103
+
#define PIN_UART2_RX 90
104
+
#define PIN_UART2_RTS 91
105
+
#define PIN_UART2_CTS 92
106
+
#define PIN_UART3_TX 93
107
+
#define PIN_UART3_RX 94
108
+
#define PIN_UART3_RTS 95
109
+
#define PIN_UART3_CTS 96
110
+
#define PIN_SPI0_CS0 97
111
+
#define PIN_SPI0_CS1 98
112
+
#define PIN_SPI0_SDI 99
113
+
#define PIN_SPI0_SDO 100
114
+
#define PIN_SPI0_SCK 101
115
+
#define PIN_SPI1_CS0 102
116
+
#define PIN_SPI1_CS1 103
117
+
#define PIN_SPI1_SDI 104
118
+
#define PIN_SPI1_SDO 105
119
+
#define PIN_SPI1_SCK 106
120
+
#define PIN_JTAG0_TDO 107
121
+
#define PIN_JTAG0_TCK 108
122
+
#define PIN_JTAG0_TDI 109
123
+
#define PIN_JTAG0_TMS 110
124
+
#define PIN_JTAG0_TRST 111
125
+
#define PIN_JTAG0_SRST 112
126
+
#define PIN_JTAG1_TDO 113
127
+
#define PIN_JTAG1_TCK 114
128
+
#define PIN_JTAG1_TDI 115
129
+
#define PIN_JTAG1_TMS 116
130
+
#define PIN_JTAG1_TRST 117
131
+
#define PIN_JTAG1_SRST 118
132
+
#define PIN_JTAG2_TDO 119
133
+
#define PIN_JTAG2_TCK 120
134
+
#define PIN_JTAG2_TDI 121
135
+
#define PIN_JTAG2_TMS 122
136
+
#define PIN_JTAG2_TRST 123
137
+
#define PIN_JTAG2_SRST 124
138
+
#define PIN_GPIO0 125
139
+
#define PIN_GPIO1 126
140
+
#define PIN_GPIO2 127
141
+
#define PIN_GPIO3 128
142
+
#define PIN_GPIO4 129
143
+
#define PIN_GPIO5 130
144
+
#define PIN_GPIO6 131
145
+
#define PIN_GPIO7 132
146
+
#define PIN_GPIO8 133
147
+
#define PIN_GPIO9 134
148
+
#define PIN_GPIO10 135
149
+
#define PIN_GPIO11 136
150
+
#define PIN_GPIO12 137
151
+
#define PIN_GPIO13 138
152
+
#define PIN_GPIO14 139
153
+
#define PIN_GPIO15 140
154
+
#define PIN_GPIO16 141
155
+
#define PIN_GPIO17 142
156
+
#define PIN_GPIO18 143
157
+
#define PIN_GPIO19 144
158
+
#define PIN_GPIO20 145
159
+
#define PIN_GPIO21 146
160
+
#define PIN_GPIO22 147
161
+
#define PIN_GPIO23 148
162
+
#define PIN_GPIO24 149
163
+
#define PIN_GPIO25 150
164
+
#define PIN_GPIO26 151
165
+
#define PIN_GPIO27 152
166
+
#define PIN_GPIO28 153
167
+
#define PIN_GPIO29 154
168
+
#define PIN_GPIO30 155
169
+
#define PIN_GPIO31 156
170
+
#define PIN_MODE_SEL0 157
171
+
#define PIN_MODE_SEL1 158
172
+
#define PIN_MODE_SEL2 159
173
+
#define PIN_BOOT_SEL0 160
174
+
#define PIN_BOOT_SEL1 161
175
+
#define PIN_BOOT_SEL2 162
176
+
#define PIN_BOOT_SEL3 163
177
+
#define PIN_BOOT_SEL4 164
178
+
#define PIN_BOOT_SEL5 165
179
+
#define PIN_BOOT_SEL6 166
180
+
#define PIN_BOOT_SEL7 167
181
+
#define PIN_MULTI_SCKT 168
182
+
#define PIN_SCKT_ID0 169
183
+
#define PIN_SCKT_ID1 170
184
+
#define PIN_PLL_CLK_IN_MAIN 171
185
+
#define PIN_PLL_CLK_IN_DDR_L 172
186
+
#define PIN_PLL_CLK_IN_DDR_R 173
187
+
#define PIN_XTAL_32K 174
188
+
#define PIN_SYS_RST 175
189
+
#define PIN_PWR_BUTTON 176
190
+
#define PIN_TEST_EN 177
191
+
#define PIN_TEST_MODE_MBIST 178
192
+
#define PIN_TEST_MODE_SCAN 179
193
+
#define PIN_TEST_MODE_BSD 180
194
+
#define PIN_BISR_BYP 181
195
+
196
+
#endif /* _DT_BINDINGS_PINCTRL_SG2042_H */
+221
include/dt-bindings/pinctrl/pinctrl-sg2044.h
+221
include/dt-bindings/pinctrl/pinctrl-sg2044.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
4
+
*
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_PINCTRL_SG2044_H
8
+
#define _DT_BINDINGS_PINCTRL_SG2044_H
9
+
10
+
#define PINMUX(pin, mux) \
11
+
(((pin) & 0xffff) | (((mux) & 0xff) << 16))
12
+
13
+
#define PIN_IIC0_SMBSUS_IN 0
14
+
#define PIN_IIC0_SMBSUS_OUT 1
15
+
#define PIN_IIC0_SMBALERT 2
16
+
#define PIN_IIC1_SMBSUS_IN 3
17
+
#define PIN_IIC1_SMBSUS_OUT 4
18
+
#define PIN_IIC1_SMBALERT 5
19
+
#define PIN_IIC2_SMBSUS_IN 6
20
+
#define PIN_IIC2_SMBSUS_OUT 7
21
+
#define PIN_IIC2_SMBALERT 8
22
+
#define PIN_IIC3_SMBSUS_IN 9
23
+
#define PIN_IIC3_SMBSUS_OUT 10
24
+
#define PIN_IIC3_SMBALERT 11
25
+
#define PIN_PCIE0_L0_RESET 12
26
+
#define PIN_PCIE0_L1_RESET 13
27
+
#define PIN_PCIE0_L0_WAKEUP 14
28
+
#define PIN_PCIE0_L1_WAKEUP 15
29
+
#define PIN_PCIE0_L0_CLKREQ_IN 16
30
+
#define PIN_PCIE0_L1_CLKREQ_IN 17
31
+
#define PIN_PCIE1_L0_RESET 18
32
+
#define PIN_PCIE1_L1_RESET 19
33
+
#define PIN_PCIE1_L0_WAKEUP 20
34
+
#define PIN_PCIE1_L1_WAKEUP 21
35
+
#define PIN_PCIE1_L0_CLKREQ_IN 22
36
+
#define PIN_PCIE1_L1_CLKREQ_IN 23
37
+
#define PIN_PCIE2_L0_RESET 24
38
+
#define PIN_PCIE2_L1_RESET 25
39
+
#define PIN_PCIE2_L0_WAKEUP 26
40
+
#define PIN_PCIE2_L1_WAKEUP 27
41
+
#define PIN_PCIE2_L0_CLKREQ_IN 28
42
+
#define PIN_PCIE2_L1_CLKREQ_IN 29
43
+
#define PIN_PCIE3_L0_RESET 30
44
+
#define PIN_PCIE3_L1_RESET 31
45
+
#define PIN_PCIE3_L0_WAKEUP 32
46
+
#define PIN_PCIE3_L1_WAKEUP 33
47
+
#define PIN_PCIE3_L0_CLKREQ_IN 34
48
+
#define PIN_PCIE3_L1_CLKREQ_IN 35
49
+
#define PIN_PCIE4_L0_RESET 36
50
+
#define PIN_PCIE4_L1_RESET 37
51
+
#define PIN_PCIE4_L0_WAKEUP 38
52
+
#define PIN_PCIE4_L1_WAKEUP 39
53
+
#define PIN_PCIE4_L0_CLKREQ_IN 40
54
+
#define PIN_PCIE4_L1_CLKREQ_IN 41
55
+
#define PIN_SPIF0_CLK_SEL1 42
56
+
#define PIN_SPIF0_CLK_SEL0 43
57
+
#define PIN_SPIF0_WP 44
58
+
#define PIN_SPIF0_HOLD 45
59
+
#define PIN_SPIF0_SDI 46
60
+
#define PIN_SPIF0_CS 47
61
+
#define PIN_SPIF0_SCK 48
62
+
#define PIN_SPIF0_SDO 49
63
+
#define PIN_SPIF1_CLK_SEL1 50
64
+
#define PIN_SPIF1_CLK_SEL0 51
65
+
#define PIN_SPIF1_WP 52
66
+
#define PIN_SPIF1_HOLD 53
67
+
#define PIN_SPIF1_SDI 54
68
+
#define PIN_SPIF1_CS 55
69
+
#define PIN_SPIF1_SCK 56
70
+
#define PIN_SPIF1_SDO 57
71
+
#define PIN_EMMC_WP 58
72
+
#define PIN_EMMC_CD 59
73
+
#define PIN_EMMC_RST 60
74
+
#define PIN_EMMC_PWR_EN 61
75
+
#define PIN_SDIO_CD 62
76
+
#define PIN_SDIO_WP 63
77
+
#define PIN_SDIO_RST 64
78
+
#define PIN_SDIO_PWR_EN 65
79
+
#define PIN_RGMII0_TXD0 66
80
+
#define PIN_RGMII0_TXD1 67
81
+
#define PIN_RGMII0_TXD2 68
82
+
#define PIN_RGMII0_TXD3 69
83
+
#define PIN_RGMII0_TXCTRL 70
84
+
#define PIN_RGMII0_RXD0 71
85
+
#define PIN_RGMII0_RXD1 72
86
+
#define PIN_RGMII0_RXD2 73
87
+
#define PIN_RGMII0_RXD3 74
88
+
#define PIN_RGMII0_RXCTRL 75
89
+
#define PIN_RGMII0_TXC 76
90
+
#define PIN_RGMII0_RXC 77
91
+
#define PIN_RGMII0_REFCLKO 78
92
+
#define PIN_RGMII0_IRQ 79
93
+
#define PIN_RGMII0_MDC 80
94
+
#define PIN_RGMII0_MDIO 81
95
+
#define PIN_PWM0 82
96
+
#define PIN_PWM1 83
97
+
#define PIN_PWM2 84
98
+
#define PIN_PWM3 85
99
+
#define PIN_FAN0 86
100
+
#define PIN_FAN1 87
101
+
#define PIN_FAN2 88
102
+
#define PIN_FAN3 89
103
+
#define PIN_IIC0_SDA 90
104
+
#define PIN_IIC0_SCL 91
105
+
#define PIN_IIC1_SDA 92
106
+
#define PIN_IIC1_SCL 93
107
+
#define PIN_IIC2_SDA 94
108
+
#define PIN_IIC2_SCL 95
109
+
#define PIN_IIC3_SDA 96
110
+
#define PIN_IIC3_SCL 97
111
+
#define PIN_UART0_TX 98
112
+
#define PIN_UART0_RX 99
113
+
#define PIN_UART0_RTS 100
114
+
#define PIN_UART0_CTS 101
115
+
#define PIN_UART1_TX 102
116
+
#define PIN_UART1_RX 103
117
+
#define PIN_UART1_RTS 104
118
+
#define PIN_UART1_CTS 105
119
+
#define PIN_UART2_TX 106
120
+
#define PIN_UART2_RX 107
121
+
#define PIN_UART2_RTS 108
122
+
#define PIN_UART2_CTS 109
123
+
#define PIN_UART3_TX 110
124
+
#define PIN_UART3_RX 111
125
+
#define PIN_UART3_RTS 112
126
+
#define PIN_UART3_CTS 113
127
+
#define PIN_SPI0_CS0 114
128
+
#define PIN_SPI0_CS1 115
129
+
#define PIN_SPI0_SDI 116
130
+
#define PIN_SPI0_SDO 117
131
+
#define PIN_SPI0_SCK 118
132
+
#define PIN_SPI1_CS0 119
133
+
#define PIN_SPI1_CS1 120
134
+
#define PIN_SPI1_SDI 121
135
+
#define PIN_SPI1_SDO 122
136
+
#define PIN_SPI1_SCK 123
137
+
#define PIN_JTAG0_TDO 124
138
+
#define PIN_JTAG0_TCK 125
139
+
#define PIN_JTAG0_TDI 126
140
+
#define PIN_JTAG0_TMS 127
141
+
#define PIN_JTAG0_TRST 128
142
+
#define PIN_JTAG0_SRST 129
143
+
#define PIN_JTAG1_TDO 130
144
+
#define PIN_JTAG1_TCK 131
145
+
#define PIN_JTAG1_TDI 132
146
+
#define PIN_JTAG1_TMS 133
147
+
#define PIN_JTAG1_TRST 134
148
+
#define PIN_JTAG1_SRST 135
149
+
#define PIN_JTAG2_TDO 136
150
+
#define PIN_JTAG2_TCK 137
151
+
#define PIN_JTAG2_TDI 138
152
+
#define PIN_JTAG2_TMS 139
153
+
#define PIN_JTAG2_TRST 140
154
+
#define PIN_JTAG2_SRST 141
155
+
#define PIN_JTAG3_TDO 142
156
+
#define PIN_JTAG3_TCK 143
157
+
#define PIN_JTAG3_TDI 144
158
+
#define PIN_JTAG3_TMS 145
159
+
#define PIN_JTAG3_TRST 146
160
+
#define PIN_JTAG3_SRST 147
161
+
#define PIN_GPIO0 148
162
+
#define PIN_GPIO1 149
163
+
#define PIN_GPIO2 150
164
+
#define PIN_GPIO3 151
165
+
#define PIN_GPIO4 152
166
+
#define PIN_GPIO5 153
167
+
#define PIN_GPIO6 154
168
+
#define PIN_GPIO7 155
169
+
#define PIN_GPIO8 156
170
+
#define PIN_GPIO9 157
171
+
#define PIN_GPIO10 158
172
+
#define PIN_GPIO11 159
173
+
#define PIN_GPIO12 160
174
+
#define PIN_GPIO13 161
175
+
#define PIN_GPIO14 162
176
+
#define PIN_GPIO15 163
177
+
#define PIN_GPIO16 164
178
+
#define PIN_GPIO17 165
179
+
#define PIN_GPIO18 166
180
+
#define PIN_GPIO19 167
181
+
#define PIN_GPIO20 168
182
+
#define PIN_GPIO21 169
183
+
#define PIN_GPIO22 170
184
+
#define PIN_GPIO23 171
185
+
#define PIN_GPIO24 172
186
+
#define PIN_GPIO25 173
187
+
#define PIN_GPIO26 174
188
+
#define PIN_GPIO27 175
189
+
#define PIN_GPIO28 176
190
+
#define PIN_GPIO29 177
191
+
#define PIN_GPIO30 178
192
+
#define PIN_GPIO31 179
193
+
#define PIN_MODE_SEL0 180
194
+
#define PIN_MODE_SEL1 181
195
+
#define PIN_MODE_SEL2 182
196
+
#define PIN_BOOT_SEL0 183
197
+
#define PIN_BOOT_SEL1 184
198
+
#define PIN_BOOT_SEL2 185
199
+
#define PIN_BOOT_SEL3 186
200
+
#define PIN_BOOT_SEL4 187
201
+
#define PIN_BOOT_SEL5 188
202
+
#define PIN_BOOT_SEL6 189
203
+
#define PIN_BOOT_SEL7 190
204
+
#define PIN_MULTI_SCKT 191
205
+
#define PIN_SCKT_ID0 192
206
+
#define PIN_SCKT_ID1 193
207
+
#define PIN_PLL_CLK_IN_MAIN 194
208
+
#define PIN_PLL_CLK_IN_DDR_0 195
209
+
#define PIN_PLL_CLK_IN_DDR_1 196
210
+
#define PIN_PLL_CLK_IN_DDR_2 197
211
+
#define PIN_PLL_CLK_IN_DDR_3 198
212
+
#define PIN_XTAL_32K 199
213
+
#define PIN_SYS_RST 200
214
+
#define PIN_PWR_BUTTON 201
215
+
#define PIN_TEST_EN 202
216
+
#define PIN_TEST_MODE_MBIST 203
217
+
#define PIN_TEST_MODE_SCAN 204
218
+
#define PIN_TEST_MODE_BSD 205
219
+
#define PIN_BISR_BYP 206
220
+
221
+
#endif /* _DT_BINDINGS_PINCTRL_SG2044_H */