tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clocksource: exynos_mct: Use readl_relaxed/writel_relaxed

Using the __raw functions is discouraged. Update the file to
consistently use the proper functions.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

authored by

Doug Anderson and committed by
Daniel Lezcano fdb06f66 a38b1f60

+12 -12
+12 -12
drivers/clocksource/exynos_mct.c
··· 94 94 u32 mask; 95 95 u32 i; 96 96 97 - __raw_writel(value, reg_base + offset); 97 + writel_relaxed(value, reg_base + offset); 98 98 99 99 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { 100 100 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; ··· 144 144 145 145 /* Wait maximum 1 ms until written values are applied */ 146 146 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) 147 - if (__raw_readl(reg_base + stat_addr) & mask) { 148 - __raw_writel(mask, reg_base + stat_addr); 147 + if (readl_relaxed(reg_base + stat_addr) & mask) { 148 + writel_relaxed(mask, reg_base + stat_addr); 149 149 return; 150 150 } 151 151 ··· 157 157 { 158 158 u32 reg; 159 159 160 - reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); 160 + reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 161 161 reg |= MCT_G_TCON_START; 162 162 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); 163 163 } ··· 165 165 static cycle_t notrace _exynos4_frc_read(void) 166 166 { 167 167 unsigned int lo, hi; 168 - u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); 168 + u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); 169 169 170 170 do { 171 171 hi = hi2; 172 - lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L); 173 - hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); 172 + lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); 173 + hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); 174 174 } while (hi != hi2); 175 175 176 176 return ((cycle_t)hi << 32) | lo; ··· 225 225 { 226 226 unsigned int tcon; 227 227 228 - tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); 228 + tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 229 229 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); 230 230 231 231 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); ··· 238 238 unsigned int tcon; 239 239 cycle_t comp_cycle; 240 240 241 - tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); 241 + tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 242 242 243 243 if (mode == CLOCK_EVT_MODE_PERIODIC) { 244 244 tcon |= MCT_G_TCON_COMP0_AUTO_INC; ··· 327 327 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; 328 328 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; 329 329 330 - tmp = __raw_readl(reg_base + offset); 330 + tmp = readl_relaxed(reg_base + offset); 331 331 if (tmp & mask) { 332 332 tmp &= ~mask; 333 333 exynos4_mct_write(tmp, offset); ··· 349 349 /* enable MCT tick interrupt */ 350 350 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); 351 351 352 - tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET); 352 + tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); 353 353 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | 354 354 MCT_L_TCON_INTERVAL_MODE; 355 355 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); ··· 401 401 exynos4_mct_tick_stop(mevt); 402 402 403 403 /* Clear the MCT tick interrupt */ 404 - if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { 404 + if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { 405 405 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); 406 406 return 1; 407 407 } else {