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drm/i915/display: include intel_display_reg_defs.h from display regs files

Some display register files include i915_reg_defs.h, some don't include
anything. Prefer intel_display_reg_defs.h in display.

Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Link: https://lore.kernel.org/r/06c24e1f6a7a2f6b4801b0a079eec3cc924402a7.1749469962.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Jani Nikula fd585ee8 5f105b2e

+9 -7
+1 -1
drivers/gpu/drm/i915/display/intel_cmtg_regs.h
··· 6 6 #ifndef __INTEL_CMTG_REGS_H__ 7 7 #define __INTEL_CMTG_REGS_H__ 8 8 9 - #include "i915_reg_defs.h" 9 + #include "intel_display_reg_defs.h" 10 10 11 11 #define CMTG_CLK_SEL _MMIO(0x46160) 12 12 #define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29)
+1 -1
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
··· 6 6 #ifndef __INTEL_COMBO_PHY_REGS__ 7 7 #define __INTEL_COMBO_PHY_REGS__ 8 8 9 - #include "i915_reg_defs.h" 9 + #include "intel_display_reg_defs.h" 10 10 11 11 #define _ICL_COMBOPHY_A 0x162000 12 12 #define _ICL_COMBOPHY_B 0x6C000
+1 -1
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
··· 6 6 #ifndef __INTEL_CX0_PHY_REGS_H__ 7 7 #define __INTEL_CX0_PHY_REGS_H__ 8 8 9 - #include "i915_reg_defs.h" 10 9 #include "intel_display_limits.h" 10 + #include "intel_display_reg_defs.h" 11 11 12 12 /* DDI Buffer Control */ 13 13 #define _DDI_CLK_VALFREQ_A 0x64030
+2
drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
··· 8 8 9 9 #include <linux/types.h> 10 10 11 + #include "intel_display_reg_defs.h" 12 + 11 13 struct intel_dkl_phy_reg { 12 14 u32 reg:24; 13 15 u32 bank_idx:4;
+1 -1
drivers/gpu/drm/i915/display/intel_dmc_regs.h
··· 6 6 #ifndef __INTEL_DMC_REGS_H__ 7 7 #define __INTEL_DMC_REGS_H__ 8 8 9 - #include "i915_reg_defs.h" 9 + #include "intel_display_reg_defs.h" 10 10 11 11 enum dmc_event_id { 12 12 DMC_EVENT_TRUE = 0x0,
+1 -1
drivers/gpu/drm/i915/display/intel_gmbus_regs.h
··· 6 6 #ifndef __INTEL_GMBUS_REGS_H__ 7 7 #define __INTEL_GMBUS_REGS_H__ 8 8 9 - #include "i915_reg_defs.h" 9 + #include "intel_display_reg_defs.h" 10 10 11 11 #define __GMBUS_MMIO_BASE(__display) ((__display)->gmbus.mmio_base) 12 12
+1 -1
drivers/gpu/drm/i915/display/intel_hti_regs.h
··· 6 6 #ifndef __INTEL_HTI_REGS_H__ 7 7 #define __INTEL_HTI_REGS_H__ 8 8 9 - #include "i915_reg_defs.h" 9 + #include "intel_display_reg_defs.h" 10 10 11 11 #define HDPORT_STATE _MMIO(0x45050) 12 12 #define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
+1 -1
drivers/gpu/drm/i915/display/intel_sbi_regs.h
··· 4 4 #ifndef __INTEL_SBI_REGS_H__ 5 5 #define __INTEL_SBI_REGS_H__ 6 6 7 - #include "i915_reg_defs.h" 7 + #include "intel_display_reg_defs.h" 8 8 9 9 /* 10 10 * Sideband Interface (SBI) is programmed indirectly, via SBI_ADDR, which