tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: rockchip: Add RV1126 pinctrl support
RV1126 has five GPIOs groups - GPIO0 in PD_MMU and GPIO1-4
in PD_BUS.
In GPIO0, up to Lower C group GPIO0_C[3:0] is part of PMU
but rest of the groups from there are part of GRF.
Added pinctrl support for RV1126 and the pull, drv and schmitt
calculations are inferred from [1] authored by Jianqun Xu.
[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/pinctrl/pinctrl-rockchip.c
Cc: linux-gpio@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20220818124132.125304-8-jagan@edgeble.ai
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Jagan Teki
and committed by
Linus Walleij
fd4ea486
2dce5027
+327
-7
+326
-7
drivers/pinctrl/pinctrl-rockchip.c
+326
-7
drivers/pinctrl/pinctrl-rockchip.c
···
57
57
#define IOMUX_UNROUTED BIT(3)
58
58
#define IOMUX_WIDTH_3BIT BIT(4)
59
59
#define IOMUX_WIDTH_2BIT BIT(5)
60
+
#define IOMUX_L_SOURCE_PMU BIT(6)
60
61
61
62
#define PIN_BANK(id, pins, label) \
62
63
{ \
···
146
145
.pull_type[1] = pull1, \
147
146
.pull_type[2] = pull2, \
148
147
.pull_type[3] = pull3, \
148
+
}
149
+
150
+
#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
151
+
iom3, offset0, offset1, offset2, \
152
+
offset3) \
153
+
{ \
154
+
.bank_num = id, \
155
+
.nr_pins = pins, \
156
+
.name = label, \
157
+
.iomux = { \
158
+
{ .type = iom0, .offset = offset0 }, \
159
+
{ .type = iom1, .offset = offset1 }, \
160
+
{ .type = iom2, .offset = offset2 }, \
161
+
{ .type = iom3, .offset = offset3 }, \
162
+
}, \
149
163
}
150
164
151
165
#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
···
459
443
},
460
444
};
461
445
446
+
static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
447
+
{
448
+
.num = 0,
449
+
.pin = 20,
450
+
.reg = 0x10000,
451
+
.bit = 0,
452
+
.mask = 0xf
453
+
},
454
+
{
455
+
.num = 0,
456
+
.pin = 21,
457
+
.reg = 0x10000,
458
+
.bit = 4,
459
+
.mask = 0xf
460
+
},
461
+
{
462
+
.num = 0,
463
+
.pin = 22,
464
+
.reg = 0x10000,
465
+
.bit = 8,
466
+
.mask = 0xf
467
+
},
468
+
{
469
+
.num = 0,
470
+
.pin = 23,
471
+
.reg = 0x10000,
472
+
.bit = 12,
473
+
.mask = 0xf
474
+
},
475
+
};
476
+
462
477
static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
463
478
{
464
479
.num = 2,
···
687
640
RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
688
641
RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
689
642
RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
643
+
};
644
+
645
+
static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
646
+
RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
647
+
RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
648
+
649
+
RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
650
+
RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
651
+
RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
652
+
653
+
RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
654
+
RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
655
+
656
+
RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
657
+
RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
658
+
659
+
RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
660
+
RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
661
+
662
+
RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
663
+
RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
664
+
RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
665
+
666
+
RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
667
+
RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
668
+
669
+
RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
670
+
RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
671
+
RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
672
+
673
+
RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
674
+
RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
675
+
RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
676
+
677
+
RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
678
+
RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
679
+
680
+
RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
681
+
RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
682
+
683
+
RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
684
+
RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
685
+
686
+
RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
687
+
RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
688
+
689
+
RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
690
+
RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
691
+
692
+
RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
693
+
RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
694
+
695
+
RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
696
+
RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
697
+
698
+
RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
699
+
RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
700
+
RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
701
+
702
+
RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
703
+
RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
704
+
RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
705
+
706
+
RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
707
+
RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
708
+
RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
709
+
710
+
RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
711
+
RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
712
+
713
+
RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
714
+
RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
715
+
716
+
RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
717
+
RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
718
+
719
+
RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
720
+
RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
721
+
722
+
RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
723
+
RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
724
+
725
+
RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
726
+
RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
727
+
728
+
RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
729
+
RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
730
+
731
+
RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
732
+
RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
733
+
734
+
RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
735
+
RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
736
+
RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
737
+
738
+
RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
739
+
RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
690
740
};
691
741
692
742
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
···
1021
877
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1022
878
return RK_FUNC_GPIO;
1023
879
1024
-
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1025
-
? info->regmap_pmu : info->regmap_base;
880
+
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
881
+
regmap = info->regmap_pmu;
882
+
else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
883
+
regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
884
+
else
885
+
regmap = info->regmap_base;
1026
886
1027
887
/* get basic quadrupel of mux registers and the correct reg inside */
1028
888
mux_type = bank->iomux[iomux_num].type;
···
1135
987
1136
988
dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1137
989
1138
-
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1139
-
? info->regmap_pmu : info->regmap_base;
990
+
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
991
+
regmap = info->regmap_pmu;
992
+
else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
993
+
regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
994
+
else
995
+
regmap = info->regmap_base;
1140
996
1141
997
/* get basic quadrupel of mux registers and the correct reg inside */
1142
998
mux_type = bank->iomux[iomux_num].type;
···
1413
1261
*reg = RV1108_SCHMITT_GRF_OFFSET;
1414
1262
pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1415
1263
*reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1264
+
}
1265
+
*reg += ((pin_num / pins_per_reg) * 4);
1266
+
*bit = pin_num % pins_per_reg;
1267
+
1268
+
return 0;
1269
+
}
1270
+
1271
+
#define RV1126_PULL_PMU_OFFSET 0x40
1272
+
#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
1273
+
#define RV1126_PULL_PINS_PER_REG 8
1274
+
#define RV1126_PULL_BITS_PER_PIN 2
1275
+
#define RV1126_PULL_BANK_STRIDE 16
1276
+
#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1277
+
1278
+
static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1279
+
int pin_num, struct regmap **regmap,
1280
+
int *reg, u8 *bit)
1281
+
{
1282
+
struct rockchip_pinctrl *info = bank->drvdata;
1283
+
1284
+
/* The first 24 pins of the first bank are located in PMU */
1285
+
if (bank->bank_num == 0) {
1286
+
if (RV1126_GPIO_C4_D7(pin_num)) {
1287
+
*regmap = info->regmap_base;
1288
+
*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1289
+
*reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
1290
+
*bit = pin_num % RV1126_PULL_PINS_PER_REG;
1291
+
*bit *= RV1126_PULL_BITS_PER_PIN;
1292
+
return 0;
1293
+
}
1294
+
*regmap = info->regmap_pmu;
1295
+
*reg = RV1126_PULL_PMU_OFFSET;
1296
+
} else {
1297
+
*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1298
+
*regmap = info->regmap_base;
1299
+
*reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
1300
+
}
1301
+
1302
+
*reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
1303
+
*bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1304
+
*bit *= RV1126_PULL_BITS_PER_PIN;
1305
+
1306
+
return 0;
1307
+
}
1308
+
1309
+
#define RV1126_DRV_PMU_OFFSET 0x20
1310
+
#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
1311
+
#define RV1126_DRV_BITS_PER_PIN 4
1312
+
#define RV1126_DRV_PINS_PER_REG 4
1313
+
#define RV1126_DRV_BANK_STRIDE 32
1314
+
1315
+
static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1316
+
int pin_num, struct regmap **regmap,
1317
+
int *reg, u8 *bit)
1318
+
{
1319
+
struct rockchip_pinctrl *info = bank->drvdata;
1320
+
1321
+
/* The first 24 pins of the first bank are located in PMU */
1322
+
if (bank->bank_num == 0) {
1323
+
if (RV1126_GPIO_C4_D7(pin_num)) {
1324
+
*regmap = info->regmap_base;
1325
+
*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1326
+
*reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
1327
+
*reg -= 0x4;
1328
+
*bit = pin_num % RV1126_DRV_PINS_PER_REG;
1329
+
*bit *= RV1126_DRV_BITS_PER_PIN;
1330
+
return 0;
1331
+
}
1332
+
*regmap = info->regmap_pmu;
1333
+
*reg = RV1126_DRV_PMU_OFFSET;
1334
+
} else {
1335
+
*regmap = info->regmap_base;
1336
+
*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1337
+
*reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
1338
+
}
1339
+
1340
+
*reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
1341
+
*bit = pin_num % RV1126_DRV_PINS_PER_REG;
1342
+
*bit *= RV1126_DRV_BITS_PER_PIN;
1343
+
1344
+
return 0;
1345
+
}
1346
+
1347
+
#define RV1126_SCHMITT_PMU_OFFSET 0x60
1348
+
#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
1349
+
#define RV1126_SCHMITT_BANK_STRIDE 16
1350
+
#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
1351
+
#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
1352
+
1353
+
static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1354
+
int pin_num,
1355
+
struct regmap **regmap,
1356
+
int *reg, u8 *bit)
1357
+
{
1358
+
struct rockchip_pinctrl *info = bank->drvdata;
1359
+
int pins_per_reg;
1360
+
1361
+
if (bank->bank_num == 0) {
1362
+
if (RV1126_GPIO_C4_D7(pin_num)) {
1363
+
*regmap = info->regmap_base;
1364
+
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1365
+
*reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
1366
+
*bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
1367
+
return 0;
1368
+
}
1369
+
*regmap = info->regmap_pmu;
1370
+
*reg = RV1126_SCHMITT_PMU_OFFSET;
1371
+
pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
1372
+
} else {
1373
+
*regmap = info->regmap_base;
1374
+
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1375
+
pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
1376
+
*reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
1416
1377
}
1417
1378
*reg += ((pin_num / pins_per_reg) * 4);
1418
1379
*bit = pin_num % pins_per_reg;
···
2263
1998
goto config;
2264
1999
}
2265
2000
2001
+
if (ctrl->type == RV1126) {
2002
+
rmask_bits = RV1126_DRV_BITS_PER_PIN;
2003
+
ret = strength;
2004
+
goto config;
2005
+
}
2006
+
2266
2007
ret = -EINVAL;
2267
2008
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2268
2009
if (rockchip_perpin_drv_list[drv_type][i] == strength) {
···
2439
2168
break;
2440
2169
case PX30:
2441
2170
case RV1108:
2171
+
case RV1126:
2442
2172
case RK3188:
2443
2173
case RK3288:
2444
2174
case RK3308:
···
2688
2416
return pull ? false : true;
2689
2417
case PX30:
2690
2418
case RV1108:
2419
+
case RV1126:
2691
2420
case RK3188:
2692
2421
case RK3288:
2693
2422
case RK3308:
···
3162
2889
3163
2890
/* preset iomux offset value, set new start value */
3164
2891
if (iom->offset >= 0) {
3165
-
if (iom->type & IOMUX_SOURCE_PMU)
2892
+
if ((iom->type & IOMUX_SOURCE_PMU) ||
2893
+
(iom->type & IOMUX_L_SOURCE_PMU))
3166
2894
pmu_offs = iom->offset;
3167
2895
else
3168
2896
grf_offs = iom->offset;
3169
2897
} else { /* set current iomux offset */
3170
-
iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2898
+
iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
2899
+
(iom->type & IOMUX_L_SOURCE_PMU)) ?
3171
2900
pmu_offs : grf_offs;
3172
2901
}
3173
2902
···
3194
2919
inc = (iom->type & (IOMUX_WIDTH_4BIT |
3195
2920
IOMUX_WIDTH_3BIT |
3196
2921
IOMUX_WIDTH_2BIT)) ? 8 : 4;
3197
-
if (iom->type & IOMUX_SOURCE_PMU)
2922
+
if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
3198
2923
pmu_offs += inc;
3199
2924
else
3200
2925
grf_offs += inc;
···
3451
3176
.pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3452
3177
.drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3453
3178
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3179
+
};
3180
+
3181
+
static struct rockchip_pin_bank rv1126_pin_banks[] = {
3182
+
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3183
+
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3184
+
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3185
+
IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
3186
+
IOMUX_WIDTH_4BIT),
3187
+
PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
3188
+
IOMUX_WIDTH_4BIT,
3189
+
IOMUX_WIDTH_4BIT,
3190
+
IOMUX_WIDTH_4BIT,
3191
+
IOMUX_WIDTH_4BIT,
3192
+
0x10010, 0x10018, 0x10020, 0x10028),
3193
+
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
3194
+
IOMUX_WIDTH_4BIT,
3195
+
IOMUX_WIDTH_4BIT,
3196
+
IOMUX_WIDTH_4BIT,
3197
+
IOMUX_WIDTH_4BIT),
3198
+
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3199
+
IOMUX_WIDTH_4BIT,
3200
+
IOMUX_WIDTH_4BIT,
3201
+
IOMUX_WIDTH_4BIT,
3202
+
IOMUX_WIDTH_4BIT),
3203
+
PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
3204
+
IOMUX_WIDTH_4BIT, 0, 0, 0),
3205
+
};
3206
+
3207
+
static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
3208
+
.pin_banks = rv1126_pin_banks,
3209
+
.nr_banks = ARRAY_SIZE(rv1126_pin_banks),
3210
+
.label = "RV1126-GPIO",
3211
+
.type = RV1126,
3212
+
.grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
3213
+
.pmu_mux_offset = 0x0,
3214
+
.iomux_routes = rv1126_mux_route_data,
3215
+
.niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
3216
+
.iomux_recalced = rv1126_mux_recalced_data,
3217
+
.niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
3218
+
.pull_calc_reg = rv1126_calc_pull_reg_and_bit,
3219
+
.drv_calc_reg = rv1126_calc_drv_reg_and_bit,
3220
+
.schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
3454
3221
};
3455
3222
3456
3223
static struct rockchip_pin_bank rk2928_pin_banks[] = {
···
3885
3568
.data = &px30_pin_ctrl },
3886
3569
{ .compatible = "rockchip,rv1108-pinctrl",
3887
3570
.data = &rv1108_pin_ctrl },
3571
+
{ .compatible = "rockchip,rv1126-pinctrl",
3572
+
.data = &rv1126_pin_ctrl },
3888
3573
{ .compatible = "rockchip,rk2928-pinctrl",
3889
3574
.data = &rk2928_pin_ctrl },
3890
3575
{ .compatible = "rockchip,rk3036-pinctrl",