PCI: Separate CardBus setup & build it only with CONFIG_CARDBUS

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

PCI bridge window setup code includes special code to handle CardBus
bridges. CardBus has long since fallen out of favor and modern systems have
no use for it.

Move CardBus setup code to its own file and use existing CONFIG_CARDBUS to
decide whether it should be built or not.

Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20251219174036.16738-18-ilpo.jarvinen@linux.intel.com

authored by

Ilpo Järvinen and committed by

Bjorn Helgaas 2 months ago fd29d4ea b398665a

+202 -168

6 changed files

expand all

drivers

pci

Makefile

pci.h

setup-bus.c

setup-cardbus.c

pcmcia

yenta_socket.c

include

linux

pci.h

drivers/pci/Makefile

··· 39 39 obj-$(CONFIG_PCI_DYNAMIC_OF_NODES) += of_property.o 40 40 obj-$(CONFIG_PCI_NPEM) += npem.o 41 41 obj-$(CONFIG_PCIE_TPH) += tph.o 42 + obj-$(CONFIG_CARDBUS) += setup-cardbus.o 42 43 43 44 # Endpoint library must be initialized before its users 44 45 obj-$(CONFIG_PCI_ENDPOINT) += endpoint/

+21 -2

drivers/pci/pci.h

··· 379 379 extern unsigned long pci_cardbus_io_size; 380 380 extern unsigned long pci_cardbus_mem_size; 381 381 382 + #ifdef CONFIG_CARDBUS 383 + unsigned long pci_cardbus_resource_alignment(struct resource *res); 384 + int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 385 + struct list_head *realloc_head); 386 + 387 + #else 388 + static inline unsigned long pci_cardbus_resource_alignment(struct resource *res) 389 + { 390 + return 0; 391 + } 392 + static inline int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 393 + struct list_head *realloc_head) 394 + { 395 + return -EOPNOTSUPP; 396 + } 397 + #endif /* CONFIG_CARDBUS */ 398 + 382 399 /** 383 400 * pci_match_one_device - Tell if a PCI device structure has a matching 384 401 * PCI device id structure ··· 457 440 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 458 441 struct resource *res, unsigned int reg, u32 *sizes); 459 442 void pci_configure_ari(struct pci_dev *dev); 443 + 444 + int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, 445 + struct resource *res, resource_size_t add_size, 446 + resource_size_t min_align); 460 447 void __pci_bus_size_bridges(struct pci_bus *bus, 461 448 struct list_head *realloc_head); 462 449 void __pci_bus_assign_resources(const struct pci_bus *bus, ··· 949 928 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 950 929 static inline void pci_resume_ptm(struct pci_dev *dev) { } 951 930 #endif 952 - 953 - unsigned long pci_cardbus_resource_alignment(struct resource *); 954 931 955 932 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 956 933 struct resource *res)

+7 -164

drivers/pci/setup-bus.c

··· 67 67 * @add_size: Additional size to be optionally added to the resource 68 68 * @min_align: Minimum memory window alignment 69 69 */ 70 - static int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, 71 - struct resource *res, 72 - resource_size_t add_size, 73 - resource_size_t min_align) 70 + int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, 71 + struct resource *res, resource_size_t add_size, 72 + resource_size_t min_align) 74 73 { 75 74 struct pci_dev_resource *tmp; 76 75 ··· 772 773 __assign_resources_sorted(&head, realloc_head, fail_head); 773 774 } 774 775 775 - void pci_setup_cardbus(struct pci_bus *bus) 776 - { 777 - struct pci_dev *bridge = bus->self; 778 - struct resource *res; 779 - struct pci_bus_region region; 780 - 781 - pci_info(bridge, "CardBus bridge to %pR\n", 782 - &bus->busn_res); 783 - 784 - res = bus->resource[0]; 785 - pcibios_resource_to_bus(bridge->bus, &region, res); 786 - if (resource_assigned(res) && res->flags & IORESOURCE_IO) { 787 - /* 788 - * The IO resource is allocated a range twice as large as it 789 - * would normally need. This allows us to set both IO regs. 790 - */ 791 - pci_info(bridge, " bridge window %pR\n", res); 792 - pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 793 - region.start); 794 - pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 795 - region.end); 796 - } 797 - 798 - res = bus->resource[1]; 799 - pcibios_resource_to_bus(bridge->bus, &region, res); 800 - if (resource_assigned(res) && res->flags & IORESOURCE_IO) { 801 - pci_info(bridge, " bridge window %pR\n", res); 802 - pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 803 - region.start); 804 - pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 805 - region.end); 806 - } 807 - 808 - res = bus->resource[2]; 809 - pcibios_resource_to_bus(bridge->bus, &region, res); 810 - if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { 811 - pci_info(bridge, " bridge window %pR\n", res); 812 - pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 813 - region.start); 814 - pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 815 - region.end); 816 - } 817 - 818 - res = bus->resource[3]; 819 - pcibios_resource_to_bus(bridge->bus, &region, res); 820 - if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { 821 - pci_info(bridge, " bridge window %pR\n", res); 822 - pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 823 - region.start); 824 - pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 825 - region.end); 826 - } 827 - } 828 - EXPORT_SYMBOL(pci_setup_cardbus); 829 - 830 776 /* 831 777 * Initialize bridges with base/limit values we have collected. PCI-to-PCI 832 778 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there ··· 1368 1424 } 1369 1425 } 1370 1426 1371 - unsigned long pci_cardbus_resource_alignment(struct resource *res) 1372 - { 1373 - if (res->flags & IORESOURCE_IO) 1374 - return pci_cardbus_io_size; 1375 - if (res->flags & IORESOURCE_MEM) 1376 - return pci_cardbus_mem_size; 1377 - return 0; 1378 - } 1379 - 1380 - static void pci_bus_size_cardbus(struct pci_bus *bus, 1381 - struct list_head *realloc_head) 1382 - { 1383 - struct pci_dev *bridge = bus->self; 1384 - struct resource *b_res; 1385 - resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; 1386 - u16 ctrl; 1387 - 1388 - b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; 1389 - if (resource_assigned(b_res)) 1390 - goto handle_b_res_1; 1391 - /* 1392 - * Reserve some resources for CardBus. We reserve a fixed amount 1393 - * of bus space for CardBus bridges. 1394 - */ 1395 - resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 1396 - b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1397 - if (realloc_head) { 1398 - b_res->end -= pci_cardbus_io_size; 1399 - pci_dev_res_add_to_list(realloc_head, bridge, b_res, 1400 - pci_cardbus_io_size, 1401 - pci_cardbus_io_size); 1402 - } 1403 - 1404 - handle_b_res_1: 1405 - b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; 1406 - if (resource_assigned(b_res)) 1407 - goto handle_b_res_2; 1408 - resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 1409 - b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1410 - if (realloc_head) { 1411 - b_res->end -= pci_cardbus_io_size; 1412 - pci_dev_res_add_to_list(realloc_head, bridge, b_res, 1413 - pci_cardbus_io_size, 1414 - pci_cardbus_io_size); 1415 - } 1416 - 1417 - handle_b_res_2: 1418 - /* MEM1 must not be pref MMIO */ 1419 - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1420 - if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { 1421 - ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; 1422 - pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1423 - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1424 - } 1425 - 1426 - /* Check whether prefetchable memory is supported by this bridge. */ 1427 - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1428 - if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 1429 - ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 1430 - pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1431 - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1432 - } 1433 - 1434 - b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; 1435 - if (resource_assigned(b_res)) 1436 - goto handle_b_res_3; 1437 - /* 1438 - * If we have prefetchable memory support, allocate two regions. 1439 - * Otherwise, allocate one region of twice the size. 1440 - */ 1441 - if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 1442 - resource_set_range(b_res, pci_cardbus_mem_size, 1443 - pci_cardbus_mem_size); 1444 - b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | 1445 - IORESOURCE_STARTALIGN; 1446 - if (realloc_head) { 1447 - b_res->end -= pci_cardbus_mem_size; 1448 - pci_dev_res_add_to_list(realloc_head, bridge, b_res, 1449 - pci_cardbus_mem_size, 1450 - pci_cardbus_mem_size); 1451 - } 1452 - 1453 - /* Reduce that to half */ 1454 - b_res_3_size = pci_cardbus_mem_size; 1455 - } 1456 - 1457 - handle_b_res_3: 1458 - b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; 1459 - if (resource_assigned(b_res)) 1460 - goto handle_done; 1461 - resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size); 1462 - b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; 1463 - if (realloc_head) { 1464 - b_res->end -= b_res_3_size; 1465 - pci_dev_res_add_to_list(realloc_head, bridge, b_res, 1466 - b_res_3_size, pci_cardbus_mem_size); 1467 - } 1468 - 1469 - handle_done: 1470 - ; 1471 - } 1472 - 1473 1427 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) 1474 1428 { 1475 1429 struct pci_dev *dev; ··· 1384 1542 1385 1543 switch (dev->hdr_type) { 1386 1544 case PCI_HEADER_TYPE_CARDBUS: 1387 - pci_bus_size_cardbus(b, realloc_head); 1545 + if (pci_bus_size_cardbus_bridge(b, realloc_head)) 1546 + continue; 1388 1547 break; 1389 1548 1390 1549 case PCI_HEADER_TYPE_BRIDGE: ··· 1509 1666 break; 1510 1667 1511 1668 case PCI_HEADER_TYPE_CARDBUS: 1512 - pci_setup_cardbus(b); 1669 + pci_setup_cardbus_bridge(b); 1513 1670 break; 1514 1671 1515 1672 default: ··· 1614 1771 break; 1615 1772 1616 1773 case PCI_CLASS_BRIDGE_CARDBUS: 1617 - pci_setup_cardbus(b); 1774 + pci_setup_cardbus_bridge(b); 1618 1775 break; 1619 1776 1620 1777 default:

+167

drivers/pci/setup-cardbus.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Cardbus bridge setup routines. 4 + */ 5 + 6 + #include <linux/ioport.h> 7 + #include <linux/pci.h> 8 + #include <linux/types.h> 9 + 10 + #include "pci.h" 11 + 12 + unsigned long pci_cardbus_resource_alignment(struct resource *res) 13 + { 14 + if (res->flags & IORESOURCE_IO) 15 + return pci_cardbus_io_size; 16 + if (res->flags & IORESOURCE_MEM) 17 + return pci_cardbus_mem_size; 18 + return 0; 19 + } 20 + 21 + int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 22 + struct list_head *realloc_head) 23 + { 24 + struct pci_dev *bridge = bus->self; 25 + struct resource *b_res; 26 + resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; 27 + u16 ctrl; 28 + 29 + b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; 30 + if (resource_assigned(b_res)) 31 + goto handle_b_res_1; 32 + /* 33 + * Reserve some resources for CardBus. We reserve a fixed amount 34 + * of bus space for CardBus bridges. 35 + */ 36 + resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 37 + b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 38 + if (realloc_head) { 39 + b_res->end -= pci_cardbus_io_size; 40 + pci_dev_res_add_to_list(realloc_head, bridge, b_res, 41 + pci_cardbus_io_size, 42 + pci_cardbus_io_size); 43 + } 44 + 45 + handle_b_res_1: 46 + b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; 47 + if (resource_assigned(b_res)) 48 + goto handle_b_res_2; 49 + resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 50 + b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 51 + if (realloc_head) { 52 + b_res->end -= pci_cardbus_io_size; 53 + pci_dev_res_add_to_list(realloc_head, bridge, b_res, 54 + pci_cardbus_io_size, 55 + pci_cardbus_io_size); 56 + } 57 + 58 + handle_b_res_2: 59 + /* MEM1 must not be pref MMIO */ 60 + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 61 + if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { 62 + ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; 63 + pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 64 + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 65 + } 66 + 67 + /* Check whether prefetchable memory is supported by this bridge. */ 68 + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 69 + if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 70 + ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 71 + pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 72 + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 73 + } 74 + 75 + b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; 76 + if (resource_assigned(b_res)) 77 + goto handle_b_res_3; 78 + /* 79 + * If we have prefetchable memory support, allocate two regions. 80 + * Otherwise, allocate one region of twice the size. 81 + */ 82 + if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 83 + resource_set_range(b_res, pci_cardbus_mem_size, 84 + pci_cardbus_mem_size); 85 + b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | 86 + IORESOURCE_STARTALIGN; 87 + if (realloc_head) { 88 + b_res->end -= pci_cardbus_mem_size; 89 + pci_dev_res_add_to_list(realloc_head, bridge, b_res, 90 + pci_cardbus_mem_size, 91 + pci_cardbus_mem_size); 92 + } 93 + 94 + /* Reduce that to half */ 95 + b_res_3_size = pci_cardbus_mem_size; 96 + } 97 + 98 + handle_b_res_3: 99 + b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; 100 + if (resource_assigned(b_res)) 101 + goto handle_done; 102 + resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size); 103 + b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; 104 + if (realloc_head) { 105 + b_res->end -= b_res_3_size; 106 + pci_dev_res_add_to_list(realloc_head, bridge, b_res, 107 + b_res_3_size, pci_cardbus_mem_size); 108 + } 109 + 110 + handle_done: 111 + return 0; 112 + } 113 + 114 + void pci_setup_cardbus_bridge(struct pci_bus *bus) 115 + { 116 + struct pci_dev *bridge = bus->self; 117 + struct resource *res; 118 + struct pci_bus_region region; 119 + 120 + pci_info(bridge, "CardBus bridge to %pR\n", 121 + &bus->busn_res); 122 + 123 + res = bus->resource[0]; 124 + pcibios_resource_to_bus(bridge->bus, &region, res); 125 + if (resource_assigned(res) && res->flags & IORESOURCE_IO) { 126 + /* 127 + * The IO resource is allocated a range twice as large as it 128 + * would normally need. This allows us to set both IO regs. 129 + */ 130 + pci_info(bridge, " bridge window %pR\n", res); 131 + pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 132 + region.start); 133 + pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 134 + region.end); 135 + } 136 + 137 + res = bus->resource[1]; 138 + pcibios_resource_to_bus(bridge->bus, &region, res); 139 + if (resource_assigned(res) && res->flags & IORESOURCE_IO) { 140 + pci_info(bridge, " bridge window %pR\n", res); 141 + pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 142 + region.start); 143 + pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 144 + region.end); 145 + } 146 + 147 + res = bus->resource[2]; 148 + pcibios_resource_to_bus(bridge->bus, &region, res); 149 + if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { 150 + pci_info(bridge, " bridge window %pR\n", res); 151 + pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 152 + region.start); 153 + pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 154 + region.end); 155 + } 156 + 157 + res = bus->resource[3]; 158 + pcibios_resource_to_bus(bridge->bus, &region, res); 159 + if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { 160 + pci_info(bridge, " bridge window %pR\n", res); 161 + pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 162 + region.start); 163 + pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 164 + region.end); 165 + } 166 + } 167 + EXPORT_SYMBOL(pci_setup_cardbus_bridge);

+1 -1

drivers/pcmcia/yenta_socket.c

··· 779 779 IORESOURCE_MEM, 780 780 PCI_CB_MEMORY_BASE_1, PCI_CB_MEMORY_LIMIT_1); 781 781 if (program) 782 - pci_setup_cardbus(socket->dev->subordinate); 782 + pci_setup_cardbus_bridge(socket->dev->subordinate); 783 783 } 784 784 785 785

+5 -1

include/linux/pci.h

··· 1243 1243 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1244 1244 void pci_stop_root_bus(struct pci_bus *bus); 1245 1245 void pci_remove_root_bus(struct pci_bus *bus); 1246 - void pci_setup_cardbus(struct pci_bus *bus); 1246 + #ifdef CONFIG_CARDBUS 1247 + void pci_setup_cardbus_bridge(struct pci_bus *bus); 1248 + #else 1249 + static inline void pci_setup_cardbus_bridge(struct pci_bus *bus) { } 1250 + #endif 1247 1251 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1248 1252 void pci_sort_breadthfirst(void); 1249 1253 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)