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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
can: add Renesas R-Car CAN driver
Add support for the CAN controller found in Renesas R-Car SoCs.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
authored by
Sergei Shtylyov
and committed by
Marc Kleine-Budde
fd115931
a9c69209
+904
+10
drivers/net/can/Kconfig
+10
drivers/net/can/Kconfig
···
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endian syntheses of the cores would need some modifications on
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the hardware level to work.
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config CAN_RCAR
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tristate "Renesas R-Car CAN controller"
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depends on ARM
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---help---
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Say Y here if you want to use CAN controller found on Renesas R-Car
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SoCs.
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To compile this driver as a module, choose M here: the module will
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be called rcar_can.
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source "drivers/net/can/mscan/Kconfig"
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source "drivers/net/can/sja1000/Kconfig"
+1
drivers/net/can/Makefile
+1
drivers/net/can/Makefile
+876
drivers/net/can/rcar_can.c
+876
drivers/net/can/rcar_can.c
···
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/* Renesas R-Car CAN device driver
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*
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* Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com>
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/netdevice.h>
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#include <linux/platform_device.h>
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#include <linux/can/led.h>
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#include <linux/can/dev.h>
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#include <linux/clk.h>
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#include <linux/can/platform/rcar_can.h>
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+
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#define RCAR_CAN_DRV_NAME "rcar_can"
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+
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/* Mailbox configuration:
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* mailbox 60 - 63 - Rx FIFO mailboxes
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* mailbox 56 - 59 - Tx FIFO mailboxes
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* non-FIFO mailboxes are not used
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*/
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#define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */
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#define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */
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#define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */
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#define RCAR_CAN_FIFO_DEPTH 4
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/* Mailbox registers structure */
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struct rcar_can_mbox_regs {
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u32 id; /* IDE and RTR bits, SID and EID */
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u8 stub; /* Not used */
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u8 dlc; /* Data Length Code - bits [0..3] */
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u8 data[8]; /* Data Bytes */
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u8 tsh; /* Time Stamp Higher Byte */
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u8 tsl; /* Time Stamp Lower Byte */
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};
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struct rcar_can_regs {
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struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */
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u32 mkr_2_9[8]; /* Mask Registers 2-9 */
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u32 fidcr[2]; /* FIFO Received ID Compare Register */
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u32 mkivlr1; /* Mask Invalid Register 1 */
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u32 mier1; /* Mailbox Interrupt Enable Register 1 */
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u32 mkr_0_1[2]; /* Mask Registers 0-1 */
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u32 mkivlr0; /* Mask Invalid Register 0*/
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u32 mier0; /* Mailbox Interrupt Enable Register 0 */
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u8 pad_440[0x3c0];
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u8 mctl[64]; /* Message Control Registers */
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u16 ctlr; /* Control Register */
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u16 str; /* Status register */
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u8 bcr[3]; /* Bit Configuration Register */
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u8 clkr; /* Clock Select Register */
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u8 rfcr; /* Receive FIFO Control Register */
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u8 rfpcr; /* Receive FIFO Pointer Control Register */
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u8 tfcr; /* Transmit FIFO Control Register */
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u8 tfpcr; /* Transmit FIFO Pointer Control Register */
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u8 eier; /* Error Interrupt Enable Register */
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u8 eifr; /* Error Interrupt Factor Judge Register */
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u8 recr; /* Receive Error Count Register */
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u8 tecr; /* Transmit Error Count Register */
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u8 ecsr; /* Error Code Store Register */
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u8 cssr; /* Channel Search Support Register */
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u8 mssr; /* Mailbox Search Status Register */
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u8 msmr; /* Mailbox Search Mode Register */
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u16 tsr; /* Time Stamp Register */
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u8 afsr; /* Acceptance Filter Support Register */
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u8 pad_857;
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u8 tcr; /* Test Control Register */
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u8 pad_859[7];
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u8 ier; /* Interrupt Enable Register */
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u8 isr; /* Interrupt Status Register */
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u8 pad_862;
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u8 mbsmr; /* Mailbox Search Mask Register */
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};
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struct rcar_can_priv {
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struct can_priv can; /* Must be the first member! */
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struct net_device *ndev;
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struct napi_struct napi;
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struct rcar_can_regs __iomem *regs;
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struct clk *clk;
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u8 tx_dlc[RCAR_CAN_FIFO_DEPTH];
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u32 tx_head;
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u32 tx_tail;
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u8 clock_select;
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u8 ier;
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};
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static const struct can_bittiming_const rcar_can_bittiming_const = {
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.name = RCAR_CAN_DRV_NAME,
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.tseg1_min = 4,
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.tseg1_max = 16,
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.tseg2_min = 2,
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.tseg2_max = 8,
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.sjw_max = 4,
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.brp_min = 1,
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.brp_max = 1024,
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.brp_inc = 1,
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};
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/* Control Register bits */
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#define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */
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#define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */
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/* at bus-off entry */
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#define RCAR_CAN_CTLR_SLPM (1 << 10)
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#define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */
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#define RCAR_CAN_CTLR_CANM_HALT (1 << 9)
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#define RCAR_CAN_CTLR_CANM_RESET (1 << 8)
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#define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8)
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#define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */
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#define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */
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#define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */
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#define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */
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/* Status Register bits */
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#define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */
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/* FIFO Received ID Compare Registers 0 and 1 bits */
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#define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */
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#define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */
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/* Receive FIFO Control Register bits */
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#define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */
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#define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */
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/* Transmit FIFO Control Register bits */
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#define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */
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/* Number Status Bits */
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#define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */
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/* Message Number Status Bits */
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#define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */
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#define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */
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/* for Rx mailboxes 0-31 */
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#define RCAR_CAN_N_RX_MKREGS2 8
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/* Bit Configuration Register settings */
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#define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20)
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#define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8)
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#define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4)
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#define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07)
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/* Mailbox and Mask Registers bits */
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#define RCAR_CAN_IDE (1 << 31)
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#define RCAR_CAN_RTR (1 << 30)
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#define RCAR_CAN_SID_SHIFT 18
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/* Mailbox Interrupt Enable Register 1 bits */
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#define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */
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#define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */
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/* Interrupt Enable Register bits */
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#define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */
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#define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */
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/* Enable Bit */
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#define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */
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/* Enable Bit */
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/* Interrupt Status Register bits */
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#define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */
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#define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */
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/* Status Bit */
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#define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */
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/* Status Bit */
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/* Error Interrupt Enable Register bits */
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#define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */
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#define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */
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/* Interrupt Enable */
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#define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */
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#define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */
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#define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */
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#define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */
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#define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */
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#define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */
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/* Error Interrupt Factor Judge Register bits */
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#define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */
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#define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */
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/* Detect Flag */
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#define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */
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#define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */
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#define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */
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#define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */
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#define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */
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#define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */
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/* Error Code Store Register bits */
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#define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */
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#define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */
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#define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */
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#define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */
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#define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */
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#define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */
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#define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */
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#define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */
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#define RCAR_CAN_NAPI_WEIGHT 4
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#define MAX_STR_READS 0x100
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static void tx_failure_cleanup(struct net_device *ndev)
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{
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int i;
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for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++)
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can_free_echo_skb(ndev, i);
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}
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static void rcar_can_error(struct net_device *ndev)
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{
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struct rcar_can_priv *priv = netdev_priv(ndev);
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struct net_device_stats *stats = &ndev->stats;
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struct can_frame *cf;
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struct sk_buff *skb;
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u8 eifr, txerr = 0, rxerr = 0;
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/* Propagate the error condition to the CAN stack */
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skb = alloc_can_err_skb(ndev, &cf);
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eifr = readb(&priv->regs->eifr);
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if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) {
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txerr = readb(&priv->regs->tecr);
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rxerr = readb(&priv->regs->recr);
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if (skb) {
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cf->can_id |= CAN_ERR_CRTL;
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cf->data[6] = txerr;
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cf->data[7] = rxerr;
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}
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}
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if (eifr & RCAR_CAN_EIFR_BEIF) {
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int rx_errors = 0, tx_errors = 0;
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u8 ecsr;
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netdev_dbg(priv->ndev, "Bus error interrupt:\n");
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if (skb) {
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cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
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cf->data[2] = CAN_ERR_PROT_UNSPEC;
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}
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ecsr = readb(&priv->regs->ecsr);
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if (ecsr & RCAR_CAN_ECSR_ADEF) {
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netdev_dbg(priv->ndev, "ACK Delimiter Error\n");
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tx_errors++;
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writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr);
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if (skb)
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cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
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}
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if (ecsr & RCAR_CAN_ECSR_BE0F) {
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netdev_dbg(priv->ndev, "Bit Error (dominant)\n");
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tx_errors++;
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writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr);
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if (skb)
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cf->data[2] |= CAN_ERR_PROT_BIT0;
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}
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if (ecsr & RCAR_CAN_ECSR_BE1F) {
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netdev_dbg(priv->ndev, "Bit Error (recessive)\n");
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tx_errors++;
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writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr);
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if (skb)
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cf->data[2] |= CAN_ERR_PROT_BIT1;
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}
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if (ecsr & RCAR_CAN_ECSR_CEF) {
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netdev_dbg(priv->ndev, "CRC Error\n");
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rx_errors++;
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writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr);
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if (skb)
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cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
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}
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if (ecsr & RCAR_CAN_ECSR_AEF) {
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netdev_dbg(priv->ndev, "ACK Error\n");
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tx_errors++;
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writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr);
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if (skb) {
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cf->can_id |= CAN_ERR_ACK;
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cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
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}
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}
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if (ecsr & RCAR_CAN_ECSR_FEF) {
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netdev_dbg(priv->ndev, "Form Error\n");
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rx_errors++;
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writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr);
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if (skb)
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cf->data[2] |= CAN_ERR_PROT_FORM;
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}
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if (ecsr & RCAR_CAN_ECSR_SEF) {
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netdev_dbg(priv->ndev, "Stuff Error\n");
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rx_errors++;
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writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr);
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if (skb)
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cf->data[2] |= CAN_ERR_PROT_STUFF;
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}
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priv->can.can_stats.bus_error++;
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ndev->stats.rx_errors += rx_errors;
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ndev->stats.tx_errors += tx_errors;
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writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr);
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}
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if (eifr & RCAR_CAN_EIFR_EWIF) {
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netdev_dbg(priv->ndev, "Error warning interrupt\n");
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priv->can.state = CAN_STATE_ERROR_WARNING;
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priv->can.can_stats.error_warning++;
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/* Clear interrupt condition */
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writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr);
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if (skb)
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cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
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CAN_ERR_CRTL_RX_WARNING;
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}
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if (eifr & RCAR_CAN_EIFR_EPIF) {
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netdev_dbg(priv->ndev, "Error passive interrupt\n");
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priv->can.state = CAN_STATE_ERROR_PASSIVE;
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priv->can.can_stats.error_passive++;
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/* Clear interrupt condition */
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writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr);
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if (skb)
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cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
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CAN_ERR_CRTL_RX_PASSIVE;
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}
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if (eifr & RCAR_CAN_EIFR_BOEIF) {
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netdev_dbg(priv->ndev, "Bus-off entry interrupt\n");
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tx_failure_cleanup(ndev);
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priv->ier = RCAR_CAN_IER_ERSIE;
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writeb(priv->ier, &priv->regs->ier);
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priv->can.state = CAN_STATE_BUS_OFF;
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/* Clear interrupt condition */
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writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr);
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can_bus_off(ndev);
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if (skb)
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cf->can_id |= CAN_ERR_BUSOFF;
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}
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if (eifr & RCAR_CAN_EIFR_ORIF) {
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netdev_dbg(priv->ndev, "Receive overrun error interrupt\n");
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ndev->stats.rx_over_errors++;
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+
ndev->stats.rx_errors++;
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writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr);
341
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if (skb) {
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cf->can_id |= CAN_ERR_CRTL;
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cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
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}
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}
346
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if (eifr & RCAR_CAN_EIFR_OLIF) {
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netdev_dbg(priv->ndev,
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"Overload Frame Transmission error interrupt\n");
349
+
ndev->stats.rx_over_errors++;
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+
ndev->stats.rx_errors++;
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writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr);
352
+
if (skb) {
353
+
cf->can_id |= CAN_ERR_PROT;
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+
cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
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+
}
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+
}
357
+
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if (skb) {
359
+
stats->rx_packets++;
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stats->rx_bytes += cf->can_dlc;
361
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netif_rx(skb);
362
+
}
363
+
}
364
+
365
+
static void rcar_can_tx_done(struct net_device *ndev)
366
+
{
367
+
struct rcar_can_priv *priv = netdev_priv(ndev);
368
+
struct net_device_stats *stats = &ndev->stats;
369
+
u8 isr;
370
+
371
+
while (1) {
372
+
u8 unsent = readb(&priv->regs->tfcr);
373
+
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unsent = (unsent & RCAR_CAN_TFCR_TFUST) >>
375
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RCAR_CAN_TFCR_TFUST_SHIFT;
376
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if (priv->tx_head - priv->tx_tail <= unsent)
377
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break;
378
+
stats->tx_packets++;
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stats->tx_bytes += priv->tx_dlc[priv->tx_tail %
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RCAR_CAN_FIFO_DEPTH];
381
+
priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0;
382
+
can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH);
383
+
priv->tx_tail++;
384
+
netif_wake_queue(ndev);
385
+
}
386
+
/* Clear interrupt */
387
+
isr = readb(&priv->regs->isr);
388
+
writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr);
389
+
can_led_event(ndev, CAN_LED_EVENT_TX);
390
+
}
391
+
392
+
static irqreturn_t rcar_can_interrupt(int irq, void *dev_id)
393
+
{
394
+
struct net_device *ndev = dev_id;
395
+
struct rcar_can_priv *priv = netdev_priv(ndev);
396
+
u8 isr;
397
+
398
+
isr = readb(&priv->regs->isr);
399
+
if (!(isr & priv->ier))
400
+
return IRQ_NONE;
401
+
402
+
if (isr & RCAR_CAN_ISR_ERSF)
403
+
rcar_can_error(ndev);
404
+
405
+
if (isr & RCAR_CAN_ISR_TXFF)
406
+
rcar_can_tx_done(ndev);
407
+
408
+
if (isr & RCAR_CAN_ISR_RXFF) {
409
+
if (napi_schedule_prep(&priv->napi)) {
410
+
/* Disable Rx FIFO interrupts */
411
+
priv->ier &= ~RCAR_CAN_IER_RXFIE;
412
+
writeb(priv->ier, &priv->regs->ier);
413
+
__napi_schedule(&priv->napi);
414
+
}
415
+
}
416
+
417
+
return IRQ_HANDLED;
418
+
}
419
+
420
+
static void rcar_can_set_bittiming(struct net_device *dev)
421
+
{
422
+
struct rcar_can_priv *priv = netdev_priv(dev);
423
+
struct can_bittiming *bt = &priv->can.bittiming;
424
+
u32 bcr;
425
+
426
+
bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) |
427
+
RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) |
428
+
RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1);
429
+
/* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access.
430
+
* All the registers are big-endian but they get byte-swapped on 32-bit
431
+
* read/write (but not on 8-bit, contrary to the manuals)...
432
+
*/
433
+
writel((bcr << 8) | priv->clock_select, &priv->regs->bcr);
434
+
}
435
+
436
+
static void rcar_can_start(struct net_device *ndev)
437
+
{
438
+
struct rcar_can_priv *priv = netdev_priv(ndev);
439
+
u16 ctlr;
440
+
int i;
441
+
442
+
/* Set controller to known mode:
443
+
* - FIFO mailbox mode
444
+
* - accept all messages
445
+
* - overrun mode
446
+
* CAN is in sleep mode after MCU hardware or software reset.
447
+
*/
448
+
ctlr = readw(&priv->regs->ctlr);
449
+
ctlr &= ~RCAR_CAN_CTLR_SLPM;
450
+
writew(ctlr, &priv->regs->ctlr);
451
+
/* Go to reset mode */
452
+
ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET;
453
+
writew(ctlr, &priv->regs->ctlr);
454
+
for (i = 0; i < MAX_STR_READS; i++) {
455
+
if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)
456
+
break;
457
+
}
458
+
rcar_can_set_bittiming(ndev);
459
+
ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */
460
+
ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */
461
+
/* at bus-off */
462
+
ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */
463
+
ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */
464
+
writew(ctlr, &priv->regs->ctlr);
465
+
466
+
/* Accept all SID and EID */
467
+
writel(0, &priv->regs->mkr_2_9[6]);
468
+
writel(0, &priv->regs->mkr_2_9[7]);
469
+
/* In FIFO mailbox mode, write "0" to bits 24 to 31 */
470
+
writel(0, &priv->regs->mkivlr1);
471
+
/* Accept all frames */
472
+
writel(0, &priv->regs->fidcr[0]);
473
+
writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]);
474
+
/* Enable and configure FIFO mailbox interrupts */
475
+
writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1);
476
+
477
+
priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE |
478
+
RCAR_CAN_IER_TXFIE;
479
+
writeb(priv->ier, &priv->regs->ier);
480
+
481
+
/* Accumulate error codes */
482
+
writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr);
483
+
/* Enable error interrupts */
484
+
writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE |
485
+
(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ?
486
+
RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE |
487
+
RCAR_CAN_EIER_OLIE, &priv->regs->eier);
488
+
priv->can.state = CAN_STATE_ERROR_ACTIVE;
489
+
490
+
/* Go to operation mode */
491
+
writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr);
492
+
for (i = 0; i < MAX_STR_READS; i++) {
493
+
if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST))
494
+
break;
495
+
}
496
+
/* Enable Rx and Tx FIFO */
497
+
writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr);
498
+
writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr);
499
+
}
500
+
501
+
static int rcar_can_open(struct net_device *ndev)
502
+
{
503
+
struct rcar_can_priv *priv = netdev_priv(ndev);
504
+
int err;
505
+
506
+
err = clk_prepare_enable(priv->clk);
507
+
if (err) {
508
+
netdev_err(ndev, "clk_prepare_enable() failed, error %d\n",
509
+
err);
510
+
goto out;
511
+
}
512
+
err = open_candev(ndev);
513
+
if (err) {
514
+
netdev_err(ndev, "open_candev() failed, error %d\n", err);
515
+
goto out_clock;
516
+
}
517
+
napi_enable(&priv->napi);
518
+
err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev);
519
+
if (err) {
520
+
netdev_err(ndev, "error requesting interrupt %x\n", ndev->irq);
521
+
goto out_close;
522
+
}
523
+
can_led_event(ndev, CAN_LED_EVENT_OPEN);
524
+
rcar_can_start(ndev);
525
+
netif_start_queue(ndev);
526
+
return 0;
527
+
out_close:
528
+
napi_disable(&priv->napi);
529
+
close_candev(ndev);
530
+
out_clock:
531
+
clk_disable_unprepare(priv->clk);
532
+
out:
533
+
return err;
534
+
}
535
+
536
+
static void rcar_can_stop(struct net_device *ndev)
537
+
{
538
+
struct rcar_can_priv *priv = netdev_priv(ndev);
539
+
u16 ctlr;
540
+
int i;
541
+
542
+
/* Go to (force) reset mode */
543
+
ctlr = readw(&priv->regs->ctlr);
544
+
ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET;
545
+
writew(ctlr, &priv->regs->ctlr);
546
+
for (i = 0; i < MAX_STR_READS; i++) {
547
+
if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)
548
+
break;
549
+
}
550
+
writel(0, &priv->regs->mier0);
551
+
writel(0, &priv->regs->mier1);
552
+
writeb(0, &priv->regs->ier);
553
+
writeb(0, &priv->regs->eier);
554
+
/* Go to sleep mode */
555
+
ctlr |= RCAR_CAN_CTLR_SLPM;
556
+
writew(ctlr, &priv->regs->ctlr);
557
+
priv->can.state = CAN_STATE_STOPPED;
558
+
}
559
+
560
+
static int rcar_can_close(struct net_device *ndev)
561
+
{
562
+
struct rcar_can_priv *priv = netdev_priv(ndev);
563
+
564
+
netif_stop_queue(ndev);
565
+
rcar_can_stop(ndev);
566
+
free_irq(ndev->irq, ndev);
567
+
napi_disable(&priv->napi);
568
+
clk_disable_unprepare(priv->clk);
569
+
close_candev(ndev);
570
+
can_led_event(ndev, CAN_LED_EVENT_STOP);
571
+
return 0;
572
+
}
573
+
574
+
static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb,
575
+
struct net_device *ndev)
576
+
{
577
+
struct rcar_can_priv *priv = netdev_priv(ndev);
578
+
struct can_frame *cf = (struct can_frame *)skb->data;
579
+
u32 data, i;
580
+
581
+
if (can_dropped_invalid_skb(ndev, skb))
582
+
return NETDEV_TX_OK;
583
+
584
+
if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
585
+
data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE;
586
+
else /* Standard frame format */
587
+
data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT;
588
+
589
+
if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */
590
+
data |= RCAR_CAN_RTR;
591
+
} else {
592
+
for (i = 0; i < cf->can_dlc; i++)
593
+
writeb(cf->data[i],
594
+
&priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]);
595
+
}
596
+
597
+
writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id);
598
+
599
+
writeb(cf->can_dlc, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc);
600
+
601
+
priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->can_dlc;
602
+
can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH);
603
+
priv->tx_head++;
604
+
/* Start Tx: write 0xff to the TFPCR register to increment
605
+
* the CPU-side pointer for the transmit FIFO to the next
606
+
* mailbox location
607
+
*/
608
+
writeb(0xff, &priv->regs->tfpcr);
609
+
/* Stop the queue if we've filled all FIFO entries */
610
+
if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH)
611
+
netif_stop_queue(ndev);
612
+
613
+
return NETDEV_TX_OK;
614
+
}
615
+
616
+
static const struct net_device_ops rcar_can_netdev_ops = {
617
+
.ndo_open = rcar_can_open,
618
+
.ndo_stop = rcar_can_close,
619
+
.ndo_start_xmit = rcar_can_start_xmit,
620
+
};
621
+
622
+
static void rcar_can_rx_pkt(struct rcar_can_priv *priv)
623
+
{
624
+
struct net_device_stats *stats = &priv->ndev->stats;
625
+
struct can_frame *cf;
626
+
struct sk_buff *skb;
627
+
u32 data;
628
+
u8 dlc;
629
+
630
+
skb = alloc_can_skb(priv->ndev, &cf);
631
+
if (!skb) {
632
+
stats->rx_dropped++;
633
+
return;
634
+
}
635
+
636
+
data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id);
637
+
if (data & RCAR_CAN_IDE)
638
+
cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
639
+
else
640
+
cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK;
641
+
642
+
dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc);
643
+
cf->can_dlc = get_can_dlc(dlc);
644
+
if (data & RCAR_CAN_RTR) {
645
+
cf->can_id |= CAN_RTR_FLAG;
646
+
} else {
647
+
for (dlc = 0; dlc < cf->can_dlc; dlc++)
648
+
cf->data[dlc] =
649
+
readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]);
650
+
}
651
+
652
+
can_led_event(priv->ndev, CAN_LED_EVENT_RX);
653
+
654
+
stats->rx_bytes += cf->can_dlc;
655
+
stats->rx_packets++;
656
+
netif_receive_skb(skb);
657
+
}
658
+
659
+
static int rcar_can_rx_poll(struct napi_struct *napi, int quota)
660
+
{
661
+
struct rcar_can_priv *priv = container_of(napi,
662
+
struct rcar_can_priv, napi);
663
+
int num_pkts;
664
+
665
+
for (num_pkts = 0; num_pkts < quota; num_pkts++) {
666
+
u8 rfcr, isr;
667
+
668
+
isr = readb(&priv->regs->isr);
669
+
/* Clear interrupt bit */
670
+
if (isr & RCAR_CAN_ISR_RXFF)
671
+
writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr);
672
+
rfcr = readb(&priv->regs->rfcr);
673
+
if (rfcr & RCAR_CAN_RFCR_RFEST)
674
+
break;
675
+
rcar_can_rx_pkt(priv);
676
+
/* Write 0xff to the RFPCR register to increment
677
+
* the CPU-side pointer for the receive FIFO
678
+
* to the next mailbox location
679
+
*/
680
+
writeb(0xff, &priv->regs->rfpcr);
681
+
}
682
+
/* All packets processed */
683
+
if (num_pkts < quota) {
684
+
napi_complete(napi);
685
+
priv->ier |= RCAR_CAN_IER_RXFIE;
686
+
writeb(priv->ier, &priv->regs->ier);
687
+
}
688
+
return num_pkts;
689
+
}
690
+
691
+
static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
692
+
{
693
+
switch (mode) {
694
+
case CAN_MODE_START:
695
+
rcar_can_start(ndev);
696
+
netif_wake_queue(ndev);
697
+
return 0;
698
+
default:
699
+
return -EOPNOTSUPP;
700
+
}
701
+
}
702
+
703
+
static int rcar_can_get_berr_counter(const struct net_device *dev,
704
+
struct can_berr_counter *bec)
705
+
{
706
+
struct rcar_can_priv *priv = netdev_priv(dev);
707
+
int err;
708
+
709
+
err = clk_prepare_enable(priv->clk);
710
+
if (err)
711
+
return err;
712
+
bec->txerr = readb(&priv->regs->tecr);
713
+
bec->rxerr = readb(&priv->regs->recr);
714
+
clk_disable_unprepare(priv->clk);
715
+
return 0;
716
+
}
717
+
718
+
static int rcar_can_probe(struct platform_device *pdev)
719
+
{
720
+
struct rcar_can_platform_data *pdata;
721
+
struct rcar_can_priv *priv;
722
+
struct net_device *ndev;
723
+
struct resource *mem;
724
+
void __iomem *addr;
725
+
int err = -ENODEV;
726
+
int irq;
727
+
728
+
pdata = dev_get_platdata(&pdev->dev);
729
+
if (!pdata) {
730
+
dev_err(&pdev->dev, "No platform data provided!\n");
731
+
goto fail;
732
+
}
733
+
734
+
irq = platform_get_irq(pdev, 0);
735
+
if (!irq) {
736
+
dev_err(&pdev->dev, "No IRQ resource\n");
737
+
goto fail;
738
+
}
739
+
740
+
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
741
+
addr = devm_ioremap_resource(&pdev->dev, mem);
742
+
if (IS_ERR(addr)) {
743
+
err = PTR_ERR(addr);
744
+
goto fail;
745
+
}
746
+
747
+
ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH);
748
+
if (!ndev) {
749
+
dev_err(&pdev->dev, "alloc_candev() failed\n");
750
+
err = -ENOMEM;
751
+
goto fail;
752
+
}
753
+
754
+
priv = netdev_priv(ndev);
755
+
756
+
priv->clk = devm_clk_get(&pdev->dev, NULL);
757
+
if (IS_ERR(priv->clk)) {
758
+
err = PTR_ERR(priv->clk);
759
+
dev_err(&pdev->dev, "cannot get clock: %d\n", err);
760
+
goto fail_clk;
761
+
}
762
+
763
+
ndev->netdev_ops = &rcar_can_netdev_ops;
764
+
ndev->irq = irq;
765
+
ndev->flags |= IFF_ECHO;
766
+
priv->ndev = ndev;
767
+
priv->regs = addr;
768
+
priv->clock_select = pdata->clock_select;
769
+
priv->can.clock.freq = clk_get_rate(priv->clk);
770
+
priv->can.bittiming_const = &rcar_can_bittiming_const;
771
+
priv->can.do_set_mode = rcar_can_do_set_mode;
772
+
priv->can.do_get_berr_counter = rcar_can_get_berr_counter;
773
+
priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
774
+
platform_set_drvdata(pdev, ndev);
775
+
SET_NETDEV_DEV(ndev, &pdev->dev);
776
+
777
+
netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll,
778
+
RCAR_CAN_NAPI_WEIGHT);
779
+
err = register_candev(ndev);
780
+
if (err) {
781
+
dev_err(&pdev->dev, "register_candev() failed, error %d\n",
782
+
err);
783
+
goto fail_candev;
784
+
}
785
+
786
+
devm_can_led_init(ndev);
787
+
788
+
dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
789
+
priv->regs, ndev->irq);
790
+
791
+
return 0;
792
+
fail_candev:
793
+
netif_napi_del(&priv->napi);
794
+
fail_clk:
795
+
free_candev(ndev);
796
+
fail:
797
+
return err;
798
+
}
799
+
800
+
static int rcar_can_remove(struct platform_device *pdev)
801
+
{
802
+
struct net_device *ndev = platform_get_drvdata(pdev);
803
+
struct rcar_can_priv *priv = netdev_priv(ndev);
804
+
805
+
unregister_candev(ndev);
806
+
netif_napi_del(&priv->napi);
807
+
free_candev(ndev);
808
+
return 0;
809
+
}
810
+
811
+
static int __maybe_unused rcar_can_suspend(struct device *dev)
812
+
{
813
+
struct net_device *ndev = dev_get_drvdata(dev);
814
+
struct rcar_can_priv *priv = netdev_priv(ndev);
815
+
u16 ctlr;
816
+
817
+
if (netif_running(ndev)) {
818
+
netif_stop_queue(ndev);
819
+
netif_device_detach(ndev);
820
+
}
821
+
ctlr = readw(&priv->regs->ctlr);
822
+
ctlr |= RCAR_CAN_CTLR_CANM_HALT;
823
+
writew(ctlr, &priv->regs->ctlr);
824
+
ctlr |= RCAR_CAN_CTLR_SLPM;
825
+
writew(ctlr, &priv->regs->ctlr);
826
+
priv->can.state = CAN_STATE_SLEEPING;
827
+
828
+
clk_disable(priv->clk);
829
+
return 0;
830
+
}
831
+
832
+
static int __maybe_unused rcar_can_resume(struct device *dev)
833
+
{
834
+
struct net_device *ndev = dev_get_drvdata(dev);
835
+
struct rcar_can_priv *priv = netdev_priv(ndev);
836
+
u16 ctlr;
837
+
int err;
838
+
839
+
err = clk_enable(priv->clk);
840
+
if (err) {
841
+
netdev_err(ndev, "clk_enable() failed, error %d\n", err);
842
+
return err;
843
+
}
844
+
845
+
ctlr = readw(&priv->regs->ctlr);
846
+
ctlr &= ~RCAR_CAN_CTLR_SLPM;
847
+
writew(ctlr, &priv->regs->ctlr);
848
+
ctlr &= ~RCAR_CAN_CTLR_CANM;
849
+
writew(ctlr, &priv->regs->ctlr);
850
+
priv->can.state = CAN_STATE_ERROR_ACTIVE;
851
+
852
+
if (netif_running(ndev)) {
853
+
netif_device_attach(ndev);
854
+
netif_start_queue(ndev);
855
+
}
856
+
return 0;
857
+
}
858
+
859
+
static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume);
860
+
861
+
static struct platform_driver rcar_can_driver = {
862
+
.driver = {
863
+
.name = RCAR_CAN_DRV_NAME,
864
+
.owner = THIS_MODULE,
865
+
.pm = &rcar_can_pm_ops,
866
+
},
867
+
.probe = rcar_can_probe,
868
+
.remove = rcar_can_remove,
869
+
};
870
+
871
+
module_platform_driver(rcar_can_driver);
872
+
873
+
MODULE_AUTHOR("Cogent Embedded, Inc.");
874
+
MODULE_LICENSE("GPL");
875
+
MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC");
876
+
MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME);
+17
include/linux/can/platform/rcar_can.h
+17
include/linux/can/platform/rcar_can.h
···
1
+
#ifndef _CAN_PLATFORM_RCAR_CAN_H_
2
+
#define _CAN_PLATFORM_RCAR_CAN_H_
3
+
4
+
#include <linux/types.h>
5
+
6
+
/* Clock Select Register settings */
7
+
enum CLKR {
8
+
CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */
9
+
CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */
10
+
CLKR_CLKEXT = 3 /* Externally input clock */
11
+
};
12
+
13
+
struct rcar_can_platform_data {
14
+
enum CLKR clock_select; /* Clock source select */
15
+
};
16
+
17
+
#endif /* !_CAN_PLATFORM_RCAR_CAN_H_ */