tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'spear/clock' and 'imx/clock' into next/clock
Updated to resolve dependencies.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+17416
-2993
+7
-6
Documentation/arm/SPEAr/overview.txt
+7
-6
Documentation/arm/SPEAr/overview.txt
···
17
17
SPEAr (Platform)
18
18
- SPEAr3XX (3XX SOC series, based on ARM9)
19
19
- SPEAr300 (SOC)
20
-
- SPEAr300_EVB (Evaluation Board)
20
+
- SPEAr300 Evaluation Board
21
21
- SPEAr310 (SOC)
22
-
- SPEAr310_EVB (Evaluation Board)
22
+
- SPEAr310 Evaluation Board
23
23
- SPEAr320 (SOC)
24
-
- SPEAr320_EVB (Evaluation Board)
24
+
- SPEAr320 Evaluation Board
25
25
- SPEAr6XX (6XX SOC series, based on ARM9)
26
26
- SPEAr600 (SOC)
27
-
- SPEAr600_EVB (Evaluation Board)
27
+
- SPEAr600 Evaluation Board
28
28
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
29
29
- SPEAr1300 (SOC)
30
30
···
51
51
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
52
52
spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
53
53
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
54
-
mach-spear* also contains board specific files for each machine type.
54
+
mach-spear* doesn't contains board specific files as they fully support
55
+
Flattened Device Tree.
55
56
56
57
57
58
Document Author
58
59
---------------
59
60
60
-
Viresh Kumar, (c) 2010 ST Microelectronics
61
+
Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
+18
Documentation/devicetree/bindings/arm/spear-timer.txt
+18
Documentation/devicetree/bindings/arm/spear-timer.txt
···
1
+
* SPEAr ARM Timer
2
+
3
+
** Timer node required properties:
4
+
5
+
- compatible : Should be:
6
+
"st,spear-timer"
7
+
- reg: Address range of the timer registers
8
+
- interrupt-parent: Should be the phandle for the interrupt controller
9
+
that services interrupts for this device
10
+
- interrupt: Should contain the timer interrupt number
11
+
12
+
Example:
13
+
14
+
timer@f0000000 {
15
+
compatible = "st,spear-timer";
16
+
reg = <0xf0000000 0x400>;
17
+
interrupts = <2>;
18
+
};
+18
Documentation/devicetree/bindings/arm/spear.txt
+18
Documentation/devicetree/bindings/arm/spear.txt
···
6
6
Required root node property:
7
7
8
8
compatible = "st,spear600";
9
+
10
+
Boards with the ST SPEAr300 SoC shall have the following properties:
11
+
12
+
Required root node property:
13
+
14
+
compatible = "st,spear300";
15
+
16
+
Boards with the ST SPEAr310 SoC shall have the following properties:
17
+
18
+
Required root node property:
19
+
20
+
compatible = "st,spear310";
21
+
22
+
Boards with the ST SPEAr320 SoC shall have the following properties:
23
+
24
+
Required root node property:
25
+
26
+
compatible = "st,spear320";
+95
Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+95
Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
···
1
+
* Freescale IOMUX Controller (IOMUXC) for i.MX
2
+
3
+
The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
4
+
to share one PAD to several functional blocks. The sharing is done by
5
+
multiplexing the PAD input/output signals. For each PAD there are up to
6
+
8 muxing options (called ALT modes). Since different modules require
7
+
different PAD settings (like pull up, keeper, etc) the IOMUXC controls
8
+
also the PAD settings parameters.
9
+
10
+
Please refer to pinctrl-bindings.txt in this directory for details of the
11
+
common pinctrl bindings used by client devices, including the meaning of the
12
+
phrase "pin configuration node".
13
+
14
+
Freescale IMX pin configuration node is a node of a group of pins which can be
15
+
used for a specific device or function. This node represents both mux and config
16
+
of the pins in that group. The 'mux' selects the function mode(also named mux
17
+
mode) this pin can work on and the 'config' configures various pad settings
18
+
such as pull-up, open drain, drive strength, etc.
19
+
20
+
Required properties for iomux controller:
21
+
- compatible: "fsl,<soc>-iomuxc"
22
+
Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
23
+
24
+
Required properties for pin configuration node:
25
+
- fsl,pins: two integers array, represents a group of pins mux and config
26
+
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
27
+
pin working on a specific function, CONFIG is the pad setting value like
28
+
pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
29
+
pins and functions of each SoC.
30
+
31
+
Bits used for CONFIG:
32
+
NO_PAD_CTL(1 << 31): indicate this pin does not need config.
33
+
34
+
SION(1 << 30): Software Input On Field.
35
+
Force the selected mux mode input path no matter of MUX_MODE functionality.
36
+
By default the input path is determined by functionality of the selected
37
+
mux mode (regular).
38
+
39
+
Other bits are used for PAD setting.
40
+
Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
41
+
of bits definitions.
42
+
43
+
NOTE:
44
+
Some requirements for using fsl,imx-pinctrl binding:
45
+
1. We have pin function node defined under iomux controller node to represent
46
+
what pinmux functions this SoC supports.
47
+
2. The pin configuration node intends to work on a specific function should
48
+
to be defined under that specific function node.
49
+
The function node's name should represent well about what function
50
+
this group of pins in this pin configuration node are working on.
51
+
3. The driver can use the function node's name and pin configuration node's
52
+
name describe the pin function and group hierarchy.
53
+
For example, Linux IMX pinctrl driver takes the function node's name
54
+
as the function name and pin configuration node's name as group name to
55
+
create the map table.
56
+
4. Each pin configuration node should have a phandle, devices can set pins
57
+
configurations by referring to the phandle of that pin configuration node.
58
+
59
+
Examples:
60
+
usdhc@0219c000 { /* uSDHC4 */
61
+
fsl,card-wired;
62
+
vmmc-supply = <®_3p3v>;
63
+
status = "okay";
64
+
pinctrl-names = "default";
65
+
pinctrl-0 = <&pinctrl_usdhc4_1>;
66
+
};
67
+
68
+
iomuxc@020e0000 {
69
+
compatible = "fsl,imx6q-iomuxc";
70
+
reg = <0x020e0000 0x4000>;
71
+
72
+
/* shared pinctrl settings */
73
+
usdhc4 {
74
+
pinctrl_usdhc4_1: usdhc4grp-1 {
75
+
fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
76
+
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
77
+
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
78
+
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
79
+
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
80
+
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
81
+
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
82
+
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
83
+
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
84
+
1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
85
+
};
86
+
};
87
+
....
88
+
};
89
+
Refer to the IOMUXC controller chapter in imx6q datasheet,
90
+
0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
91
+
80Ohm driver strength and Fast Slew Rate.
92
+
User should refer to each SoC spec to set the correct value.
93
+
94
+
TODO: when dtc macro support is available, we can change above raw data
95
+
to dt macro which can get better readability in dts file.
+1628
Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
+1628
Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
···
1
+
* Freescale IMX6Q IOMUX Controller
2
+
3
+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4
+
and usage.
5
+
6
+
Required properties:
7
+
- compatible: "fsl,imx6q-iomuxc"
8
+
- fsl,pins: two integers array, represents a group of pins mux and config
9
+
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10
+
pin working on a specific function, CONFIG is the pad setting value like
11
+
pull-up for this pin. Please refer to imx6q datasheet for the valid pad
12
+
config settings.
13
+
14
+
CONFIG bits definition:
15
+
PAD_CTL_HYS (1 << 16)
16
+
PAD_CTL_PUS_100K_DOWN (0 << 14)
17
+
PAD_CTL_PUS_47K_UP (1 << 14)
18
+
PAD_CTL_PUS_100K_UP (2 << 14)
19
+
PAD_CTL_PUS_22K_UP (3 << 14)
20
+
PAD_CTL_PUE (1 << 13)
21
+
PAD_CTL_PKE (1 << 12)
22
+
PAD_CTL_ODE (1 << 11)
23
+
PAD_CTL_SPEED_LOW (1 << 6)
24
+
PAD_CTL_SPEED_MED (2 << 6)
25
+
PAD_CTL_SPEED_HIGH (3 << 6)
26
+
PAD_CTL_DSE_DISABLE (0 << 3)
27
+
PAD_CTL_DSE_240ohm (1 << 3)
28
+
PAD_CTL_DSE_120ohm (2 << 3)
29
+
PAD_CTL_DSE_80ohm (3 << 3)
30
+
PAD_CTL_DSE_60ohm (4 << 3)
31
+
PAD_CTL_DSE_48ohm (5 << 3)
32
+
PAD_CTL_DSE_40ohm (6 << 3)
33
+
PAD_CTL_DSE_34ohm (7 << 3)
34
+
PAD_CTL_SRE_FAST (1 << 0)
35
+
PAD_CTL_SRE_SLOW (0 << 0)
36
+
37
+
See below for available PIN_FUNC_ID for imx6q:
38
+
MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0
39
+
MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1
40
+
MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2
41
+
MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3
42
+
MX6Q_PAD_SD2_DAT1__KPP_COL_7 4
43
+
MX6Q_PAD_SD2_DAT1__GPIO_1_14 5
44
+
MX6Q_PAD_SD2_DAT1__CCM_WAIT 6
45
+
MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7
46
+
MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8
47
+
MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9
48
+
MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10
49
+
MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11
50
+
MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12
51
+
MX6Q_PAD_SD2_DAT2__GPIO_1_13 13
52
+
MX6Q_PAD_SD2_DAT2__CCM_STOP 14
53
+
MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15
54
+
MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16
55
+
MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17
56
+
MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18
57
+
MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19
58
+
MX6Q_PAD_SD2_DAT0__GPIO_1_15 20
59
+
MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21
60
+
MX6Q_PAD_SD2_DAT0__TESTO_2 22
61
+
MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23
62
+
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24
63
+
MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25
64
+
MX6Q_PAD_RGMII_TXC__GPIO_6_19 26
65
+
MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27
66
+
MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28
67
+
MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29
68
+
MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30
69
+
MX6Q_PAD_RGMII_TD0__GPIO_6_20 31
70
+
MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32
71
+
MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33
72
+
MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34
73
+
MX6Q_PAD_RGMII_TD1__GPIO_6_21 35
74
+
MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36
75
+
MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37
76
+
MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38
77
+
MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39
78
+
MX6Q_PAD_RGMII_TD2__GPIO_6_22 40
79
+
MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41
80
+
MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42
81
+
MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43
82
+
MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44
83
+
MX6Q_PAD_RGMII_TD3__GPIO_6_23 45
84
+
MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46
85
+
MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47
86
+
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48
87
+
MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49
88
+
MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50
89
+
MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51
90
+
MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52
91
+
MX6Q_PAD_RGMII_RD0__GPIO_6_25 53
92
+
MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54
93
+
MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55
94
+
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56
95
+
MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57
96
+
MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58
97
+
MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59
98
+
MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60
99
+
MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61
100
+
MX6Q_PAD_RGMII_RD1__GPIO_6_27 62
101
+
MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63
102
+
MX6Q_PAD_RGMII_RD1__SJC_FAIL 64
103
+
MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65
104
+
MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66
105
+
MX6Q_PAD_RGMII_RD2__GPIO_6_28 67
106
+
MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68
107
+
MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69
108
+
MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70
109
+
MX6Q_PAD_RGMII_RD3__GPIO_6_29 71
110
+
MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72
111
+
MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73
112
+
MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74
113
+
MX6Q_PAD_RGMII_RXC__GPIO_6_30 75
114
+
MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76
115
+
MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77
116
+
MX6Q_PAD_EIM_A25__ECSPI4_SS1 78
117
+
MX6Q_PAD_EIM_A25__ECSPI2_RDY 79
118
+
MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80
119
+
MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81
120
+
MX6Q_PAD_EIM_A25__GPIO_5_2 82
121
+
MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83
122
+
MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84
123
+
MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85
124
+
MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86
125
+
MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87
126
+
MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88
127
+
MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89
128
+
MX6Q_PAD_EIM_EB2__GPIO_2_30 90
129
+
MX6Q_PAD_EIM_EB2__I2C2_SCL 91
130
+
MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92
131
+
MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93
132
+
MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94
133
+
MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95
134
+
MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96
135
+
MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97
136
+
MX6Q_PAD_EIM_D16__GPIO_3_16 98
137
+
MX6Q_PAD_EIM_D16__I2C2_SDA 99
138
+
MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100
139
+
MX6Q_PAD_EIM_D17__ECSPI1_MISO 101
140
+
MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102
141
+
MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103
142
+
MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104
143
+
MX6Q_PAD_EIM_D17__GPIO_3_17 105
144
+
MX6Q_PAD_EIM_D17__I2C3_SCL 106
145
+
MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107
146
+
MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108
147
+
MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109
148
+
MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110
149
+
MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111
150
+
MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112
151
+
MX6Q_PAD_EIM_D18__GPIO_3_18 113
152
+
MX6Q_PAD_EIM_D18__I2C3_SDA 114
153
+
MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115
154
+
MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116
155
+
MX6Q_PAD_EIM_D19__ECSPI1_SS1 117
156
+
MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118
157
+
MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119
158
+
MX6Q_PAD_EIM_D19__UART1_CTS 120
159
+
MX6Q_PAD_EIM_D19__GPIO_3_19 121
160
+
MX6Q_PAD_EIM_D19__EPIT1_EPITO 122
161
+
MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123
162
+
MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124
163
+
MX6Q_PAD_EIM_D20__ECSPI4_SS0 125
164
+
MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126
165
+
MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127
166
+
MX6Q_PAD_EIM_D20__UART1_RTS 128
167
+
MX6Q_PAD_EIM_D20__GPIO_3_20 129
168
+
MX6Q_PAD_EIM_D20__EPIT2_EPITO 130
169
+
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131
170
+
MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132
171
+
MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133
172
+
MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134
173
+
MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135
174
+
MX6Q_PAD_EIM_D21__GPIO_3_21 136
175
+
MX6Q_PAD_EIM_D21__I2C1_SCL 137
176
+
MX6Q_PAD_EIM_D21__SPDIF_IN1 138
177
+
MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139
178
+
MX6Q_PAD_EIM_D22__ECSPI4_MISO 140
179
+
MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141
180
+
MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142
181
+
MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143
182
+
MX6Q_PAD_EIM_D22__GPIO_3_22 144
183
+
MX6Q_PAD_EIM_D22__SPDIF_OUT1 145
184
+
MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146
185
+
MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147
186
+
MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148
187
+
MX6Q_PAD_EIM_D23__UART3_CTS 149
188
+
MX6Q_PAD_EIM_D23__UART1_DCD 150
189
+
MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151
190
+
MX6Q_PAD_EIM_D23__GPIO_3_23 152
191
+
MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153
192
+
MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154
193
+
MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155
194
+
MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156
195
+
MX6Q_PAD_EIM_EB3__UART3_RTS 157
196
+
MX6Q_PAD_EIM_EB3__UART1_RI 158
197
+
MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159
198
+
MX6Q_PAD_EIM_EB3__GPIO_2_31 160
199
+
MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161
200
+
MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162
201
+
MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163
202
+
MX6Q_PAD_EIM_D24__ECSPI4_SS2 164
203
+
MX6Q_PAD_EIM_D24__UART3_TXD 165
204
+
MX6Q_PAD_EIM_D24__ECSPI1_SS2 166
205
+
MX6Q_PAD_EIM_D24__ECSPI2_SS2 167
206
+
MX6Q_PAD_EIM_D24__GPIO_3_24 168
207
+
MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169
208
+
MX6Q_PAD_EIM_D24__UART1_DTR 170
209
+
MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171
210
+
MX6Q_PAD_EIM_D25__ECSPI4_SS3 172
211
+
MX6Q_PAD_EIM_D25__UART3_RXD 173
212
+
MX6Q_PAD_EIM_D25__ECSPI1_SS3 174
213
+
MX6Q_PAD_EIM_D25__ECSPI2_SS3 175
214
+
MX6Q_PAD_EIM_D25__GPIO_3_25 176
215
+
MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177
216
+
MX6Q_PAD_EIM_D25__UART1_DSR 178
217
+
MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179
218
+
MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180
219
+
MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181
220
+
MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182
221
+
MX6Q_PAD_EIM_D26__UART2_TXD 183
222
+
MX6Q_PAD_EIM_D26__GPIO_3_26 184
223
+
MX6Q_PAD_EIM_D26__IPU1_SISG_2 185
224
+
MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186
225
+
MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187
226
+
MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188
227
+
MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189
228
+
MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190
229
+
MX6Q_PAD_EIM_D27__UART2_RXD 191
230
+
MX6Q_PAD_EIM_D27__GPIO_3_27 192
231
+
MX6Q_PAD_EIM_D27__IPU1_SISG_3 193
232
+
MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194
233
+
MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195
234
+
MX6Q_PAD_EIM_D28__I2C1_SDA 196
235
+
MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197
236
+
MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198
237
+
MX6Q_PAD_EIM_D28__UART2_CTS 199
238
+
MX6Q_PAD_EIM_D28__GPIO_3_28 200
239
+
MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201
240
+
MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202
241
+
MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203
242
+
MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204
243
+
MX6Q_PAD_EIM_D29__ECSPI4_SS0 205
244
+
MX6Q_PAD_EIM_D29__UART2_RTS 206
245
+
MX6Q_PAD_EIM_D29__GPIO_3_29 207
246
+
MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208
247
+
MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209
248
+
MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210
249
+
MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211
250
+
MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212
251
+
MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213
252
+
MX6Q_PAD_EIM_D30__UART3_CTS 214
253
+
MX6Q_PAD_EIM_D30__GPIO_3_30 215
254
+
MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216
255
+
MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217
256
+
MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218
257
+
MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219
258
+
MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220
259
+
MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221
260
+
MX6Q_PAD_EIM_D31__UART3_RTS 222
261
+
MX6Q_PAD_EIM_D31__GPIO_3_31 223
262
+
MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224
263
+
MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225
264
+
MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226
265
+
MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227
266
+
MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228
267
+
MX6Q_PAD_EIM_A24__IPU2_SISG_2 229
268
+
MX6Q_PAD_EIM_A24__IPU1_SISG_2 230
269
+
MX6Q_PAD_EIM_A24__GPIO_5_4 231
270
+
MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232
271
+
MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233
272
+
MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234
273
+
MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235
274
+
MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236
275
+
MX6Q_PAD_EIM_A23__IPU2_SISG_3 237
276
+
MX6Q_PAD_EIM_A23__IPU1_SISG_3 238
277
+
MX6Q_PAD_EIM_A23__GPIO_6_6 239
278
+
MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240
279
+
MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241
280
+
MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242
281
+
MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243
282
+
MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244
283
+
MX6Q_PAD_EIM_A22__GPIO_2_16 245
284
+
MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246
285
+
MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247
286
+
MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248
287
+
MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249
288
+
MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250
289
+
MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251
290
+
MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252
291
+
MX6Q_PAD_EIM_A21__GPIO_2_17 253
292
+
MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254
293
+
MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255
294
+
MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256
295
+
MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257
296
+
MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258
297
+
MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259
298
+
MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260
299
+
MX6Q_PAD_EIM_A20__GPIO_2_18 261
300
+
MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262
301
+
MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263
302
+
MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264
303
+
MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265
304
+
MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266
305
+
MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267
306
+
MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268
307
+
MX6Q_PAD_EIM_A19__GPIO_2_19 269
308
+
MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270
309
+
MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271
310
+
MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272
311
+
MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273
312
+
MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274
313
+
MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275
314
+
MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276
315
+
MX6Q_PAD_EIM_A18__GPIO_2_20 277
316
+
MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278
317
+
MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279
318
+
MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280
319
+
MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281
320
+
MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282
321
+
MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283
322
+
MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284
323
+
MX6Q_PAD_EIM_A17__GPIO_2_21 285
324
+
MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286
325
+
MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287
326
+
MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288
327
+
MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289
328
+
MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290
329
+
MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291
330
+
MX6Q_PAD_EIM_A16__GPIO_2_22 292
331
+
MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293
332
+
MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294
333
+
MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295
334
+
MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296
335
+
MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297
336
+
MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298
337
+
MX6Q_PAD_EIM_CS0__GPIO_2_23 299
338
+
MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300
339
+
MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301
340
+
MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302
341
+
MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303
342
+
MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304
343
+
MX6Q_PAD_EIM_CS1__GPIO_2_24 305
344
+
MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306
345
+
MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307
346
+
MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308
347
+
MX6Q_PAD_EIM_OE__ECSPI2_MISO 309
348
+
MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310
349
+
MX6Q_PAD_EIM_OE__GPIO_2_25 311
350
+
MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312
351
+
MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313
352
+
MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314
353
+
MX6Q_PAD_EIM_RW__ECSPI2_SS0 315
354
+
MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316
355
+
MX6Q_PAD_EIM_RW__GPIO_2_26 317
356
+
MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318
357
+
MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319
358
+
MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320
359
+
MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321
360
+
MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322
361
+
MX6Q_PAD_EIM_LBA__GPIO_2_27 323
362
+
MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324
363
+
MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325
364
+
MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326
365
+
MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327
366
+
MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328
367
+
MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329
368
+
MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330
369
+
MX6Q_PAD_EIM_EB0__GPIO_2_28 331
370
+
MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332
371
+
MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333
372
+
MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334
373
+
MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335
374
+
MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336
375
+
MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337
376
+
MX6Q_PAD_EIM_EB1__GPIO_2_29 338
377
+
MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339
378
+
MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340
379
+
MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341
380
+
MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342
381
+
MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343
382
+
MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344
383
+
MX6Q_PAD_EIM_DA0__GPIO_3_0 345
384
+
MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346
385
+
MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347
386
+
MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348
387
+
MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349
388
+
MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350
389
+
MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351
390
+
MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352
391
+
MX6Q_PAD_EIM_DA1__GPIO_3_1 353
392
+
MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354
393
+
MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355
394
+
MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356
395
+
MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357
396
+
MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358
397
+
MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359
398
+
MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360
399
+
MX6Q_PAD_EIM_DA2__GPIO_3_2 361
400
+
MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362
401
+
MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363
402
+
MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364
403
+
MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365
404
+
MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366
405
+
MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367
406
+
MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368
407
+
MX6Q_PAD_EIM_DA3__GPIO_3_3 369
408
+
MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370
409
+
MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371
410
+
MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372
411
+
MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373
412
+
MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374
413
+
MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375
414
+
MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376
415
+
MX6Q_PAD_EIM_DA4__GPIO_3_4 377
416
+
MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378
417
+
MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379
418
+
MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380
419
+
MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381
420
+
MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382
421
+
MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383
422
+
MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384
423
+
MX6Q_PAD_EIM_DA5__GPIO_3_5 385
424
+
MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386
425
+
MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387
426
+
MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388
427
+
MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389
428
+
MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390
429
+
MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391
430
+
MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392
431
+
MX6Q_PAD_EIM_DA6__GPIO_3_6 393
432
+
MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394
433
+
MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395
434
+
MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396
435
+
MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397
436
+
MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398
437
+
MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399
438
+
MX6Q_PAD_EIM_DA7__GPIO_3_7 400
439
+
MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 401
440
+
MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 402
441
+
MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 403
442
+
MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 404
443
+
MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 405
444
+
MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 406
445
+
MX6Q_PAD_EIM_DA8__GPIO_3_8 407
446
+
MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 408
447
+
MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 409
448
+
MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 410
449
+
MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 411
450
+
MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 412
451
+
MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 413
452
+
MX6Q_PAD_EIM_DA9__GPIO_3_9 414
453
+
MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 415
454
+
MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 416
455
+
MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 417
456
+
MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 418
457
+
MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 419
458
+
MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 420
459
+
MX6Q_PAD_EIM_DA10__GPIO_3_10 421
460
+
MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 422
461
+
MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 423
462
+
MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 424
463
+
MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 425
464
+
MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 426
465
+
MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 427
466
+
MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 428
467
+
MX6Q_PAD_EIM_DA11__GPIO_3_11 429
468
+
MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 430
469
+
MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 431
470
+
MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 432
471
+
MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 433
472
+
MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 434
473
+
MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 435
474
+
MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 436
475
+
MX6Q_PAD_EIM_DA12__GPIO_3_12 437
476
+
MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 438
477
+
MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 439
478
+
MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 440
479
+
MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 441
480
+
MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK 442
481
+
MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 443
482
+
MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 444
483
+
MX6Q_PAD_EIM_DA13__GPIO_3_13 445
484
+
MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 446
485
+
MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 447
486
+
MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 448
487
+
MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 449
488
+
MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK 450
489
+
MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 451
490
+
MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 452
491
+
MX6Q_PAD_EIM_DA14__GPIO_3_14 453
492
+
MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 454
493
+
MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 455
494
+
MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 456
495
+
MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 457
496
+
MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 458
497
+
MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 459
498
+
MX6Q_PAD_EIM_DA15__GPIO_3_15 460
499
+
MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 461
500
+
MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 462
501
+
MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 463
502
+
MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B 464
503
+
MX6Q_PAD_EIM_WAIT__GPIO_5_0 465
504
+
MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 466
505
+
MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 467
506
+
MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK 468
507
+
MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 469
508
+
MX6Q_PAD_EIM_BCLK__GPIO_6_31 470
509
+
MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 471
510
+
MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK 472
511
+
MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK 473
512
+
MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 474
513
+
MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 475
514
+
MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 476
515
+
MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 477
516
+
MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 478
517
+
MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 479
518
+
MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 480
519
+
MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 481
520
+
MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 482
521
+
MX6Q_PAD_DI0_PIN15__GPIO_4_17 483
522
+
MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 484
523
+
MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 485
524
+
MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 486
525
+
MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 487
526
+
MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 488
527
+
MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 489
528
+
MX6Q_PAD_DI0_PIN2__GPIO_4_18 490
529
+
MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 491
530
+
MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 492
531
+
MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 493
532
+
MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 494
533
+
MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 495
534
+
MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 496
535
+
MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 497
536
+
MX6Q_PAD_DI0_PIN3__GPIO_4_19 498
537
+
MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 499
538
+
MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 500
539
+
MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 501
540
+
MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 502
541
+
MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 503
542
+
MX6Q_PAD_DI0_PIN4__USDHC1_WP 504
543
+
MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 505
544
+
MX6Q_PAD_DI0_PIN4__GPIO_4_20 506
545
+
MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 507
546
+
MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 508
547
+
MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 509
548
+
MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 510
549
+
MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 511
550
+
MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 512
551
+
MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN 513
552
+
MX6Q_PAD_DISP0_DAT0__GPIO_4_21 514
553
+
MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 515
554
+
MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 516
555
+
MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 517
556
+
MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 518
557
+
MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 519
558
+
MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL 520
559
+
MX6Q_PAD_DISP0_DAT1__GPIO_4_22 521
560
+
MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 522
561
+
MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 523
562
+
MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 524
563
+
MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 525
564
+
MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 526
565
+
MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 527
566
+
MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 528
567
+
MX6Q_PAD_DISP0_DAT2__GPIO_4_23 529
568
+
MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 530
569
+
MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 531
570
+
MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 532
571
+
MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 533
572
+
MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 534
573
+
MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 535
574
+
MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR 536
575
+
MX6Q_PAD_DISP0_DAT3__GPIO_4_24 537
576
+
MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 538
577
+
MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 539
578
+
MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 540
579
+
MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 541
580
+
MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 542
581
+
MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 543
582
+
MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 544
583
+
MX6Q_PAD_DISP0_DAT4__GPIO_4_25 545
584
+
MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 546
585
+
MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 547
586
+
MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 548
587
+
MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 549
588
+
MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 550
589
+
MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS 551
590
+
MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS 552
591
+
MX6Q_PAD_DISP0_DAT5__GPIO_4_26 553
592
+
MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 554
593
+
MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 555
594
+
MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 556
595
+
MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 557
596
+
MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 558
597
+
MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC 559
598
+
MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT 560
599
+
MX6Q_PAD_DISP0_DAT6__GPIO_4_27 561
600
+
MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 562
601
+
MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 563
602
+
MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 564
603
+
MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 565
604
+
MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 566
605
+
MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 567
606
+
MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 568
607
+
MX6Q_PAD_DISP0_DAT7__GPIO_4_28 569
608
+
MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 570
609
+
MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 571
610
+
MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 572
611
+
MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 573
612
+
MX6Q_PAD_DISP0_DAT8__PWM1_PWMO 574
613
+
MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B 575
614
+
MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 576
615
+
MX6Q_PAD_DISP0_DAT8__GPIO_4_29 577
616
+
MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 578
617
+
MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 579
618
+
MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 580
619
+
MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 581
620
+
MX6Q_PAD_DISP0_DAT9__PWM2_PWMO 582
621
+
MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B 583
622
+
MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 584
623
+
MX6Q_PAD_DISP0_DAT9__GPIO_4_30 585
624
+
MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 586
625
+
MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 587
626
+
MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 588
627
+
MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 589
628
+
MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 590
629
+
MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 591
630
+
MX6Q_PAD_DISP0_DAT10__GPIO_4_31 592
631
+
MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 593
632
+
MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 594
633
+
MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 595
634
+
MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 596
635
+
MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 597
636
+
MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 598
637
+
MX6Q_PAD_DISP0_DAT11__GPIO_5_5 599
638
+
MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 600
639
+
MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 601
640
+
MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 602
641
+
MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 603
642
+
MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED 604
643
+
MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 605
644
+
MX6Q_PAD_DISP0_DAT12__GPIO_5_6 606
645
+
MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 607
646
+
MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 608
647
+
MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 609
648
+
MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 610
649
+
MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 611
650
+
MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 612
651
+
MX6Q_PAD_DISP0_DAT13__GPIO_5_7 613
652
+
MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 614
653
+
MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 615
654
+
MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 616
655
+
MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 617
656
+
MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 618
657
+
MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 619
658
+
MX6Q_PAD_DISP0_DAT14__GPIO_5_8 620
659
+
MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 621
660
+
MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 622
661
+
MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 623
662
+
MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 624
663
+
MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 625
664
+
MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 626
665
+
MX6Q_PAD_DISP0_DAT15__GPIO_5_9 627
666
+
MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 628
667
+
MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 629
668
+
MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 630
669
+
MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 631
670
+
MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 632
671
+
MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 633
672
+
MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 634
673
+
MX6Q_PAD_DISP0_DAT16__GPIO_5_10 635
674
+
MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 636
675
+
MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 637
676
+
MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 638
677
+
MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 639
678
+
MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 640
679
+
MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 641
680
+
MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 642
681
+
MX6Q_PAD_DISP0_DAT17__GPIO_5_11 643
682
+
MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 644
683
+
MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 645
684
+
MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 646
685
+
MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 647
686
+
MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 648
687
+
MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 649
688
+
MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 650
689
+
MX6Q_PAD_DISP0_DAT18__GPIO_5_12 651
690
+
MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 652
691
+
MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 653
692
+
MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 654
693
+
MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 655
694
+
MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 656
695
+
MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 657
696
+
MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 658
697
+
MX6Q_PAD_DISP0_DAT19__GPIO_5_13 659
698
+
MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 660
699
+
MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 661
700
+
MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 662
701
+
MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 663
702
+
MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 664
703
+
MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 665
704
+
MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 666
705
+
MX6Q_PAD_DISP0_DAT20__GPIO_5_14 667
706
+
MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 668
707
+
MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 669
708
+
MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 670
709
+
MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 671
710
+
MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 672
711
+
MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 673
712
+
MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 674
713
+
MX6Q_PAD_DISP0_DAT21__GPIO_5_15 675
714
+
MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 676
715
+
MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 677
716
+
MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 678
717
+
MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 679
718
+
MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 680
719
+
MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 681
720
+
MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 682
721
+
MX6Q_PAD_DISP0_DAT22__GPIO_5_16 683
722
+
MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 684
723
+
MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 685
724
+
MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 686
725
+
MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 687
726
+
MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 688
727
+
MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 689
728
+
MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 690
729
+
MX6Q_PAD_DISP0_DAT23__GPIO_5_17 691
730
+
MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 692
731
+
MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 693
732
+
MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED 694
733
+
MX6Q_PAD_ENET_MDIO__ENET_MDIO 695
734
+
MX6Q_PAD_ENET_MDIO__ESAI1_SCKR 696
735
+
MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 697
736
+
MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT 698
737
+
MX6Q_PAD_ENET_MDIO__GPIO_1_22 699
738
+
MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK 700
739
+
MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED 701
740
+
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 702
741
+
MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR 703
742
+
MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 704
743
+
MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 705
744
+
MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK 706
745
+
MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH 707
746
+
MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 708
747
+
MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR 709
748
+
MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 710
749
+
MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT 711
750
+
MX6Q_PAD_ENET_RX_ER__GPIO_1_24 712
751
+
MX6Q_PAD_ENET_RX_ER__PHY_TDI 713
752
+
MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD 714
753
+
MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED 715
754
+
MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 716
755
+
MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT 717
756
+
MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK 718
757
+
MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 719
758
+
MX6Q_PAD_ENET_CRS_DV__PHY_TDO 720
759
+
MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD 721
760
+
MX6Q_PAD_ENET_RXD1__MLB_MLBSIG 722
761
+
MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 723
762
+
MX6Q_PAD_ENET_RXD1__ESAI1_FST 724
763
+
MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT 725
764
+
MX6Q_PAD_ENET_RXD1__GPIO_1_26 726
765
+
MX6Q_PAD_ENET_RXD1__PHY_TCK 727
766
+
MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON 728
767
+
MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT 729
768
+
MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 730
769
+
MX6Q_PAD_ENET_RXD0__ESAI1_HCKT 731
770
+
MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 732
771
+
MX6Q_PAD_ENET_RXD0__GPIO_1_27 733
772
+
MX6Q_PAD_ENET_RXD0__PHY_TMS 734
773
+
MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV 735
774
+
MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED 736
775
+
MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 737
776
+
MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 738
777
+
MX6Q_PAD_ENET_TX_EN__GPIO_1_28 739
778
+
MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI 740
779
+
MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH 741
780
+
MX6Q_PAD_ENET_TXD1__MLB_MLBCLK 742
781
+
MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 743
782
+
MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 744
783
+
MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 745
784
+
MX6Q_PAD_ENET_TXD1__GPIO_1_29 746
785
+
MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO 747
786
+
MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD 748
787
+
MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED 749
788
+
MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 750
789
+
MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 751
790
+
MX6Q_PAD_ENET_TXD0__GPIO_1_30 752
791
+
MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK 753
792
+
MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD 754
793
+
MX6Q_PAD_ENET_MDC__MLB_MLBDAT 755
794
+
MX6Q_PAD_ENET_MDC__ENET_MDC 756
795
+
MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 757
796
+
MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 758
797
+
MX6Q_PAD_ENET_MDC__GPIO_1_31 759
798
+
MX6Q_PAD_ENET_MDC__SATA_PHY_TMS 760
799
+
MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON 761
800
+
MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 762
801
+
MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 763
802
+
MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 764
803
+
MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 765
804
+
MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 766
805
+
MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 767
806
+
MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 768
807
+
MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 769
808
+
MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 770
809
+
MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 771
810
+
MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 772
811
+
MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 773
812
+
MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 774
813
+
MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 775
814
+
MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 776
815
+
MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 777
816
+
MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 778
817
+
MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 779
818
+
MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 780
819
+
MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 781
820
+
MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 782
821
+
MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 783
822
+
MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 784
823
+
MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 785
824
+
MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 786
825
+
MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 787
826
+
MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 788
827
+
MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 789
828
+
MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 790
829
+
MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 791
830
+
MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 792
831
+
MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 793
832
+
MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 794
833
+
MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 795
834
+
MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 796
835
+
MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 797
836
+
MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 798
837
+
MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 799
838
+
MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 800
839
+
MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 801
840
+
MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 802
841
+
MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 803
842
+
MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 804
843
+
MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 805
844
+
MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 806
845
+
MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 807
846
+
MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 808
847
+
MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 809
848
+
MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 810
849
+
MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 811
850
+
MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 812
851
+
MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 813
852
+
MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 814
853
+
MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 815
854
+
MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 816
855
+
MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 817
856
+
MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS 818
857
+
MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 819
858
+
MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 820
859
+
MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS 821
860
+
MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET 822
861
+
MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 823
862
+
MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 824
863
+
MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 825
864
+
MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 826
865
+
MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 827
866
+
MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 828
867
+
MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 829
868
+
MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 830
869
+
MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 831
870
+
MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE 832
871
+
MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 833
872
+
MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 834
873
+
MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 835
874
+
MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 836
875
+
MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 837
876
+
MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 838
877
+
MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 839
878
+
MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 840
879
+
MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 841
880
+
MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 842
881
+
MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 843
882
+
MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 844
883
+
MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 845
884
+
MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 846
885
+
MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 847
886
+
MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 848
887
+
MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 849
888
+
MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 850
889
+
MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 851
890
+
MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 852
891
+
MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 853
892
+
MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 854
893
+
MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 855
894
+
MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 856
895
+
MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 857
896
+
MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 858
897
+
MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 859
898
+
MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 860
899
+
MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 861
900
+
MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 862
901
+
MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 863
902
+
MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 864
903
+
MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 865
904
+
MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 866
905
+
MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 867
906
+
MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 868
907
+
MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 869
908
+
MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 870
909
+
MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 871
910
+
MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 872
911
+
MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 873
912
+
MX6Q_PAD_KEY_COL0__ENET_RDATA_3 874
913
+
MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC 875
914
+
MX6Q_PAD_KEY_COL0__KPP_COL_0 876
915
+
MX6Q_PAD_KEY_COL0__UART4_TXD 877
916
+
MX6Q_PAD_KEY_COL0__GPIO_4_6 878
917
+
MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT 879
918
+
MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST 880
919
+
MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 881
920
+
MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 882
921
+
MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 883
922
+
MX6Q_PAD_KEY_ROW0__KPP_ROW_0 884
923
+
MX6Q_PAD_KEY_ROW0__UART4_RXD 885
924
+
MX6Q_PAD_KEY_ROW0__GPIO_4_7 886
925
+
MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT 887
926
+
MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 888
927
+
MX6Q_PAD_KEY_COL1__ECSPI1_MISO 889
928
+
MX6Q_PAD_KEY_COL1__ENET_MDIO 890
929
+
MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 891
930
+
MX6Q_PAD_KEY_COL1__KPP_COL_1 892
931
+
MX6Q_PAD_KEY_COL1__UART5_TXD 893
932
+
MX6Q_PAD_KEY_COL1__GPIO_4_8 894
933
+
MX6Q_PAD_KEY_COL1__USDHC1_VSELECT 895
934
+
MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 896
935
+
MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 897
936
+
MX6Q_PAD_KEY_ROW1__ENET_COL 898
937
+
MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 899
938
+
MX6Q_PAD_KEY_ROW1__KPP_ROW_1 900
939
+
MX6Q_PAD_KEY_ROW1__UART5_RXD 901
940
+
MX6Q_PAD_KEY_ROW1__GPIO_4_9 902
941
+
MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT 903
942
+
MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 904
943
+
MX6Q_PAD_KEY_COL2__ECSPI1_SS1 905
944
+
MX6Q_PAD_KEY_COL2__ENET_RDATA_2 906
945
+
MX6Q_PAD_KEY_COL2__CAN1_TXCAN 907
946
+
MX6Q_PAD_KEY_COL2__KPP_COL_2 908
947
+
MX6Q_PAD_KEY_COL2__ENET_MDC 909
948
+
MX6Q_PAD_KEY_COL2__GPIO_4_10 910
949
+
MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP 911
950
+
MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 912
951
+
MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 913
952
+
MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 914
953
+
MX6Q_PAD_KEY_ROW2__CAN1_RXCAN 915
954
+
MX6Q_PAD_KEY_ROW2__KPP_ROW_2 916
955
+
MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT 917
956
+
MX6Q_PAD_KEY_ROW2__GPIO_4_11 918
957
+
MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 919
958
+
MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 920
959
+
MX6Q_PAD_KEY_COL3__ECSPI1_SS3 921
960
+
MX6Q_PAD_KEY_COL3__ENET_CRS 922
961
+
MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 923
962
+
MX6Q_PAD_KEY_COL3__KPP_COL_3 924
963
+
MX6Q_PAD_KEY_COL3__I2C2_SCL 925
964
+
MX6Q_PAD_KEY_COL3__GPIO_4_12 926
965
+
MX6Q_PAD_KEY_COL3__SPDIF_IN1 927
966
+
MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 928
967
+
MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT 929
968
+
MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK 930
969
+
MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 931
970
+
MX6Q_PAD_KEY_ROW3__KPP_ROW_3 932
971
+
MX6Q_PAD_KEY_ROW3__I2C2_SDA 933
972
+
MX6Q_PAD_KEY_ROW3__GPIO_4_13 934
973
+
MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT 935
974
+
MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 936
975
+
MX6Q_PAD_KEY_COL4__CAN2_TXCAN 937
976
+
MX6Q_PAD_KEY_COL4__IPU1_SISG_4 938
977
+
MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC 939
978
+
MX6Q_PAD_KEY_COL4__KPP_COL_4 940
979
+
MX6Q_PAD_KEY_COL4__UART5_RTS 941
980
+
MX6Q_PAD_KEY_COL4__GPIO_4_14 942
981
+
MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 943
982
+
MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944
983
+
MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945
984
+
MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946
985
+
MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947
986
+
MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948
987
+
MX6Q_PAD_KEY_ROW4__UART5_CTS 949
988
+
MX6Q_PAD_KEY_ROW4__GPIO_4_15 950
989
+
MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951
990
+
MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952
991
+
MX6Q_PAD_GPIO_0__CCM_CLKO 953
992
+
MX6Q_PAD_GPIO_0__KPP_COL_5 954
993
+
MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955
994
+
MX6Q_PAD_GPIO_0__EPIT1_EPITO 956
995
+
MX6Q_PAD_GPIO_0__GPIO_1_0 957
996
+
MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958
997
+
MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959
998
+
MX6Q_PAD_GPIO_1__ESAI1_SCKR 960
999
+
MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961
1000
+
MX6Q_PAD_GPIO_1__KPP_ROW_5 962
1001
+
MX6Q_PAD_GPIO_1__PWM2_PWMO 963
1002
+
MX6Q_PAD_GPIO_1__GPIO_1_1 964
1003
+
MX6Q_PAD_GPIO_1__USDHC1_CD 965
1004
+
MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966
1005
+
MX6Q_PAD_GPIO_9__ESAI1_FSR 967
1006
+
MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968
1007
+
MX6Q_PAD_GPIO_9__KPP_COL_6 969
1008
+
MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970
1009
+
MX6Q_PAD_GPIO_9__PWM1_PWMO 971
1010
+
MX6Q_PAD_GPIO_9__GPIO_1_9 972
1011
+
MX6Q_PAD_GPIO_9__USDHC1_WP 973
1012
+
MX6Q_PAD_GPIO_9__SRC_EARLY_RST 974
1013
+
MX6Q_PAD_GPIO_3__ESAI1_HCKR 975
1014
+
MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 976
1015
+
MX6Q_PAD_GPIO_3__I2C3_SCL 977
1016
+
MX6Q_PAD_GPIO_3__ANATOP_24M_OUT 978
1017
+
MX6Q_PAD_GPIO_3__CCM_CLKO2 979
1018
+
MX6Q_PAD_GPIO_3__GPIO_1_3 980
1019
+
MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC 981
1020
+
MX6Q_PAD_GPIO_3__MLB_MLBCLK 982
1021
+
MX6Q_PAD_GPIO_6__ESAI1_SCKT 983
1022
+
MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 984
1023
+
MX6Q_PAD_GPIO_6__I2C3_SDA 985
1024
+
MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 986
1025
+
MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB 987
1026
+
MX6Q_PAD_GPIO_6__GPIO_1_6 988
1027
+
MX6Q_PAD_GPIO_6__USDHC2_LCTL 989
1028
+
MX6Q_PAD_GPIO_6__MLB_MLBSIG 990
1029
+
MX6Q_PAD_GPIO_2__ESAI1_FST 991
1030
+
MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 992
1031
+
MX6Q_PAD_GPIO_2__KPP_ROW_6 993
1032
+
MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 994
1033
+
MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 995
1034
+
MX6Q_PAD_GPIO_2__GPIO_1_2 996
1035
+
MX6Q_PAD_GPIO_2__USDHC2_WP 997
1036
+
MX6Q_PAD_GPIO_2__MLB_MLBDAT 998
1037
+
MX6Q_PAD_GPIO_4__ESAI1_HCKT 999
1038
+
MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 1000
1039
+
MX6Q_PAD_GPIO_4__KPP_COL_7 1001
1040
+
MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 1002
1041
+
MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1003
1042
+
MX6Q_PAD_GPIO_4__GPIO_1_4 1004
1043
+
MX6Q_PAD_GPIO_4__USDHC2_CD 1005
1044
+
MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA 1006
1045
+
MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 1007
1046
+
MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 1008
1047
+
MX6Q_PAD_GPIO_5__KPP_ROW_7 1009
1048
+
MX6Q_PAD_GPIO_5__CCM_CLKO 1010
1049
+
MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1011
1050
+
MX6Q_PAD_GPIO_5__GPIO_1_5 1012
1051
+
MX6Q_PAD_GPIO_5__I2C3_SCL 1013
1052
+
MX6Q_PAD_GPIO_5__CHEETAH_EVENTI 1014
1053
+
MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 1015
1054
+
MX6Q_PAD_GPIO_7__ECSPI5_RDY 1016
1055
+
MX6Q_PAD_GPIO_7__EPIT1_EPITO 1017
1056
+
MX6Q_PAD_GPIO_7__CAN1_TXCAN 1018
1057
+
MX6Q_PAD_GPIO_7__UART2_TXD 1019
1058
+
MX6Q_PAD_GPIO_7__GPIO_1_7 1020
1059
+
MX6Q_PAD_GPIO_7__SPDIF_PLOCK 1021
1060
+
MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE 1022
1061
+
MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 1023
1062
+
MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT 1024
1063
+
MX6Q_PAD_GPIO_8__EPIT2_EPITO 1025
1064
+
MX6Q_PAD_GPIO_8__CAN1_RXCAN 1026
1065
+
MX6Q_PAD_GPIO_8__UART2_RXD 1027
1066
+
MX6Q_PAD_GPIO_8__GPIO_1_8 1028
1067
+
MX6Q_PAD_GPIO_8__SPDIF_SRCLK 1029
1068
+
MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK 1030
1069
+
MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 1031
1070
+
MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 1032
1071
+
MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT 1033
1072
+
MX6Q_PAD_GPIO_16__USDHC1_LCTL 1034
1073
+
MX6Q_PAD_GPIO_16__SPDIF_IN1 1035
1074
+
MX6Q_PAD_GPIO_16__GPIO_7_11 1036
1075
+
MX6Q_PAD_GPIO_16__I2C3_SDA 1037
1076
+
MX6Q_PAD_GPIO_16__SJC_DE_B 1038
1077
+
MX6Q_PAD_GPIO_17__ESAI1_TX0 1039
1078
+
MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 1040
1079
+
MX6Q_PAD_GPIO_17__CCM_PMIC_RDY 1041
1080
+
MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 1042
1081
+
MX6Q_PAD_GPIO_17__SPDIF_OUT1 1043
1082
+
MX6Q_PAD_GPIO_17__GPIO_7_12 1044
1083
+
MX6Q_PAD_GPIO_17__SJC_JTAG_ACT 1045
1084
+
MX6Q_PAD_GPIO_18__ESAI1_TX1 1046
1085
+
MX6Q_PAD_GPIO_18__ENET_RX_CLK 1047
1086
+
MX6Q_PAD_GPIO_18__USDHC3_VSELECT 1048
1087
+
MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 1049
1088
+
MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK 1050
1089
+
MX6Q_PAD_GPIO_18__GPIO_7_13 1051
1090
+
MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 1052
1091
+
MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST 1053
1092
+
MX6Q_PAD_GPIO_19__KPP_COL_5 1054
1093
+
MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 1055
1094
+
MX6Q_PAD_GPIO_19__SPDIF_OUT1 1056
1095
+
MX6Q_PAD_GPIO_19__CCM_CLKO 1057
1096
+
MX6Q_PAD_GPIO_19__ECSPI1_RDY 1058
1097
+
MX6Q_PAD_GPIO_19__GPIO_4_5 1059
1098
+
MX6Q_PAD_GPIO_19__ENET_TX_ER 1060
1099
+
MX6Q_PAD_GPIO_19__SRC_INT_BOOT 1061
1100
+
MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 1062
1101
+
MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 1063
1102
+
MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 1064
1103
+
MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 1065
1104
+
MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 1066
1105
+
MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO 1067
1106
+
MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 1068
1107
+
MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 1069
1108
+
MX6Q_PAD_CSI0_MCLK__CCM_CLKO 1070
1109
+
MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 1071
1110
+
MX6Q_PAD_CSI0_MCLK__GPIO_5_19 1072
1111
+
MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 1073
1112
+
MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL 1074
1113
+
MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN 1075
1114
+
MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 1076
1115
+
MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 1077
1116
+
MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 1078
1117
+
MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 1079
1118
+
MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 1080
1119
+
MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK 1081
1120
+
MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 1082
1121
+
MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 1083
1122
+
MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 1084
1123
+
MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 1085
1124
+
MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 1086
1125
+
MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 1087
1126
+
MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 1088
1127
+
MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 1089
1128
+
MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 1090
1129
+
MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 1091
1130
+
MX6Q_PAD_CSI0_DAT4__KPP_COL_5 1092
1131
+
MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 1093
1132
+
MX6Q_PAD_CSI0_DAT4__GPIO_5_22 1094
1133
+
MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 1095
1134
+
MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 1096
1135
+
MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 1097
1136
+
MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 1098
1137
+
MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 1099
1138
+
MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 1100
1139
+
MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 1101
1140
+
MX6Q_PAD_CSI0_DAT5__GPIO_5_23 1102
1141
+
MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 1103
1142
+
MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 1104
1143
+
MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 1105
1144
+
MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 1106
1145
+
MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 1107
1146
+
MX6Q_PAD_CSI0_DAT6__KPP_COL_6 1108
1147
+
MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 1109
1148
+
MX6Q_PAD_CSI0_DAT6__GPIO_5_24 1110
1149
+
MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 1111
1150
+
MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 1112
1151
+
MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 1113
1152
+
MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 1114
1153
+
MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 1115
1154
+
MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 1116
1155
+
MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 1117
1156
+
MX6Q_PAD_CSI0_DAT7__GPIO_5_25 1118
1157
+
MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 1119
1158
+
MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 1120
1159
+
MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 1121
1160
+
MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 1122
1161
+
MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 1123
1162
+
MX6Q_PAD_CSI0_DAT8__KPP_COL_7 1124
1163
+
MX6Q_PAD_CSI0_DAT8__I2C1_SDA 1125
1164
+
MX6Q_PAD_CSI0_DAT8__GPIO_5_26 1126
1165
+
MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 1127
1166
+
MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 1128
1167
+
MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 1129
1168
+
MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 1130
1169
+
MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 1131
1170
+
MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 1132
1171
+
MX6Q_PAD_CSI0_DAT9__I2C1_SCL 1133
1172
+
MX6Q_PAD_CSI0_DAT9__GPIO_5_27 1134
1173
+
MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 1135
1174
+
MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 1136
1175
+
MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 1137
1176
+
MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 1138
1177
+
MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 1139
1178
+
MX6Q_PAD_CSI0_DAT10__UART1_TXD 1140
1179
+
MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 1141
1180
+
MX6Q_PAD_CSI0_DAT10__GPIO_5_28 1142
1181
+
MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 1143
1182
+
MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 1144
1183
+
MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 1145
1184
+
MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 1146
1185
+
MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 1147
1186
+
MX6Q_PAD_CSI0_DAT11__UART1_RXD 1148
1187
+
MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 1149
1188
+
MX6Q_PAD_CSI0_DAT11__GPIO_5_29 1150
1189
+
MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 1151
1190
+
MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 1152
1191
+
MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 1153
1192
+
MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 1154
1193
+
MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 1155
1194
+
MX6Q_PAD_CSI0_DAT12__UART4_TXD 1156
1195
+
MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 1157
1196
+
MX6Q_PAD_CSI0_DAT12__GPIO_5_30 1158
1197
+
MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 1159
1198
+
MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 1160
1199
+
MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 1161
1200
+
MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 1162
1201
+
MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 1163
1202
+
MX6Q_PAD_CSI0_DAT13__UART4_RXD 1164
1203
+
MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 1165
1204
+
MX6Q_PAD_CSI0_DAT13__GPIO_5_31 1166
1205
+
MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 1167
1206
+
MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 1168
1207
+
MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 1169
1208
+
MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 1170
1209
+
MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 1171
1210
+
MX6Q_PAD_CSI0_DAT14__UART5_TXD 1172
1211
+
MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 1173
1212
+
MX6Q_PAD_CSI0_DAT14__GPIO_6_0 1174
1213
+
MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 1175
1214
+
MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 1176
1215
+
MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 1177
1216
+
MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 1178
1217
+
MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 1179
1218
+
MX6Q_PAD_CSI0_DAT15__UART5_RXD 1180
1219
+
MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 1181
1220
+
MX6Q_PAD_CSI0_DAT15__GPIO_6_1 1182
1221
+
MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 1183
1222
+
MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 1184
1223
+
MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 1185
1224
+
MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 1186
1225
+
MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 1187
1226
+
MX6Q_PAD_CSI0_DAT16__UART4_RTS 1188
1227
+
MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 1189
1228
+
MX6Q_PAD_CSI0_DAT16__GPIO_6_2 1190
1229
+
MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 1191
1230
+
MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 1192
1231
+
MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 1193
1232
+
MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 1194
1233
+
MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 1195
1234
+
MX6Q_PAD_CSI0_DAT17__UART4_CTS 1196
1235
+
MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 1197
1236
+
MX6Q_PAD_CSI0_DAT17__GPIO_6_3 1198
1237
+
MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 1199
1238
+
MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 1200
1239
+
MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 1201
1240
+
MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 1202
1241
+
MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 1203
1242
+
MX6Q_PAD_CSI0_DAT18__UART5_RTS 1204
1243
+
MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 1205
1244
+
MX6Q_PAD_CSI0_DAT18__GPIO_6_4 1206
1245
+
MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 1207
1246
+
MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 1208
1247
+
MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 1209
1248
+
MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 1210
1249
+
MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 1211
1250
+
MX6Q_PAD_CSI0_DAT19__UART5_CTS 1212
1251
+
MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 1213
1252
+
MX6Q_PAD_CSI0_DAT19__GPIO_6_5 1214
1253
+
MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 1215
1254
+
MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 1216
1255
+
MX6Q_PAD_JTAG_TMS__SJC_TMS 1217
1256
+
MX6Q_PAD_JTAG_MOD__SJC_MOD 1218
1257
+
MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB 1219
1258
+
MX6Q_PAD_JTAG_TDI__SJC_TDI 1220
1259
+
MX6Q_PAD_JTAG_TCK__SJC_TCK 1221
1260
+
MX6Q_PAD_JTAG_TDO__SJC_TDO 1222
1261
+
MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 1223
1262
+
MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 1224
1263
+
MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 1225
1264
+
MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 1226
1265
+
MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 1227
1266
+
MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 1228
1267
+
MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 1229
1268
+
MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 1230
1269
+
MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 1231
1270
+
MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 1232
1271
+
MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 1233
1272
+
MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM 1234
1273
+
MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ 1235
1274
+
MX6Q_PAD_POR_B__SRC_POR_B 1236
1275
+
MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 1237
1276
+
MX6Q_PAD_RESET_IN_B__SRC_RESET_B 1238
1277
+
MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 1239
1278
+
MX6Q_PAD_TEST_MODE__TCU_TEST_MODE 1240
1279
+
MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 1241
1280
+
MX6Q_PAD_SD3_DAT7__UART1_TXD 1242
1281
+
MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 1243
1282
+
MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 1244
1283
+
MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 1245
1284
+
MX6Q_PAD_SD3_DAT7__GPIO_6_17 1246
1285
+
MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 1247
1286
+
MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV 1248
1287
+
MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 1249
1288
+
MX6Q_PAD_SD3_DAT6__UART1_RXD 1250
1289
+
MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 1251
1290
+
MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 1252
1291
+
MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 1253
1292
+
MX6Q_PAD_SD3_DAT6__GPIO_6_18 1254
1293
+
MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 1255
1294
+
MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 1256
1295
+
MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 1257
1296
+
MX6Q_PAD_SD3_DAT5__UART2_TXD 1258
1297
+
MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 1259
1298
+
MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 1260
1299
+
MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 1261
1300
+
MX6Q_PAD_SD3_DAT5__GPIO_7_0 1262
1301
+
MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 1263
1302
+
MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 1264
1303
+
MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 1265
1304
+
MX6Q_PAD_SD3_DAT4__UART2_RXD 1266
1305
+
MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 1267
1306
+
MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 1268
1307
+
MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 1269
1308
+
MX6Q_PAD_SD3_DAT4__GPIO_7_1 1270
1309
+
MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 1271
1310
+
MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 1272
1311
+
MX6Q_PAD_SD3_CMD__USDHC3_CMD 1273
1312
+
MX6Q_PAD_SD3_CMD__UART2_CTS 1274
1313
+
MX6Q_PAD_SD3_CMD__CAN1_TXCAN 1275
1314
+
MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 1276
1315
+
MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 1277
1316
+
MX6Q_PAD_SD3_CMD__GPIO_7_2 1278
1317
+
MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 1279
1318
+
MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 1280
1319
+
MX6Q_PAD_SD3_CLK__USDHC3_CLK 1281
1320
+
MX6Q_PAD_SD3_CLK__UART2_RTS 1282
1321
+
MX6Q_PAD_SD3_CLK__CAN1_RXCAN 1283
1322
+
MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 1284
1323
+
MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 1285
1324
+
MX6Q_PAD_SD3_CLK__GPIO_7_3 1286
1325
+
MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 1287
1326
+
MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 1288
1327
+
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 1289
1328
+
MX6Q_PAD_SD3_DAT0__UART1_CTS 1290
1329
+
MX6Q_PAD_SD3_DAT0__CAN2_TXCAN 1291
1330
+
MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 1292
1331
+
MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 1293
1332
+
MX6Q_PAD_SD3_DAT0__GPIO_7_4 1294
1333
+
MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 1295
1334
+
MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 1296
1335
+
MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 1297
1336
+
MX6Q_PAD_SD3_DAT1__UART1_RTS 1298
1337
+
MX6Q_PAD_SD3_DAT1__CAN2_RXCAN 1299
1338
+
MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 1300
1339
+
MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 1301
1340
+
MX6Q_PAD_SD3_DAT1__GPIO_7_5 1302
1341
+
MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 1303
1342
+
MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 1304
1343
+
MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 1305
1344
+
MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 1306
1345
+
MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 1307
1346
+
MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 1308
1347
+
MX6Q_PAD_SD3_DAT2__GPIO_7_6 1309
1348
+
MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 1310
1349
+
MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 1311
1350
+
MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 1312
1351
+
MX6Q_PAD_SD3_DAT3__UART3_CTS 1313
1352
+
MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 1314
1353
+
MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 1315
1354
+
MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 1316
1355
+
MX6Q_PAD_SD3_DAT3__GPIO_7_7 1317
1356
+
MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 1318
1357
+
MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 1319
1358
+
MX6Q_PAD_SD3_RST__USDHC3_RST 1320
1359
+
MX6Q_PAD_SD3_RST__UART3_RTS 1321
1360
+
MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 1322
1361
+
MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 1323
1362
+
MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 1324
1363
+
MX6Q_PAD_SD3_RST__GPIO_7_8 1325
1364
+
MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 1326
1365
+
MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 1327
1366
+
MX6Q_PAD_NANDF_CLE__RAWNAND_CLE 1328
1367
+
MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 1329
1368
+
MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 1330
1369
+
MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 1331
1370
+
MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 1332
1371
+
MX6Q_PAD_NANDF_CLE__GPIO_6_7 1333
1372
+
MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 1334
1373
+
MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 1335
1374
+
MX6Q_PAD_NANDF_ALE__RAWNAND_ALE 1336
1375
+
MX6Q_PAD_NANDF_ALE__USDHC4_RST 1337
1376
+
MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 1338
1377
+
MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 1339
1378
+
MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 1340
1379
+
MX6Q_PAD_NANDF_ALE__GPIO_6_8 1341
1380
+
MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 1342
1381
+
MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 1343
1382
+
MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN 1344
1383
+
MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 1345
1384
+
MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 1346
1385
+
MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 1347
1386
+
MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 1348
1387
+
MX6Q_PAD_NANDF_WP_B__GPIO_6_9 1349
1388
+
MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 1350
1389
+
MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 1351
1390
+
MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 1352
1391
+
MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 1353
1392
+
MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 1354
1393
+
MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 1355
1394
+
MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 1356
1395
+
MX6Q_PAD_NANDF_RB0__GPIO_6_10 1357
1396
+
MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 1358
1397
+
MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 1359
1398
+
MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N 1360
1399
+
MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 1361
1400
+
MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 1362
1401
+
MX6Q_PAD_NANDF_CS0__GPIO_6_11 1363
1402
+
MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 1364
1403
+
MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N 1365
1404
+
MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT 1366
1405
+
MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT 1367
1406
+
MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 1368
1407
+
MX6Q_PAD_NANDF_CS1__GPIO_6_14 1369
1408
+
MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT 1370
1409
+
MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N 1371
1410
+
MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 1372
1411
+
MX6Q_PAD_NANDF_CS2__ESAI1_TX0 1373
1412
+
MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE 1374
1413
+
MX6Q_PAD_NANDF_CS2__CCM_CLKO2 1375
1414
+
MX6Q_PAD_NANDF_CS2__GPIO_6_15 1376
1415
+
MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 1377
1416
+
MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N 1378
1417
+
MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 1379
1418
+
MX6Q_PAD_NANDF_CS3__ESAI1_TX1 1380
1419
+
MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 1381
1420
+
MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 1382
1421
+
MX6Q_PAD_NANDF_CS3__GPIO_6_16 1383
1422
+
MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 1384
1423
+
MX6Q_PAD_NANDF_CS3__TPSMP_CLK 1385
1424
+
MX6Q_PAD_SD4_CMD__USDHC4_CMD 1386
1425
+
MX6Q_PAD_SD4_CMD__RAWNAND_RDN 1387
1426
+
MX6Q_PAD_SD4_CMD__UART3_TXD 1388
1427
+
MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 1389
1428
+
MX6Q_PAD_SD4_CMD__GPIO_7_9 1390
1429
+
MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR 1391
1430
+
MX6Q_PAD_SD4_CLK__USDHC4_CLK 1392
1431
+
MX6Q_PAD_SD4_CLK__RAWNAND_WRN 1393
1432
+
MX6Q_PAD_SD4_CLK__UART3_RXD 1394
1433
+
MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 1395
1434
+
MX6Q_PAD_SD4_CLK__GPIO_7_10 1396
1435
+
MX6Q_PAD_NANDF_D0__RAWNAND_D0 1397
1436
+
MX6Q_PAD_NANDF_D0__USDHC1_DAT4 1398
1437
+
MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 1399
1438
+
MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 1400
1439
+
MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 1401
1440
+
MX6Q_PAD_NANDF_D0__GPIO_2_0 1402
1441
+
MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 1403
1442
+
MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 1404
1443
+
MX6Q_PAD_NANDF_D1__RAWNAND_D1 1405
1444
+
MX6Q_PAD_NANDF_D1__USDHC1_DAT5 1406
1445
+
MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 1407
1446
+
MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 1408
1447
+
MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 1409
1448
+
MX6Q_PAD_NANDF_D1__GPIO_2_1 1410
1449
+
MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 1411
1450
+
MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 1412
1451
+
MX6Q_PAD_NANDF_D2__RAWNAND_D2 1413
1452
+
MX6Q_PAD_NANDF_D2__USDHC1_DAT6 1414
1453
+
MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 1415
1454
+
MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 1416
1455
+
MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 1417
1456
+
MX6Q_PAD_NANDF_D2__GPIO_2_2 1418
1457
+
MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 1419
1458
+
MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 1420
1459
+
MX6Q_PAD_NANDF_D3__RAWNAND_D3 1421
1460
+
MX6Q_PAD_NANDF_D3__USDHC1_DAT7 1422
1461
+
MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 1423
1462
+
MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 1424
1463
+
MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 1425
1464
+
MX6Q_PAD_NANDF_D3__GPIO_2_3 1426
1465
+
MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 1427
1466
+
MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 1428
1467
+
MX6Q_PAD_NANDF_D4__RAWNAND_D4 1429
1468
+
MX6Q_PAD_NANDF_D4__USDHC2_DAT4 1430
1469
+
MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 1431
1470
+
MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 1432
1471
+
MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 1433
1472
+
MX6Q_PAD_NANDF_D4__GPIO_2_4 1434
1473
+
MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 1435
1474
+
MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 1436
1475
+
MX6Q_PAD_NANDF_D5__RAWNAND_D5 1437
1476
+
MX6Q_PAD_NANDF_D5__USDHC2_DAT5 1438
1477
+
MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 1439
1478
+
MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 1440
1479
+
MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 1441
1480
+
MX6Q_PAD_NANDF_D5__GPIO_2_5 1442
1481
+
MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 1443
1482
+
MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 1444
1483
+
MX6Q_PAD_NANDF_D6__RAWNAND_D6 1445
1484
+
MX6Q_PAD_NANDF_D6__USDHC2_DAT6 1446
1485
+
MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 1447
1486
+
MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 1448
1487
+
MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 1449
1488
+
MX6Q_PAD_NANDF_D6__GPIO_2_6 1450
1489
+
MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 1451
1490
+
MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 1452
1491
+
MX6Q_PAD_NANDF_D7__RAWNAND_D7 1453
1492
+
MX6Q_PAD_NANDF_D7__USDHC2_DAT7 1454
1493
+
MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 1455
1494
+
MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 1456
1495
+
MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 1457
1496
+
MX6Q_PAD_NANDF_D7__GPIO_2_7 1458
1497
+
MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 1459
1498
+
MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 1460
1499
+
MX6Q_PAD_SD4_DAT0__RAWNAND_D8 1461
1500
+
MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 1462
1501
+
MX6Q_PAD_SD4_DAT0__RAWNAND_DQS 1463
1502
+
MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 1464
1503
+
MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 1465
1504
+
MX6Q_PAD_SD4_DAT0__GPIO_2_8 1466
1505
+
MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 1467
1506
+
MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 1468
1507
+
MX6Q_PAD_SD4_DAT1__RAWNAND_D9 1469
1508
+
MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 1470
1509
+
MX6Q_PAD_SD4_DAT1__PWM3_PWMO 1471
1510
+
MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 1472
1511
+
MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 1473
1512
+
MX6Q_PAD_SD4_DAT1__GPIO_2_9 1474
1513
+
MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 1475
1514
+
MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 1476
1515
+
MX6Q_PAD_SD4_DAT2__RAWNAND_D10 1477
1516
+
MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 1478
1517
+
MX6Q_PAD_SD4_DAT2__PWM4_PWMO 1479
1518
+
MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 1480
1519
+
MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 1481
1520
+
MX6Q_PAD_SD4_DAT2__GPIO_2_10 1482
1521
+
MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 1483
1522
+
MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 1484
1523
+
MX6Q_PAD_SD4_DAT3__RAWNAND_D11 1485
1524
+
MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 1486
1525
+
MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 1487
1526
+
MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 1488
1527
+
MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489
1528
+
MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490
1529
+
MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491
1530
+
MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492
1531
+
MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493
1532
+
MX6Q_PAD_SD4_DAT4__UART2_RXD 1494
1533
+
MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495
1534
+
MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496
1535
+
MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497
1536
+
MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498
1537
+
MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499
1538
+
MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500
1539
+
MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501
1540
+
MX6Q_PAD_SD4_DAT5__UART2_RTS 1502
1541
+
MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503
1542
+
MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504
1543
+
MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505
1544
+
MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506
1545
+
MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507
1546
+
MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508
1547
+
MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509
1548
+
MX6Q_PAD_SD4_DAT6__UART2_CTS 1510
1549
+
MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511
1550
+
MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512
1551
+
MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513
1552
+
MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514
1553
+
MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515
1554
+
MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516
1555
+
MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517
1556
+
MX6Q_PAD_SD4_DAT7__UART2_TXD 1518
1557
+
MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519
1558
+
MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520
1559
+
MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521
1560
+
MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522
1561
+
MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523
1562
+
MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524
1563
+
MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525
1564
+
MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526
1565
+
MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527
1566
+
MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528
1567
+
MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529
1568
+
MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530
1569
+
MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531
1570
+
MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532
1571
+
MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533
1572
+
MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534
1573
+
MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535
1574
+
MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536
1575
+
MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537
1576
+
MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538
1577
+
MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539
1578
+
MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540
1579
+
MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541
1580
+
MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542
1581
+
MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543
1582
+
MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544
1583
+
MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545
1584
+
MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546
1585
+
MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547
1586
+
MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548
1587
+
MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549
1588
+
MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550
1589
+
MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551
1590
+
MX6Q_PAD_SD1_CMD__GPIO_1_18 1552
1591
+
MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553
1592
+
MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554
1593
+
MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555
1594
+
MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556
1595
+
MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557
1596
+
MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558
1597
+
MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559
1598
+
MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560
1599
+
MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561
1600
+
MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562
1601
+
MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563
1602
+
MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564
1603
+
MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565
1604
+
MX6Q_PAD_SD1_CLK__GPIO_1_20 1566
1605
+
MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567
1606
+
MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568
1607
+
MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569
1608
+
MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570
1609
+
MX6Q_PAD_SD2_CLK__KPP_COL_5 1571
1610
+
MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572
1611
+
MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573
1612
+
MX6Q_PAD_SD2_CLK__GPIO_1_10 1574
1613
+
MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575
1614
+
MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576
1615
+
MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577
1616
+
MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578
1617
+
MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579
1618
+
MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580
1619
+
MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581
1620
+
MX6Q_PAD_SD2_CMD__GPIO_1_11 1582
1621
+
MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583
1622
+
MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584
1623
+
MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585
1624
+
MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586
1625
+
MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587
1626
+
MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588
1627
+
MX6Q_PAD_SD2_DAT3__SJC_DONE 1589
1628
+
MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590
+918
Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
+918
Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
···
1
+
* Freescale MXS Pin Controller
2
+
3
+
The pins controlled by mxs pin controller are organized in banks, each bank
4
+
has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
5
+
function is GPIO. The configuration on the pins includes drive strength,
6
+
voltage and pull-up.
7
+
8
+
Required properties:
9
+
- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10
+
- reg: Should contain the register physical address and length for the
11
+
pin controller.
12
+
13
+
Please refer to pinctrl-bindings.txt in this directory for details of the
14
+
common pinctrl bindings used by client devices.
15
+
16
+
The node of mxs pin controller acts as a container for an arbitrary number of
17
+
subnodes. Each of these subnodes represents some desired configuration for
18
+
a group of pins, and only affects those parameters that are explicitly listed.
19
+
In other words, a subnode that describes a drive strength parameter implies no
20
+
information about pull-up. For this reason, even seemingly boolean values are
21
+
actually tristates in this binding: unspecified, off, or on. Unspecified is
22
+
represented as an absent property, and off/on are represented as integer
23
+
values 0 and 1.
24
+
25
+
Those subnodes under mxs pin controller node will fall into two categories.
26
+
One is to set up a group of pins for a function, both mux selection and pin
27
+
configurations, and it's called group node in the binding document. The other
28
+
one is to adjust the pin configuration for some particular pins that need a
29
+
different configuration than what is defined in group node. The binding
30
+
document calls this type of node config node.
31
+
32
+
On mxs, there is no hardware pin group. The pin group in this binding only
33
+
means a group of pins put together for particular peripheral to work in
34
+
particular function, like SSP0 functioning as mmc0-8bit. That said, the
35
+
group node should include all the pins needed for one function rather than
36
+
having these pins defined in several group nodes. It also means each of
37
+
"pinctrl-*" phandle in client device node should only have one group node
38
+
pointed in there, while the phandle can have multiple config node referenced
39
+
there to adjust configurations for some pins in the group.
40
+
41
+
Required subnode-properties:
42
+
- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
43
+
with given mux function, with bank, pin and mux packed as below.
44
+
45
+
[15..12] : bank number
46
+
[11..4] : pin number
47
+
[3..0] : mux selection
48
+
49
+
This integer with mux selection packed is used as an entity by both group
50
+
and config nodes to identify a pin. The mux selection in the integer takes
51
+
effects only on group node, and will get ignored by driver with config node,
52
+
since config node is only meant to set up pin configurations.
53
+
54
+
Valid values for these integers are listed below.
55
+
56
+
- reg: Should be the index of the group nodes for same function. This property
57
+
is required only for group nodes, and should not be present in any config
58
+
nodes.
59
+
60
+
Optional subnode-properties:
61
+
- fsl,drive-strength: Integer.
62
+
0: 4 mA
63
+
1: 8 mA
64
+
2: 12 mA
65
+
3: 16 mA
66
+
- fsl,voltage: Integer.
67
+
0: 1.8 V
68
+
1: 3.3 V
69
+
- fsl,pull-up: Integer.
70
+
0: Disable the internal pull-up
71
+
1: Enable the internal pull-up
72
+
73
+
Examples:
74
+
75
+
pinctrl@80018000 {
76
+
#address-cells = <1>;
77
+
#size-cells = <0>;
78
+
compatible = "fsl,imx28-pinctrl";
79
+
reg = <0x80018000 2000>;
80
+
81
+
mmc0_8bit_pins_a: mmc0-8bit@0 {
82
+
reg = <0>;
83
+
fsl,pinmux-ids = <
84
+
0x2000 0x2010 0x2020 0x2030
85
+
0x2040 0x2050 0x2060 0x2070
86
+
0x2080 0x2090 0x20a0>;
87
+
fsl,drive-strength = <1>;
88
+
fsl,voltage = <1>;
89
+
fsl,pull-up = <1>;
90
+
};
91
+
92
+
mmc_cd_cfg: mmc-cd-cfg {
93
+
fsl,pinmux-ids = <0x2090>;
94
+
fsl,pull-up = <0>;
95
+
};
96
+
97
+
mmc_sck_cfg: mmc-sck-cfg {
98
+
fsl,pinmux-ids = <0x20a0>;
99
+
fsl,drive-strength = <2>;
100
+
fsl,pull-up = <0>;
101
+
};
102
+
};
103
+
104
+
In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
105
+
to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
106
+
applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are
107
+
adjusting the configuration for pins card-detection and clock from what group
108
+
node mmc0-8bit defines. Only the configuration properties to be adjusted need
109
+
to be listed in the config nodes.
110
+
111
+
Valid values for i.MX28 pinmux-id:
112
+
113
+
pinmux id
114
+
------ --
115
+
MX28_PAD_GPMI_D00__GPMI_D0 0x0000
116
+
MX28_PAD_GPMI_D01__GPMI_D1 0x0010
117
+
MX28_PAD_GPMI_D02__GPMI_D2 0x0020
118
+
MX28_PAD_GPMI_D03__GPMI_D3 0x0030
119
+
MX28_PAD_GPMI_D04__GPMI_D4 0x0040
120
+
MX28_PAD_GPMI_D05__GPMI_D5 0x0050
121
+
MX28_PAD_GPMI_D06__GPMI_D6 0x0060
122
+
MX28_PAD_GPMI_D07__GPMI_D7 0x0070
123
+
MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
124
+
MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
125
+
MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
126
+
MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130
127
+
MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140
128
+
MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150
129
+
MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160
130
+
MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170
131
+
MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180
132
+
MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190
133
+
MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0
134
+
MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0
135
+
MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0
136
+
MX28_PAD_LCD_D00__LCD_D0 0x1000
137
+
MX28_PAD_LCD_D01__LCD_D1 0x1010
138
+
MX28_PAD_LCD_D02__LCD_D2 0x1020
139
+
MX28_PAD_LCD_D03__LCD_D3 0x1030
140
+
MX28_PAD_LCD_D04__LCD_D4 0x1040
141
+
MX28_PAD_LCD_D05__LCD_D5 0x1050
142
+
MX28_PAD_LCD_D06__LCD_D6 0x1060
143
+
MX28_PAD_LCD_D07__LCD_D7 0x1070
144
+
MX28_PAD_LCD_D08__LCD_D8 0x1080
145
+
MX28_PAD_LCD_D09__LCD_D9 0x1090
146
+
MX28_PAD_LCD_D10__LCD_D10 0x10a0
147
+
MX28_PAD_LCD_D11__LCD_D11 0x10b0
148
+
MX28_PAD_LCD_D12__LCD_D12 0x10c0
149
+
MX28_PAD_LCD_D13__LCD_D13 0x10d0
150
+
MX28_PAD_LCD_D14__LCD_D14 0x10e0
151
+
MX28_PAD_LCD_D15__LCD_D15 0x10f0
152
+
MX28_PAD_LCD_D16__LCD_D16 0x1100
153
+
MX28_PAD_LCD_D17__LCD_D17 0x1110
154
+
MX28_PAD_LCD_D18__LCD_D18 0x1120
155
+
MX28_PAD_LCD_D19__LCD_D19 0x1130
156
+
MX28_PAD_LCD_D20__LCD_D20 0x1140
157
+
MX28_PAD_LCD_D21__LCD_D21 0x1150
158
+
MX28_PAD_LCD_D22__LCD_D22 0x1160
159
+
MX28_PAD_LCD_D23__LCD_D23 0x1170
160
+
MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180
161
+
MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190
162
+
MX28_PAD_LCD_RS__LCD_RS 0x11a0
163
+
MX28_PAD_LCD_CS__LCD_CS 0x11b0
164
+
MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0
165
+
MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0
166
+
MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0
167
+
MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0
168
+
MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000
169
+
MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010
170
+
MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020
171
+
MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030
172
+
MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040
173
+
MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050
174
+
MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060
175
+
MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070
176
+
MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080
177
+
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090
178
+
MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0
179
+
MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0
180
+
MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0
181
+
MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0
182
+
MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0
183
+
MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100
184
+
MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110
185
+
MX28_PAD_SSP2_MISO__SSP2_D0 0x2120
186
+
MX28_PAD_SSP2_SS0__SSP2_D3 0x2130
187
+
MX28_PAD_SSP2_SS1__SSP2_D4 0x2140
188
+
MX28_PAD_SSP2_SS2__SSP2_D5 0x2150
189
+
MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180
190
+
MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190
191
+
MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0
192
+
MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0
193
+
MX28_PAD_AUART0_RX__AUART0_RX 0x3000
194
+
MX28_PAD_AUART0_TX__AUART0_TX 0x3010
195
+
MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020
196
+
MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030
197
+
MX28_PAD_AUART1_RX__AUART1_RX 0x3040
198
+
MX28_PAD_AUART1_TX__AUART1_TX 0x3050
199
+
MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060
200
+
MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070
201
+
MX28_PAD_AUART2_RX__AUART2_RX 0x3080
202
+
MX28_PAD_AUART2_TX__AUART2_TX 0x3090
203
+
MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0
204
+
MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0
205
+
MX28_PAD_AUART3_RX__AUART3_RX 0x30c0
206
+
MX28_PAD_AUART3_TX__AUART3_TX 0x30d0
207
+
MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0
208
+
MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0
209
+
MX28_PAD_PWM0__PWM_0 0x3100
210
+
MX28_PAD_PWM1__PWM_1 0x3110
211
+
MX28_PAD_PWM2__PWM_2 0x3120
212
+
MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140
213
+
MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150
214
+
MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160
215
+
MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170
216
+
MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180
217
+
MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190
218
+
MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0
219
+
MX28_PAD_SPDIF__SPDIF_TX 0x31b0
220
+
MX28_PAD_PWM3__PWM_3 0x31c0
221
+
MX28_PAD_PWM4__PWM_4 0x31d0
222
+
MX28_PAD_LCD_RESET__LCD_RESET 0x31e0
223
+
MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000
224
+
MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010
225
+
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020
226
+
MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030
227
+
MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040
228
+
MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050
229
+
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060
230
+
MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070
231
+
MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080
232
+
MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090
233
+
MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0
234
+
MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0
235
+
MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0
236
+
MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0
237
+
MX28_PAD_ENET0_COL__ENET0_COL 0x40e0
238
+
MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0
239
+
MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100
240
+
MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140
241
+
MX28_PAD_EMI_D00__EMI_DATA0 0x5000
242
+
MX28_PAD_EMI_D01__EMI_DATA1 0x5010
243
+
MX28_PAD_EMI_D02__EMI_DATA2 0x5020
244
+
MX28_PAD_EMI_D03__EMI_DATA3 0x5030
245
+
MX28_PAD_EMI_D04__EMI_DATA4 0x5040
246
+
MX28_PAD_EMI_D05__EMI_DATA5 0x5050
247
+
MX28_PAD_EMI_D06__EMI_DATA6 0x5060
248
+
MX28_PAD_EMI_D07__EMI_DATA7 0x5070
249
+
MX28_PAD_EMI_D08__EMI_DATA8 0x5080
250
+
MX28_PAD_EMI_D09__EMI_DATA9 0x5090
251
+
MX28_PAD_EMI_D10__EMI_DATA10 0x50a0
252
+
MX28_PAD_EMI_D11__EMI_DATA11 0x50b0
253
+
MX28_PAD_EMI_D12__EMI_DATA12 0x50c0
254
+
MX28_PAD_EMI_D13__EMI_DATA13 0x50d0
255
+
MX28_PAD_EMI_D14__EMI_DATA14 0x50e0
256
+
MX28_PAD_EMI_D15__EMI_DATA15 0x50f0
257
+
MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100
258
+
MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110
259
+
MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120
260
+
MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130
261
+
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
262
+
MX28_PAD_EMI_CLK__EMI_CLK 0x5150
263
+
MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160
264
+
MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170
265
+
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0
266
+
MX28_PAD_EMI_A00__EMI_ADDR0 0x6000
267
+
MX28_PAD_EMI_A01__EMI_ADDR1 0x6010
268
+
MX28_PAD_EMI_A02__EMI_ADDR2 0x6020
269
+
MX28_PAD_EMI_A03__EMI_ADDR3 0x6030
270
+
MX28_PAD_EMI_A04__EMI_ADDR4 0x6040
271
+
MX28_PAD_EMI_A05__EMI_ADDR5 0x6050
272
+
MX28_PAD_EMI_A06__EMI_ADDR6 0x6060
273
+
MX28_PAD_EMI_A07__EMI_ADDR7 0x6070
274
+
MX28_PAD_EMI_A08__EMI_ADDR8 0x6080
275
+
MX28_PAD_EMI_A09__EMI_ADDR9 0x6090
276
+
MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0
277
+
MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0
278
+
MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0
279
+
MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0
280
+
MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0
281
+
MX28_PAD_EMI_BA0__EMI_BA0 0x6100
282
+
MX28_PAD_EMI_BA1__EMI_BA1 0x6110
283
+
MX28_PAD_EMI_BA2__EMI_BA2 0x6120
284
+
MX28_PAD_EMI_CASN__EMI_CASN 0x6130
285
+
MX28_PAD_EMI_RASN__EMI_RASN 0x6140
286
+
MX28_PAD_EMI_WEN__EMI_WEN 0x6150
287
+
MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160
288
+
MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170
289
+
MX28_PAD_EMI_CKE__EMI_CKE 0x6180
290
+
MX28_PAD_GPMI_D00__SSP1_D0 0x0001
291
+
MX28_PAD_GPMI_D01__SSP1_D1 0x0011
292
+
MX28_PAD_GPMI_D02__SSP1_D2 0x0021
293
+
MX28_PAD_GPMI_D03__SSP1_D3 0x0031
294
+
MX28_PAD_GPMI_D04__SSP1_D4 0x0041
295
+
MX28_PAD_GPMI_D05__SSP1_D5 0x0051
296
+
MX28_PAD_GPMI_D06__SSP1_D6 0x0061
297
+
MX28_PAD_GPMI_D07__SSP1_D7 0x0071
298
+
MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101
299
+
MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111
300
+
MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121
301
+
MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131
302
+
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141
303
+
MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151
304
+
MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161
305
+
MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171
306
+
MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181
307
+
MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191
308
+
MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1
309
+
MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1
310
+
MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1
311
+
MX28_PAD_LCD_D03__ETM_DA8 0x1031
312
+
MX28_PAD_LCD_D04__ETM_DA9 0x1041
313
+
MX28_PAD_LCD_D08__ETM_DA3 0x1081
314
+
MX28_PAD_LCD_D09__ETM_DA4 0x1091
315
+
MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141
316
+
MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151
317
+
MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161
318
+
MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171
319
+
MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181
320
+
MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191
321
+
MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1
322
+
MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1
323
+
MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1
324
+
MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1
325
+
MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1
326
+
MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041
327
+
MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051
328
+
MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061
329
+
MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071
330
+
MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1
331
+
MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1
332
+
MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1
333
+
MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1
334
+
MX28_PAD_SSP2_SCK__AUART2_RX 0x2101
335
+
MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111
336
+
MX28_PAD_SSP2_MISO__AUART3_RX 0x2121
337
+
MX28_PAD_SSP2_SS0__AUART3_TX 0x2131
338
+
MX28_PAD_SSP2_SS1__SSP2_D1 0x2141
339
+
MX28_PAD_SSP2_SS2__SSP2_D2 0x2151
340
+
MX28_PAD_SSP3_SCK__AUART4_TX 0x2181
341
+
MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191
342
+
MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1
343
+
MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1
344
+
MX28_PAD_AUART0_RX__I2C0_SCL 0x3001
345
+
MX28_PAD_AUART0_TX__I2C0_SDA 0x3011
346
+
MX28_PAD_AUART0_CTS__AUART4_RX 0x3021
347
+
MX28_PAD_AUART0_RTS__AUART4_TX 0x3031
348
+
MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041
349
+
MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051
350
+
MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061
351
+
MX28_PAD_AUART1_RTS__USB0_ID 0x3071
352
+
MX28_PAD_AUART2_RX__SSP3_D1 0x3081
353
+
MX28_PAD_AUART2_TX__SSP3_D2 0x3091
354
+
MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1
355
+
MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1
356
+
MX28_PAD_AUART3_RX__CAN0_TX 0x30c1
357
+
MX28_PAD_AUART3_TX__CAN0_RX 0x30d1
358
+
MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1
359
+
MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1
360
+
MX28_PAD_PWM0__I2C1_SCL 0x3101
361
+
MX28_PAD_PWM1__I2C1_SDA 0x3111
362
+
MX28_PAD_PWM2__USB0_ID 0x3121
363
+
MX28_PAD_SAIF0_MCLK__PWM_3 0x3141
364
+
MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151
365
+
MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161
366
+
MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171
367
+
MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181
368
+
MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191
369
+
MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1
370
+
MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1
371
+
MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001
372
+
MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011
373
+
MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021
374
+
MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031
375
+
MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041
376
+
MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051
377
+
MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061
378
+
MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071
379
+
MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081
380
+
MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091
381
+
MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1
382
+
MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1
383
+
MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1
384
+
MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1
385
+
MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1
386
+
MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1
387
+
MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122
388
+
MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132
389
+
MX28_PAD_GPMI_RDY0__USB0_ID 0x0142
390
+
MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162
391
+
MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172
392
+
MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2
393
+
MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2
394
+
MX28_PAD_LCD_D00__ETM_DA0 0x1002
395
+
MX28_PAD_LCD_D01__ETM_DA1 0x1012
396
+
MX28_PAD_LCD_D02__ETM_DA2 0x1022
397
+
MX28_PAD_LCD_D03__ETM_DA3 0x1032
398
+
MX28_PAD_LCD_D04__ETM_DA4 0x1042
399
+
MX28_PAD_LCD_D05__ETM_DA5 0x1052
400
+
MX28_PAD_LCD_D06__ETM_DA6 0x1062
401
+
MX28_PAD_LCD_D07__ETM_DA7 0x1072
402
+
MX28_PAD_LCD_D08__ETM_DA8 0x1082
403
+
MX28_PAD_LCD_D09__ETM_DA9 0x1092
404
+
MX28_PAD_LCD_D10__ETM_DA10 0x10a2
405
+
MX28_PAD_LCD_D11__ETM_DA11 0x10b2
406
+
MX28_PAD_LCD_D12__ETM_DA12 0x10c2
407
+
MX28_PAD_LCD_D13__ETM_DA13 0x10d2
408
+
MX28_PAD_LCD_D14__ETM_DA14 0x10e2
409
+
MX28_PAD_LCD_D15__ETM_DA15 0x10f2
410
+
MX28_PAD_LCD_D16__ETM_DA7 0x1102
411
+
MX28_PAD_LCD_D17__ETM_DA6 0x1112
412
+
MX28_PAD_LCD_D18__ETM_DA5 0x1122
413
+
MX28_PAD_LCD_D19__ETM_DA4 0x1132
414
+
MX28_PAD_LCD_D20__ETM_DA3 0x1142
415
+
MX28_PAD_LCD_D21__ETM_DA2 0x1152
416
+
MX28_PAD_LCD_D22__ETM_DA1 0x1162
417
+
MX28_PAD_LCD_D23__ETM_DA0 0x1172
418
+
MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182
419
+
MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192
420
+
MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2
421
+
MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2
422
+
MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2
423
+
MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2
424
+
MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2
425
+
MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2
426
+
MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102
427
+
MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112
428
+
MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122
429
+
MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132
430
+
MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142
431
+
MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152
432
+
MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182
433
+
MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192
434
+
MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2
435
+
MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2
436
+
MX28_PAD_AUART0_RX__DUART_CTS 0x3002
437
+
MX28_PAD_AUART0_TX__DUART_RTS 0x3012
438
+
MX28_PAD_AUART0_CTS__DUART_RX 0x3022
439
+
MX28_PAD_AUART0_RTS__DUART_TX 0x3032
440
+
MX28_PAD_AUART1_RX__PWM_0 0x3042
441
+
MX28_PAD_AUART1_TX__PWM_1 0x3052
442
+
MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062
443
+
MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072
444
+
MX28_PAD_AUART2_RX__SSP3_D4 0x3082
445
+
MX28_PAD_AUART2_TX__SSP3_D5 0x3092
446
+
MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2
447
+
MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2
448
+
MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2
449
+
MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2
450
+
MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2
451
+
MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2
452
+
MX28_PAD_PWM0__DUART_RX 0x3102
453
+
MX28_PAD_PWM1__DUART_TX 0x3112
454
+
MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122
455
+
MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142
456
+
MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152
457
+
MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162
458
+
MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172
459
+
MX28_PAD_I2C0_SCL__DUART_RX 0x3182
460
+
MX28_PAD_I2C0_SDA__DUART_TX 0x3192
461
+
MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2
462
+
MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2
463
+
MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002
464
+
MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012
465
+
MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022
466
+
MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032
467
+
MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052
468
+
MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092
469
+
MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2
470
+
MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2
471
+
MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2
472
+
MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2
473
+
MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2
474
+
MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2
475
+
MX28_PAD_GPMI_D00__GPIO_0_0 0x0003
476
+
MX28_PAD_GPMI_D01__GPIO_0_1 0x0013
477
+
MX28_PAD_GPMI_D02__GPIO_0_2 0x0023
478
+
MX28_PAD_GPMI_D03__GPIO_0_3 0x0033
479
+
MX28_PAD_GPMI_D04__GPIO_0_4 0x0043
480
+
MX28_PAD_GPMI_D05__GPIO_0_5 0x0053
481
+
MX28_PAD_GPMI_D06__GPIO_0_6 0x0063
482
+
MX28_PAD_GPMI_D07__GPIO_0_7 0x0073
483
+
MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103
484
+
MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113
485
+
MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123
486
+
MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133
487
+
MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143
488
+
MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153
489
+
MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163
490
+
MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173
491
+
MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183
492
+
MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193
493
+
MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3
494
+
MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3
495
+
MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3
496
+
MX28_PAD_LCD_D00__GPIO_1_0 0x1003
497
+
MX28_PAD_LCD_D01__GPIO_1_1 0x1013
498
+
MX28_PAD_LCD_D02__GPIO_1_2 0x1023
499
+
MX28_PAD_LCD_D03__GPIO_1_3 0x1033
500
+
MX28_PAD_LCD_D04__GPIO_1_4 0x1043
501
+
MX28_PAD_LCD_D05__GPIO_1_5 0x1053
502
+
MX28_PAD_LCD_D06__GPIO_1_6 0x1063
503
+
MX28_PAD_LCD_D07__GPIO_1_7 0x1073
504
+
MX28_PAD_LCD_D08__GPIO_1_8 0x1083
505
+
MX28_PAD_LCD_D09__GPIO_1_9 0x1093
506
+
MX28_PAD_LCD_D10__GPIO_1_10 0x10a3
507
+
MX28_PAD_LCD_D11__GPIO_1_11 0x10b3
508
+
MX28_PAD_LCD_D12__GPIO_1_12 0x10c3
509
+
MX28_PAD_LCD_D13__GPIO_1_13 0x10d3
510
+
MX28_PAD_LCD_D14__GPIO_1_14 0x10e3
511
+
MX28_PAD_LCD_D15__GPIO_1_15 0x10f3
512
+
MX28_PAD_LCD_D16__GPIO_1_16 0x1103
513
+
MX28_PAD_LCD_D17__GPIO_1_17 0x1113
514
+
MX28_PAD_LCD_D18__GPIO_1_18 0x1123
515
+
MX28_PAD_LCD_D19__GPIO_1_19 0x1133
516
+
MX28_PAD_LCD_D20__GPIO_1_20 0x1143
517
+
MX28_PAD_LCD_D21__GPIO_1_21 0x1153
518
+
MX28_PAD_LCD_D22__GPIO_1_22 0x1163
519
+
MX28_PAD_LCD_D23__GPIO_1_23 0x1173
520
+
MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183
521
+
MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193
522
+
MX28_PAD_LCD_RS__GPIO_1_26 0x11a3
523
+
MX28_PAD_LCD_CS__GPIO_1_27 0x11b3
524
+
MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3
525
+
MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3
526
+
MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3
527
+
MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3
528
+
MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003
529
+
MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013
530
+
MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023
531
+
MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033
532
+
MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043
533
+
MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053
534
+
MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063
535
+
MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073
536
+
MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083
537
+
MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093
538
+
MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3
539
+
MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3
540
+
MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3
541
+
MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3
542
+
MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3
543
+
MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103
544
+
MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113
545
+
MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123
546
+
MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133
547
+
MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143
548
+
MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153
549
+
MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183
550
+
MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193
551
+
MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3
552
+
MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3
553
+
MX28_PAD_AUART0_RX__GPIO_3_0 0x3003
554
+
MX28_PAD_AUART0_TX__GPIO_3_1 0x3013
555
+
MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023
556
+
MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033
557
+
MX28_PAD_AUART1_RX__GPIO_3_4 0x3043
558
+
MX28_PAD_AUART1_TX__GPIO_3_5 0x3053
559
+
MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063
560
+
MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073
561
+
MX28_PAD_AUART2_RX__GPIO_3_8 0x3083
562
+
MX28_PAD_AUART2_TX__GPIO_3_9 0x3093
563
+
MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3
564
+
MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3
565
+
MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3
566
+
MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3
567
+
MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3
568
+
MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3
569
+
MX28_PAD_PWM0__GPIO_3_16 0x3103
570
+
MX28_PAD_PWM1__GPIO_3_17 0x3113
571
+
MX28_PAD_PWM2__GPIO_3_18 0x3123
572
+
MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143
573
+
MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153
574
+
MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163
575
+
MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173
576
+
MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183
577
+
MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193
578
+
MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3
579
+
MX28_PAD_SPDIF__GPIO_3_27 0x31b3
580
+
MX28_PAD_PWM3__GPIO_3_28 0x31c3
581
+
MX28_PAD_PWM4__GPIO_3_29 0x31d3
582
+
MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3
583
+
MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003
584
+
MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013
585
+
MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023
586
+
MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033
587
+
MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043
588
+
MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053
589
+
MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063
590
+
MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073
591
+
MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083
592
+
MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093
593
+
MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3
594
+
MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3
595
+
MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3
596
+
MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3
597
+
MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3
598
+
MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3
599
+
MX28_PAD_ENET_CLK__GPIO_4_16 0x4103
600
+
MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143
601
+
602
+
Valid values for i.MX23 pinmux-id:
603
+
604
+
pinmux id
605
+
------ --
606
+
MX23_PAD_GPMI_D00__GPMI_D00 0x0000
607
+
MX23_PAD_GPMI_D01__GPMI_D01 0x0010
608
+
MX23_PAD_GPMI_D02__GPMI_D02 0x0020
609
+
MX23_PAD_GPMI_D03__GPMI_D03 0x0030
610
+
MX23_PAD_GPMI_D04__GPMI_D04 0x0040
611
+
MX23_PAD_GPMI_D05__GPMI_D05 0x0050
612
+
MX23_PAD_GPMI_D06__GPMI_D06 0x0060
613
+
MX23_PAD_GPMI_D07__GPMI_D07 0x0070
614
+
MX23_PAD_GPMI_D08__GPMI_D08 0x0080
615
+
MX23_PAD_GPMI_D09__GPMI_D09 0x0090
616
+
MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
617
+
MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
618
+
MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
619
+
MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
620
+
MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
621
+
MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
622
+
MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
623
+
MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
624
+
MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
625
+
MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
626
+
MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
627
+
MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
628
+
MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
629
+
MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
630
+
MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
631
+
MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
632
+
MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
633
+
MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
634
+
MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
635
+
MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
636
+
MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
637
+
MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
638
+
MX23_PAD_LCD_D00__LCD_D00 0x1000
639
+
MX23_PAD_LCD_D01__LCD_D01 0x1010
640
+
MX23_PAD_LCD_D02__LCD_D02 0x1020
641
+
MX23_PAD_LCD_D03__LCD_D03 0x1030
642
+
MX23_PAD_LCD_D04__LCD_D04 0x1040
643
+
MX23_PAD_LCD_D05__LCD_D05 0x1050
644
+
MX23_PAD_LCD_D06__LCD_D06 0x1060
645
+
MX23_PAD_LCD_D07__LCD_D07 0x1070
646
+
MX23_PAD_LCD_D08__LCD_D08 0x1080
647
+
MX23_PAD_LCD_D09__LCD_D09 0x1090
648
+
MX23_PAD_LCD_D10__LCD_D10 0x10a0
649
+
MX23_PAD_LCD_D11__LCD_D11 0x10b0
650
+
MX23_PAD_LCD_D12__LCD_D12 0x10c0
651
+
MX23_PAD_LCD_D13__LCD_D13 0x10d0
652
+
MX23_PAD_LCD_D14__LCD_D14 0x10e0
653
+
MX23_PAD_LCD_D15__LCD_D15 0x10f0
654
+
MX23_PAD_LCD_D16__LCD_D16 0x1100
655
+
MX23_PAD_LCD_D17__LCD_D17 0x1110
656
+
MX23_PAD_LCD_RESET__LCD_RESET 0x1120
657
+
MX23_PAD_LCD_RS__LCD_RS 0x1130
658
+
MX23_PAD_LCD_WR__LCD_WR 0x1140
659
+
MX23_PAD_LCD_CS__LCD_CS 0x1150
660
+
MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
661
+
MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
662
+
MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
663
+
MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
664
+
MX23_PAD_PWM0__PWM0 0x11a0
665
+
MX23_PAD_PWM1__PWM1 0x11b0
666
+
MX23_PAD_PWM2__PWM2 0x11c0
667
+
MX23_PAD_PWM3__PWM3 0x11d0
668
+
MX23_PAD_PWM4__PWM4 0x11e0
669
+
MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
670
+
MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
671
+
MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
672
+
MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
673
+
MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
674
+
MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
675
+
MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
676
+
MX23_PAD_ROTARYA__ROTARYA 0x2070
677
+
MX23_PAD_ROTARYB__ROTARYB 0x2080
678
+
MX23_PAD_EMI_A00__EMI_A00 0x2090
679
+
MX23_PAD_EMI_A01__EMI_A01 0x20a0
680
+
MX23_PAD_EMI_A02__EMI_A02 0x20b0
681
+
MX23_PAD_EMI_A03__EMI_A03 0x20c0
682
+
MX23_PAD_EMI_A04__EMI_A04 0x20d0
683
+
MX23_PAD_EMI_A05__EMI_A05 0x20e0
684
+
MX23_PAD_EMI_A06__EMI_A06 0x20f0
685
+
MX23_PAD_EMI_A07__EMI_A07 0x2100
686
+
MX23_PAD_EMI_A08__EMI_A08 0x2110
687
+
MX23_PAD_EMI_A09__EMI_A09 0x2120
688
+
MX23_PAD_EMI_A10__EMI_A10 0x2130
689
+
MX23_PAD_EMI_A11__EMI_A11 0x2140
690
+
MX23_PAD_EMI_A12__EMI_A12 0x2150
691
+
MX23_PAD_EMI_BA0__EMI_BA0 0x2160
692
+
MX23_PAD_EMI_BA1__EMI_BA1 0x2170
693
+
MX23_PAD_EMI_CASN__EMI_CASN 0x2180
694
+
MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
695
+
MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
696
+
MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
697
+
MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
698
+
MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
699
+
MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
700
+
MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
701
+
MX23_PAD_EMI_D00__EMI_D00 0x3000
702
+
MX23_PAD_EMI_D01__EMI_D01 0x3010
703
+
MX23_PAD_EMI_D02__EMI_D02 0x3020
704
+
MX23_PAD_EMI_D03__EMI_D03 0x3030
705
+
MX23_PAD_EMI_D04__EMI_D04 0x3040
706
+
MX23_PAD_EMI_D05__EMI_D05 0x3050
707
+
MX23_PAD_EMI_D06__EMI_D06 0x3060
708
+
MX23_PAD_EMI_D07__EMI_D07 0x3070
709
+
MX23_PAD_EMI_D08__EMI_D08 0x3080
710
+
MX23_PAD_EMI_D09__EMI_D09 0x3090
711
+
MX23_PAD_EMI_D10__EMI_D10 0x30a0
712
+
MX23_PAD_EMI_D11__EMI_D11 0x30b0
713
+
MX23_PAD_EMI_D12__EMI_D12 0x30c0
714
+
MX23_PAD_EMI_D13__EMI_D13 0x30d0
715
+
MX23_PAD_EMI_D14__EMI_D14 0x30e0
716
+
MX23_PAD_EMI_D15__EMI_D15 0x30f0
717
+
MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
718
+
MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
719
+
MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
720
+
MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
721
+
MX23_PAD_EMI_CLK__EMI_CLK 0x3140
722
+
MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
723
+
MX23_PAD_GPMI_D00__LCD_D8 0x0001
724
+
MX23_PAD_GPMI_D01__LCD_D9 0x0011
725
+
MX23_PAD_GPMI_D02__LCD_D10 0x0021
726
+
MX23_PAD_GPMI_D03__LCD_D11 0x0031
727
+
MX23_PAD_GPMI_D04__LCD_D12 0x0041
728
+
MX23_PAD_GPMI_D05__LCD_D13 0x0051
729
+
MX23_PAD_GPMI_D06__LCD_D14 0x0061
730
+
MX23_PAD_GPMI_D07__LCD_D15 0x0071
731
+
MX23_PAD_GPMI_D08__LCD_D18 0x0081
732
+
MX23_PAD_GPMI_D09__LCD_D19 0x0091
733
+
MX23_PAD_GPMI_D10__LCD_D20 0x00a1
734
+
MX23_PAD_GPMI_D11__LCD_D21 0x00b1
735
+
MX23_PAD_GPMI_D12__LCD_D22 0x00c1
736
+
MX23_PAD_GPMI_D13__LCD_D23 0x00d1
737
+
MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
738
+
MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
739
+
MX23_PAD_GPMI_CLE__LCD_D16 0x0101
740
+
MX23_PAD_GPMI_ALE__LCD_D17 0x0111
741
+
MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
742
+
MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
743
+
MX23_PAD_AUART1_RX__IR_RX 0x01c1
744
+
MX23_PAD_AUART1_TX__IR_TX 0x01d1
745
+
MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
746
+
MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
747
+
MX23_PAD_LCD_D00__ETM_DA8 0x1001
748
+
MX23_PAD_LCD_D01__ETM_DA9 0x1011
749
+
MX23_PAD_LCD_D02__ETM_DA10 0x1021
750
+
MX23_PAD_LCD_D03__ETM_DA11 0x1031
751
+
MX23_PAD_LCD_D04__ETM_DA12 0x1041
752
+
MX23_PAD_LCD_D05__ETM_DA13 0x1051
753
+
MX23_PAD_LCD_D06__ETM_DA14 0x1061
754
+
MX23_PAD_LCD_D07__ETM_DA15 0x1071
755
+
MX23_PAD_LCD_D08__ETM_DA0 0x1081
756
+
MX23_PAD_LCD_D09__ETM_DA1 0x1091
757
+
MX23_PAD_LCD_D10__ETM_DA2 0x10a1
758
+
MX23_PAD_LCD_D11__ETM_DA3 0x10b1
759
+
MX23_PAD_LCD_D12__ETM_DA4 0x10c1
760
+
MX23_PAD_LCD_D13__ETM_DA5 0x10d1
761
+
MX23_PAD_LCD_D14__ETM_DA6 0x10e1
762
+
MX23_PAD_LCD_D15__ETM_DA7 0x10f1
763
+
MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
764
+
MX23_PAD_LCD_RS__ETM_TCLK 0x1131
765
+
MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
766
+
MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
767
+
MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
768
+
MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
769
+
MX23_PAD_PWM0__ROTARYA 0x11a1
770
+
MX23_PAD_PWM1__ROTARYB 0x11b1
771
+
MX23_PAD_PWM2__GPMI_RDY3 0x11c1
772
+
MX23_PAD_PWM3__ETM_TCTL 0x11d1
773
+
MX23_PAD_PWM4__ETM_TCLK 0x11e1
774
+
MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
775
+
MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
776
+
MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
777
+
MX23_PAD_ROTARYA__AUART2_RTS 0x2071
778
+
MX23_PAD_ROTARYB__AUART2_CTS 0x2081
779
+
MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
780
+
MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
781
+
MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
782
+
MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
783
+
MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
784
+
MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
785
+
MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
786
+
MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
787
+
MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
788
+
MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
789
+
MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
790
+
MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
791
+
MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
792
+
MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
793
+
MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
794
+
MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
795
+
MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
796
+
MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
797
+
MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
798
+
MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
799
+
MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
800
+
MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
801
+
MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
802
+
MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
803
+
MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
804
+
MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
805
+
MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
806
+
MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
807
+
MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
808
+
MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
809
+
MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
810
+
MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
811
+
MX23_PAD_PWM0__DUART_RX 0x11a2
812
+
MX23_PAD_PWM1__DUART_TX 0x11b2
813
+
MX23_PAD_PWM3__AUART1_CTS 0x11d2
814
+
MX23_PAD_PWM4__AUART1_RTS 0x11e2
815
+
MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
816
+
MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
817
+
MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
818
+
MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
819
+
MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
820
+
MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
821
+
MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
822
+
MX23_PAD_ROTARYA__SPDIF 0x2072
823
+
MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
824
+
MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
825
+
MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
826
+
MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
827
+
MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
828
+
MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
829
+
MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
830
+
MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
831
+
MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
832
+
MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
833
+
MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
834
+
MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
835
+
MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
836
+
MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
837
+
MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
838
+
MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
839
+
MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
840
+
MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
841
+
MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
842
+
MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
843
+
MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
844
+
MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
845
+
MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
846
+
MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
847
+
MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
848
+
MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
849
+
MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
850
+
MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
851
+
MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
852
+
MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
853
+
MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
854
+
MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
855
+
MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
856
+
MX23_PAD_LCD_D00__GPIO_1_0 0x1003
857
+
MX23_PAD_LCD_D01__GPIO_1_1 0x1013
858
+
MX23_PAD_LCD_D02__GPIO_1_2 0x1023
859
+
MX23_PAD_LCD_D03__GPIO_1_3 0x1033
860
+
MX23_PAD_LCD_D04__GPIO_1_4 0x1043
861
+
MX23_PAD_LCD_D05__GPIO_1_5 0x1053
862
+
MX23_PAD_LCD_D06__GPIO_1_6 0x1063
863
+
MX23_PAD_LCD_D07__GPIO_1_7 0x1073
864
+
MX23_PAD_LCD_D08__GPIO_1_8 0x1083
865
+
MX23_PAD_LCD_D09__GPIO_1_9 0x1093
866
+
MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
867
+
MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
868
+
MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
869
+
MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
870
+
MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
871
+
MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
872
+
MX23_PAD_LCD_D16__GPIO_1_16 0x1103
873
+
MX23_PAD_LCD_D17__GPIO_1_17 0x1113
874
+
MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
875
+
MX23_PAD_LCD_RS__GPIO_1_19 0x1133
876
+
MX23_PAD_LCD_WR__GPIO_1_20 0x1143
877
+
MX23_PAD_LCD_CS__GPIO_1_21 0x1153
878
+
MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
879
+
MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
880
+
MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
881
+
MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
882
+
MX23_PAD_PWM0__GPIO_1_26 0x11a3
883
+
MX23_PAD_PWM1__GPIO_1_27 0x11b3
884
+
MX23_PAD_PWM2__GPIO_1_28 0x11c3
885
+
MX23_PAD_PWM3__GPIO_1_29 0x11d3
886
+
MX23_PAD_PWM4__GPIO_1_30 0x11e3
887
+
MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
888
+
MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
889
+
MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
890
+
MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
891
+
MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
892
+
MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
893
+
MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
894
+
MX23_PAD_ROTARYA__GPIO_2_7 0x2073
895
+
MX23_PAD_ROTARYB__GPIO_2_8 0x2083
896
+
MX23_PAD_EMI_A00__GPIO_2_9 0x2093
897
+
MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
898
+
MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
899
+
MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
900
+
MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
901
+
MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
902
+
MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
903
+
MX23_PAD_EMI_A07__GPIO_2_16 0x2103
904
+
MX23_PAD_EMI_A08__GPIO_2_17 0x2113
905
+
MX23_PAD_EMI_A09__GPIO_2_18 0x2123
906
+
MX23_PAD_EMI_A10__GPIO_2_19 0x2133
907
+
MX23_PAD_EMI_A11__GPIO_2_20 0x2143
908
+
MX23_PAD_EMI_A12__GPIO_2_21 0x2153
909
+
MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
910
+
MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
911
+
MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
912
+
MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
913
+
MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
914
+
MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
915
+
MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
916
+
MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
917
+
MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
918
+
MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
+132
Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
+132
Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
···
1
+
NVIDIA Tegra20 pinmux controller
2
+
3
+
Required properties:
4
+
- compatible: "nvidia,tegra20-pinmux"
5
+
- reg: Should contain the register physical address and length for each of
6
+
the tri-state, mux, pull-up/down, and pad control register sets.
7
+
8
+
Please refer to pinctrl-bindings.txt in this directory for details of the
9
+
common pinctrl bindings used by client devices, including the meaning of the
10
+
phrase "pin configuration node".
11
+
12
+
Tegra's pin configuration nodes act as a container for an abitrary number of
13
+
subnodes. Each of these subnodes represents some desired configuration for a
14
+
pin, a group, or a list of pins or groups. This configuration can include the
15
+
mux function to select on those pin(s)/group(s), and various pin configuration
16
+
parameters, such as pull-up, tristate, drive strength, etc.
17
+
18
+
The name of each subnode is not important; all subnodes should be enumerated
19
+
and processed purely based on their content.
20
+
21
+
Each subnode only affects those parameters that are explicitly listed. In
22
+
other words, a subnode that lists a mux function but no pin configuration
23
+
parameters implies no information about any pin configuration parameters.
24
+
Similarly, a pin subnode that describes a pullup parameter implies no
25
+
information about e.g. the mux function or tristate parameter. For this
26
+
reason, even seemingly boolean values are actually tristates in this binding:
27
+
unspecified, off, or on. Unspecified is represented as an absent property,
28
+
and off/on are represented as integer values 0 and 1.
29
+
30
+
Required subnode-properties:
31
+
- nvidia,pins : An array of strings. Each string contains the name of a pin or
32
+
group. Valid values for these names are listed below.
33
+
34
+
Optional subnode-properties:
35
+
- nvidia,function: A string containing the name of the function to mux to the
36
+
pin or group. Valid values for function names are listed below. See the Tegra
37
+
TRM to determine which are valid for each pin or group.
38
+
- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
39
+
0: none, 1: down, 2: up.
40
+
- nvidia,tristate: Integer.
41
+
0: drive, 1: tristate.
42
+
- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
43
+
0: no, 1: yes.
44
+
- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
45
+
0: no, 1: yes.
46
+
- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
47
+
most power. Controls the drive power or current. See "Low Power Mode"
48
+
or "LPMD1" and "LPMD0" in the Tegra TRM.
49
+
- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
50
+
The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
51
+
Tegra TRM.
52
+
- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
53
+
The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
54
+
Tegra TRM.
55
+
- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
56
+
fastest. The range of valid values depends on the pingroup. See
57
+
"DRVDN_SLWR" in the Tegra TRM.
58
+
- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
59
+
fastest. The range of valid values depends on the pingroup. See
60
+
"DRVUP_SLWF" in the Tegra TRM.
61
+
62
+
Note that many of these properties are only valid for certain specific pins
63
+
or groups. See the Tegra TRM and various pinmux spreadsheets for complete
64
+
details regarding which groups support which functionality. The Linux pinctrl
65
+
driver may also be a useful reference, since it consolidates, disambiguates,
66
+
and corrects data from all those sources.
67
+
68
+
Valid values for pin and group names are:
69
+
70
+
mux groups:
71
+
72
+
These all support nvidia,function, nvidia,tristate, and many support
73
+
nvidia,pull.
74
+
75
+
ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
76
+
ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
77
+
gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
78
+
ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
79
+
ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
80
+
lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
81
+
owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
82
+
spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
83
+
uca, ucb, uda.
84
+
85
+
tristate groups:
86
+
87
+
These only support nvidia,pull.
88
+
89
+
ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
90
+
ld19_18, ld21_20, ld23_22.
91
+
92
+
drive groups:
93
+
94
+
With some exceptions, these support nvidia,high-speed-mode,
95
+
nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
96
+
nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
97
+
98
+
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
99
+
drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
100
+
drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
101
+
drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
102
+
drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
103
+
drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
104
+
drive_uda.
105
+
106
+
Example:
107
+
108
+
pinctrl@70000000 {
109
+
compatible = "nvidia,tegra20-pinmux";
110
+
reg = < 0x70000014 0x10 /* Tri-state registers */
111
+
0x70000080 0x20 /* Mux registers */
112
+
0x700000a0 0x14 /* Pull-up/down registers */
113
+
0x70000868 0xa8 >; /* Pad control registers */
114
+
};
115
+
116
+
Example board file extract:
117
+
118
+
pinctrl@70000000 {
119
+
sdio4_default: sdio4_default {
120
+
atb {
121
+
nvidia,pins = "atb", "gma", "gme";
122
+
nvidia,function = "sdio4";
123
+
nvidia,pull = <0>;
124
+
nvidia,tristate = <0>;
125
+
};
126
+
};
127
+
};
128
+
129
+
sdhci@c8000600 {
130
+
pinctrl-names = "default";
131
+
pinctrl-0 = <&sdio4_default>;
132
+
};
+132
Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
+132
Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
···
1
+
NVIDIA Tegra30 pinmux controller
2
+
3
+
The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
4
+
as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
5
+
that binding as a baseline, and only documents the differences between the
6
+
two bindings.
7
+
8
+
Required properties:
9
+
- compatible: "nvidia,tegra30-pinmux"
10
+
- reg: Should contain the register physical address and length for each of
11
+
the pad control and mux registers.
12
+
13
+
Tegra30 adds the following optional properties for pin configuration subnodes:
14
+
- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
15
+
- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
16
+
- nvidia,lock: Integer. Lock the pin configuration against further changes
17
+
until reset. 0: no, 1: yes.
18
+
- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
19
+
20
+
As with Tegra20, see the Tegra TRM for complete details regarding which groups
21
+
support which functionality.
22
+
23
+
Valid values for pin and group names are:
24
+
25
+
per-pin mux groups:
26
+
27
+
These all support nvidia,function, nvidia,tristate, nvidia,pull,
28
+
nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
29
+
nvidia,io-reset.
30
+
31
+
clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
32
+
dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
33
+
gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
34
+
sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
35
+
uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
36
+
lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
37
+
sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
38
+
lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
39
+
lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
40
+
lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
41
+
gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
42
+
gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
43
+
gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
44
+
gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
45
+
gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
46
+
gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
47
+
uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
48
+
gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
49
+
vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
50
+
vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
51
+
lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
52
+
dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
53
+
lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
54
+
ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
55
+
ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
56
+
dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
57
+
kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
58
+
kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
59
+
kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
60
+
kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
61
+
kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
62
+
vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
63
+
sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
64
+
pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
65
+
lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
66
+
clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
67
+
spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
68
+
spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
69
+
sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
70
+
sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
71
+
sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
72
+
sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
73
+
sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
74
+
cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
75
+
cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
76
+
clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
77
+
pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
78
+
pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
79
+
pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
80
+
clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
81
+
pwr_int_n.
82
+
83
+
drive groups:
84
+
85
+
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
86
+
nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
87
+
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
88
+
89
+
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
90
+
dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
91
+
gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
92
+
uart3, uda, vi1.
93
+
94
+
Example:
95
+
96
+
pinctrl@70000000 {
97
+
compatible = "nvidia,tegra30-pinmux";
98
+
reg = < 0x70000868 0xd0 /* Pad control registers */
99
+
0x70003000 0x3e0 >; /* Mux registers */
100
+
};
101
+
102
+
Example board file extract:
103
+
104
+
pinctrl@70000000 {
105
+
sdmmc4_default: pinmux {
106
+
sdmmc4_clk_pcc4 {
107
+
nvidia,pins = "sdmmc4_clk_pcc4",
108
+
"sdmmc4_rst_n_pcc3";
109
+
nvidia,function = "sdmmc4";
110
+
nvidia,pull = <0>;
111
+
nvidia,tristate = <0>;
112
+
};
113
+
sdmmc4_dat0_paa0 {
114
+
nvidia,pins = "sdmmc4_dat0_paa0",
115
+
"sdmmc4_dat1_paa1",
116
+
"sdmmc4_dat2_paa2",
117
+
"sdmmc4_dat3_paa3",
118
+
"sdmmc4_dat4_paa4",
119
+
"sdmmc4_dat5_paa5",
120
+
"sdmmc4_dat6_paa6",
121
+
"sdmmc4_dat7_paa7";
122
+
nvidia,function = "sdmmc4";
123
+
nvidia,pull = <2>;
124
+
nvidia,tristate = <0>;
125
+
};
126
+
};
127
+
};
128
+
129
+
sdhci@78000400 {
130
+
pinctrl-names = "default";
131
+
pinctrl-0 = <&sdmmc4_default>;
132
+
};
+128
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+128
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
···
1
+
== Introduction ==
2
+
3
+
Hardware modules that control pin multiplexing or configuration parameters
4
+
such as pull-up/down, tri-state, drive-strength etc are designated as pin
5
+
controllers. Each pin controller must be represented as a node in device tree,
6
+
just like any other hardware module.
7
+
8
+
Hardware modules whose signals are affected by pin configuration are
9
+
designated client devices. Again, each client device must be represented as a
10
+
node in device tree, just like any other hardware module.
11
+
12
+
For a client device to operate correctly, certain pin controllers must
13
+
set up certain specific pin configurations. Some client devices need a
14
+
single static pin configuration, e.g. set up during initialization. Others
15
+
need to reconfigure pins at run-time, for example to tri-state pins when the
16
+
device is inactive. Hence, each client device can define a set of named
17
+
states. The number and names of those states is defined by the client device's
18
+
own binding.
19
+
20
+
The common pinctrl bindings defined in this file provide an infrastructure
21
+
for client device device tree nodes to map those state names to the pin
22
+
configuration used by those states.
23
+
24
+
Note that pin controllers themselves may also be client devices of themselves.
25
+
For example, a pin controller may set up its own "active" state when the
26
+
driver loads. This would allow representing a board's static pin configuration
27
+
in a single place, rather than splitting it across multiple client device
28
+
nodes. The decision to do this or not somewhat rests with the author of
29
+
individual board device tree files, and any requirements imposed by the
30
+
bindings for the individual client devices in use by that board, i.e. whether
31
+
they require certain specific named states for dynamic pin configuration.
32
+
33
+
== Pinctrl client devices ==
34
+
35
+
For each client device individually, every pin state is assigned an integer
36
+
ID. These numbers start at 0, and are contiguous. For each state ID, a unique
37
+
property exists to define the pin configuration. Each state may also be
38
+
assigned a name. When names are used, another property exists to map from
39
+
those names to the integer IDs.
40
+
41
+
Each client device's own binding determines the set of states the must be
42
+
defined in its device tree node, and whether to define the set of state
43
+
IDs that must be provided, or whether to define the set of state names that
44
+
must be provided.
45
+
46
+
Required properties:
47
+
pinctrl-0: List of phandles, each pointing at a pin configuration
48
+
node. These referenced pin configuration nodes must be child
49
+
nodes of the pin controller that they configure. Multiple
50
+
entries may exist in this list so that multiple pin
51
+
controllers may be configured, or so that a state may be built
52
+
from multiple nodes for a single pin controller, each
53
+
contributing part of the overall configuration. See the next
54
+
section of this document for details of the format of these
55
+
pin configuration nodes.
56
+
57
+
In some cases, it may be useful to define a state, but for it
58
+
to be empty. This may be required when a common IP block is
59
+
used in an SoC either without a pin controller, or where the
60
+
pin controller does not affect the HW module in question. If
61
+
the binding for that IP block requires certain pin states to
62
+
exist, they must still be defined, but may be left empty.
63
+
64
+
Optional properties:
65
+
pinctrl-1: List of phandles, each pointing at a pin configuration
66
+
node within a pin controller.
67
+
...
68
+
pinctrl-n: List of phandles, each pointing at a pin configuration
69
+
node within a pin controller.
70
+
pinctrl-names: The list of names to assign states. List entry 0 defines the
71
+
name for integer state ID 0, list entry 1 for state ID 1, and
72
+
so on.
73
+
74
+
For example:
75
+
76
+
/* For a client device requiring named states */
77
+
device {
78
+
pinctrl-names = "active", "idle";
79
+
pinctrl-0 = <&state_0_node_a>;
80
+
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
81
+
};
82
+
83
+
/* For the same device if using state IDs */
84
+
device {
85
+
pinctrl-0 = <&state_0_node_a>;
86
+
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
87
+
};
88
+
89
+
/*
90
+
* For an IP block whose binding supports pin configuration,
91
+
* but in use on an SoC that doesn't have any pin control hardware
92
+
*/
93
+
device {
94
+
pinctrl-names = "active", "idle";
95
+
pinctrl-0 = <>;
96
+
pinctrl-1 = <>;
97
+
};
98
+
99
+
== Pin controller devices ==
100
+
101
+
Pin controller devices should contain the pin configuration nodes that client
102
+
devices reference.
103
+
104
+
For example:
105
+
106
+
pincontroller {
107
+
... /* Standard DT properties for the device itself elided */
108
+
109
+
state_0_node_a {
110
+
...
111
+
};
112
+
state_1_node_a {
113
+
...
114
+
};
115
+
state_1_node_b {
116
+
...
117
+
};
118
+
}
119
+
120
+
The contents of each of those pin configuration child nodes is defined
121
+
entirely by the binding for the individual pin controller device. There
122
+
exists no common standard for this content.
123
+
124
+
The pin configuration nodes need not be direct children of the pin controller
125
+
device; they may be grandchildren, for example. Whether this is legal, and
126
+
whether there is any interaction between the child and intermediate parent
127
+
nodes, is again defined entirely by the binding for the individual pin
128
+
controller device.
+108
Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
+108
Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
···
1
+
ST Microelectronics, SPEAr pinmux controller
2
+
3
+
Required properties:
4
+
- compatible : "st,spear300-pinmux"
5
+
: "st,spear310-pinmux"
6
+
: "st,spear320-pinmux"
7
+
- reg : Address range of the pinctrl registers
8
+
- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
9
+
- Its values for SPEAr300:
10
+
- NAND_MODE : <0>
11
+
- NOR_MODE : <1>
12
+
- PHOTO_FRAME_MODE : <2>
13
+
- LEND_IP_PHONE_MODE : <3>
14
+
- HEND_IP_PHONE_MODE : <4>
15
+
- LEND_WIFI_PHONE_MODE : <5>
16
+
- HEND_WIFI_PHONE_MODE : <6>
17
+
- ATA_PABX_WI2S_MODE : <7>
18
+
- ATA_PABX_I2S_MODE : <8>
19
+
- CAML_LCDW_MODE : <9>
20
+
- CAMU_LCD_MODE : <10>
21
+
- CAMU_WLCD_MODE : <11>
22
+
- CAML_LCD_MODE : <12>
23
+
- Its values for SPEAr320:
24
+
- AUTO_NET_SMII_MODE : <0>
25
+
- AUTO_NET_MII_MODE : <1>
26
+
- AUTO_EXP_MODE : <2>
27
+
- SMALL_PRINTERS_MODE : <3>
28
+
- EXTENDED_MODE : <4>
29
+
30
+
Please refer to pinctrl-bindings.txt in this directory for details of the common
31
+
pinctrl bindings used by client devices.
32
+
33
+
SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
34
+
of these subnodes represents muxing for a pin, a group, or a list of pins or
35
+
groups.
36
+
37
+
The name of each subnode is not important; all subnodes should be enumerated
38
+
and processed purely based on their content.
39
+
40
+
Required subnode-properties:
41
+
- st,pins : An array of strings. Each string contains the name of a pin or
42
+
group.
43
+
- st,function: A string containing the name of the function to mux to the pin or
44
+
group. See the SPEAr's TRM to determine which are valid for each pin or group.
45
+
46
+
Valid values for group and function names can be found from looking at the
47
+
group and function arrays in driver files:
48
+
drivers/pinctrl/spear/pinctrl-spear3*0.c
49
+
50
+
Valid values for group names are:
51
+
For All SPEAr3xx machines:
52
+
"firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
53
+
"gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
54
+
"gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
55
+
"timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
56
+
57
+
For SPEAr300 machines:
58
+
"fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
59
+
"clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
60
+
"dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
61
+
"gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
62
+
63
+
For SPEAr310 machines:
64
+
"emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
65
+
"uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
66
+
67
+
For SPEAr320 machines:
68
+
"clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
69
+
"sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
70
+
"uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
71
+
"uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
72
+
"uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
73
+
"uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
74
+
"uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
75
+
"uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
76
+
"uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
77
+
"uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
78
+
"uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
79
+
"can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
80
+
"pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
81
+
"pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
82
+
"pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
83
+
"pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
84
+
"pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
85
+
"pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
86
+
"ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
87
+
"ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
88
+
"ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
89
+
"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
90
+
"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
91
+
92
+
Valid values for function names are:
93
+
For All SPEAr3xx machines:
94
+
"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
95
+
"uart0", "timer_0_1", "timer_2_3"
96
+
97
+
For SPEAr300 machines:
98
+
"fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
99
+
100
+
For SPEAr310 machines:
101
+
"emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
102
+
"rs485_1", "tdm"
103
+
104
+
For SPEAr320 machines:
105
+
"clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
106
+
"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
107
+
"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
108
+
"mii0_1", "i2c1", "i2c2"
-5
Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
-5
Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
+4
Documentation/driver-model/devres.txt
+4
Documentation/driver-model/devres.txt
+51
-43
Documentation/pinctrl.txt
+51
-43
Documentation/pinctrl.txt
···
152
152
};
153
153
154
154
155
-
static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
155
+
static int foo_get_groups_count(struct pinctrl_dev *pctldev)
156
156
{
157
-
if (selector >= ARRAY_SIZE(foo_groups))
158
-
return -EINVAL;
159
-
return 0;
157
+
return ARRAY_SIZE(foo_groups);
160
158
}
161
159
162
160
static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
···
173
175
}
174
176
175
177
static struct pinctrl_ops foo_pctrl_ops = {
176
-
.list_groups = foo_list_groups,
178
+
.get_groups_count = foo_get_groups_count,
177
179
.get_group_name = foo_get_group_name,
178
180
.get_group_pins = foo_get_group_pins,
179
181
};
···
184
186
.pctlops = &foo_pctrl_ops,
185
187
};
186
188
187
-
The pin control subsystem will call the .list_groups() function repeatedly
188
-
beginning on 0 until it returns non-zero to determine legal selectors, then
189
-
it will call the other functions to retrieve the name and pins of the group.
190
-
Maintaining the data structure of the groups is up to the driver, this is
191
-
just a simple example - in practice you may need more entries in your group
192
-
structure, for example specific register ranges associated with each group
193
-
and so on.
189
+
The pin control subsystem will call the .get_groups_count() function to
190
+
determine total number of legal selectors, then it will call the other functions
191
+
to retrieve the name and pins of the group. Maintaining the data structure of
192
+
the groups is up to the driver, this is just a simple example - in practice you
193
+
may need more entries in your group structure, for example specific register
194
+
ranges associated with each group and so on.
194
195
195
196
196
197
Pin configuration
···
603
606
};
604
607
605
608
606
-
static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
609
+
static int foo_get_groups_count(struct pinctrl_dev *pctldev)
607
610
{
608
-
if (selector >= ARRAY_SIZE(foo_groups))
609
-
return -EINVAL;
610
-
return 0;
611
+
return ARRAY_SIZE(foo_groups);
611
612
}
612
613
613
614
static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
···
624
629
}
625
630
626
631
static struct pinctrl_ops foo_pctrl_ops = {
627
-
.list_groups = foo_list_groups,
632
+
.get_groups_count = foo_get_groups_count,
628
633
.get_group_name = foo_get_group_name,
629
634
.get_group_pins = foo_get_group_pins,
630
635
};
···
635
640
const unsigned num_groups;
636
641
};
637
642
638
-
static const char * const spi0_groups[] = { "spi0_1_grp" };
643
+
static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
639
644
static const char * const i2c0_groups[] = { "i2c0_grp" };
640
645
static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
641
646
"mmc0_3_grp" };
···
658
663
},
659
664
};
660
665
661
-
int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
666
+
int foo_get_functions_count(struct pinctrl_dev *pctldev)
662
667
{
663
-
if (selector >= ARRAY_SIZE(foo_functions))
664
-
return -EINVAL;
665
-
return 0;
668
+
return ARRAY_SIZE(foo_functions);
666
669
}
667
670
668
671
const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
···
696
703
}
697
704
698
705
struct pinmux_ops foo_pmxops = {
699
-
.list_functions = foo_list_funcs,
706
+
.get_functions_count = foo_get_functions_count,
700
707
.get_function_name = foo_get_fname,
701
708
.get_function_groups = foo_get_groups,
702
709
.enable = foo_enable,
···
779
786
780
787
#include <linux/pinctrl/machine.h>
781
788
782
-
static const struct pinctrl_map __initdata mapping[] = {
789
+
static const struct pinctrl_map mapping[] __initconst = {
783
790
{
784
791
.dev_name = "foo-spi.0",
785
792
.name = PINCTRL_STATE_DEFAULT,
···
945
952
The result of grabbing this mapping from the device with something like
946
953
this (see next paragraph):
947
954
948
-
p = pinctrl_get(dev);
955
+
p = devm_pinctrl_get(dev);
949
956
s = pinctrl_lookup_state(p, "8bit");
950
957
ret = pinctrl_select_state(p, s);
951
958
952
959
or more simply:
953
960
954
-
p = pinctrl_get_select(dev, "8bit");
961
+
p = devm_pinctrl_get_select(dev, "8bit");
955
962
956
963
Will be that you activate all the three bottom records in the mapping at
957
964
once. Since they share the same name, pin controller device, function and
···
985
992
/* Allocate a state holder named "foo" etc */
986
993
struct foo_state *foo = ...;
987
994
988
-
foo->p = pinctrl_get(&device);
995
+
foo->p = devm_pinctrl_get(&device);
989
996
if (IS_ERR(foo->p)) {
990
997
/* FIXME: clean up "foo" here */
991
998
return PTR_ERR(foo->p);
···
993
1000
994
1001
foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
995
1002
if (IS_ERR(foo->s)) {
996
-
pinctrl_put(foo->p);
997
1003
/* FIXME: clean up "foo" here */
998
1004
return PTR_ERR(s);
999
1005
}
1000
1006
1001
1007
ret = pinctrl_select_state(foo->s);
1002
1008
if (ret < 0) {
1003
-
pinctrl_put(foo->p);
1004
1009
/* FIXME: clean up "foo" here */
1005
1010
return ret;
1006
1011
}
1007
-
}
1008
-
1009
-
foo_remove()
1010
-
{
1011
-
pinctrl_put(state->p);
1012
1012
}
1013
1013
1014
1014
This get/lookup/select/put sequence can just as well be handled by bus drivers
···
1015
1029
kernel memory to hold the pinmux state. All mapping table parsing or similar
1016
1030
slow operations take place within this API.
1017
1031
1032
+
- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1033
+
to be called automatically on the retrieved pointer when the associated
1034
+
device is removed. It is recommended to use this function over plain
1035
+
pinctrl_get().
1036
+
1018
1037
- pinctrl_lookup_state() is called in process context to obtain a handle to a
1019
1038
specific state for a the client device. This operation may be slow too.
1020
1039
···
1032
1041
1033
1042
- pinctrl_put() frees all information associated with a pinctrl handle.
1034
1043
1044
+
- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1045
+
explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1046
+
However, use of this function will be rare, due to the automatic cleanup
1047
+
that will occur even without calling it.
1048
+
1049
+
pinctrl_get() must be paired with a plain pinctrl_put().
1050
+
pinctrl_get() may not be paired with devm_pinctrl_put().
1051
+
devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1052
+
devm_pinctrl_get() may not be paired with plain pinctrl_put().
1053
+
1035
1054
Usually the pin control core handled the get/put pair and call out to the
1036
1055
device drivers bookkeeping operations, like checking available functions and
1037
1056
the associated pins, whereas the enable/disable pass on to the pin controller
1038
1057
driver which takes care of activating and/or deactivating the mux setting by
1039
1058
quickly poking some registers.
1040
1059
1041
-
The pins are allocated for your device when you issue the pinctrl_get() call,
1042
-
after this you should be able to see this in the debugfs listing of all pins.
1060
+
The pins are allocated for your device when you issue the devm_pinctrl_get()
1061
+
call, after this you should be able to see this in the debugfs listing of all
1062
+
pins.
1063
+
1064
+
NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1065
+
requested pinctrl handles, for example if the pinctrl driver has not yet
1066
+
registered. Thus make sure that the error path in your driver gracefully
1067
+
cleans up and is ready to retry the probing later in the startup process.
1043
1068
1044
1069
1045
1070
System pin control hogging
···
1101
1094
1102
1095
#include <linux/pinctrl/consumer.h>
1103
1096
1104
-
foo_switch()
1105
-
{
1106
-
struct pinctrl *p;
1107
-
struct pinctrl_state *s1, *s2;
1097
+
struct pinctrl *p;
1098
+
struct pinctrl_state *s1, *s2;
1108
1099
1100
+
foo_probe()
1101
+
{
1109
1102
/* Setup */
1110
-
p = pinctrl_get(&device);
1103
+
p = devm_pinctrl_get(&device);
1111
1104
if (IS_ERR(p))
1112
1105
...
1113
1106
···
1118
1111
s2 = pinctrl_lookup_state(foo->p, "pos-B");
1119
1112
if (IS_ERR(s2))
1120
1113
...
1114
+
}
1121
1115
1116
+
foo_switch()
1117
+
{
1122
1118
/* Enable on position A */
1123
1119
ret = pinctrl_select_state(s1);
1124
1120
if (ret < 0)
···
1135
1125
...
1136
1126
1137
1127
...
1138
-
1139
-
pinctrl_put(p);
1140
1128
}
1141
1129
1142
1130
The above has to be done from process context.
+8
-15
MAINTAINERS
+8
-15
MAINTAINERS
···
5242
5242
S: Maintained
5243
5243
F: drivers/pinctrl/
5244
5244
5245
+
PIN CONTROLLER - ST SPEAR
5246
+
M: Viresh Kumar <viresh.kumar@st.com>
5247
+
L: spear-devel@list.st.com
5248
+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
5249
+
W: http://www.st.com/spear
5250
+
S: Maintained
5251
+
F: driver/pinctrl/spear/
5252
+
5245
5253
PKTCDVD DRIVER
5246
5254
M: Peter Osterlund <petero2@telia.com>
5247
5255
S: Maintained
···
6343
6335
W: http://www.st.com/spear
6344
6336
S: Maintained
6345
6337
F: drivers/clk/spear/
6346
-
6347
-
SPEAR PAD MULTIPLEXING SUPPORT
6348
-
M: Viresh Kumar <viresh.kumar@st.com>
6349
-
L: spear-devel@list.st.com
6350
-
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6351
-
W: http://www.st.com/spear
6352
-
S: Maintained
6353
-
F: arch/arm/plat-spear/include/plat/padmux.h
6354
-
F: arch/arm/plat-spear/padmux.c
6355
-
F: arch/arm/mach-spear*/spear*xx.c
6356
-
F: arch/arm/mach-spear*/include/mach/generic.h
6357
-
F: arch/arm/mach-spear3xx/spear3*0.c
6358
-
F: arch/arm/mach-spear3xx/spear3*0_evb.c
6359
-
F: arch/arm/mach-spear6xx/spear600.c
6360
-
F: arch/arm/mach-spear6xx/spear600_evb.c
6361
6338
6362
6339
SPI SUBSYSTEM
6363
6340
M: Grant Likely <grant.likely@secretlab.ca>
+1
arch/arm/Kconfig
+1
arch/arm/Kconfig
+246
arch/arm/boot/dts/spear300-evb.dts
+246
arch/arm/boot/dts/spear300-evb.dts
···
1
+
/*
2
+
* DTS file for SPEAr300 Evaluation Baord
3
+
*
4
+
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5
+
*
6
+
* The code contained herein is licensed under the GNU General Public
7
+
* License. You may obtain a copy of the GNU General Public License
8
+
* Version 2 or later at the following locations:
9
+
*
10
+
* http://www.opensource.org/licenses/gpl-license.html
11
+
* http://www.gnu.org/copyleft/gpl.html
12
+
*/
13
+
14
+
/dts-v1/;
15
+
/include/ "spear300.dtsi"
16
+
17
+
/ {
18
+
model = "ST SPEAr300 Evaluation Board";
19
+
compatible = "st,spear300-evb", "st,spear300";
20
+
#address-cells = <1>;
21
+
#size-cells = <1>;
22
+
23
+
memory {
24
+
reg = <0 0x40000000>;
25
+
};
26
+
27
+
ahb {
28
+
pinmux@99000000 {
29
+
st,pinmux-mode = <2>;
30
+
pinctrl-names = "default";
31
+
pinctrl-0 = <&state_default>;
32
+
33
+
state_default: pinmux {
34
+
i2c0 {
35
+
st,pins = "i2c0_grp";
36
+
st,function = "i2c0";
37
+
};
38
+
ssp0 {
39
+
st,pins = "ssp0_grp";
40
+
st,function = "ssp0";
41
+
};
42
+
mii0 {
43
+
st,pins = "mii0_grp";
44
+
st,function = "mii0";
45
+
};
46
+
uart0 {
47
+
st,pins = "uart0_grp";
48
+
st,function = "uart0";
49
+
};
50
+
clcd {
51
+
st,pins = "clcd_pfmode_grp";
52
+
st,function = "clcd";
53
+
};
54
+
sdhci {
55
+
st,pins = "sdhci_4bit_grp";
56
+
st,function = "sdhci";
57
+
};
58
+
gpio1 {
59
+
st,pins = "gpio1_4_to_7_grp",
60
+
"gpio1_0_to_3_grp";
61
+
st,function = "gpio1";
62
+
};
63
+
};
64
+
};
65
+
66
+
clcd@60000000 {
67
+
status = "okay";
68
+
};
69
+
70
+
dma@fc400000 {
71
+
status = "okay";
72
+
};
73
+
74
+
fsmc: flash@94000000 {
75
+
status = "okay";
76
+
};
77
+
78
+
gmac: eth@e0800000 {
79
+
status = "okay";
80
+
};
81
+
82
+
sdhci@70000000 {
83
+
int-gpio = <&gpio1 0 0>;
84
+
power-gpio = <&gpio1 2 1>;
85
+
status = "okay";
86
+
};
87
+
88
+
smi: flash@fc000000 {
89
+
status = "okay";
90
+
clock-rate=<50000000>;
91
+
92
+
flash@f8000000 {
93
+
#address-cells = <1>;
94
+
#size-cells = <1>;
95
+
reg = <0xf8000000 0x800000>;
96
+
st,smi-fast-mode;
97
+
98
+
partition@0 {
99
+
label = "xloader";
100
+
reg = <0x0 0x10000>;
101
+
};
102
+
partition@10000 {
103
+
label = "u-boot";
104
+
reg = <0x10000 0x40000>;
105
+
};
106
+
partition@50000 {
107
+
label = "linux";
108
+
reg = <0x50000 0x2c0000>;
109
+
};
110
+
partition@310000 {
111
+
label = "rootfs";
112
+
reg = <0x310000 0x4f0000>;
113
+
};
114
+
};
115
+
};
116
+
117
+
spi0: spi@d0100000 {
118
+
status = "okay";
119
+
};
120
+
121
+
ehci@e1800000 {
122
+
status = "okay";
123
+
};
124
+
125
+
ohci@e1900000 {
126
+
status = "okay";
127
+
};
128
+
129
+
ohci@e2100000 {
130
+
status = "okay";
131
+
};
132
+
133
+
apb {
134
+
gpio0: gpio@fc980000 {
135
+
status = "okay";
136
+
};
137
+
138
+
gpio1: gpio@a9000000 {
139
+
status = "okay";
140
+
};
141
+
142
+
i2c0: i2c@d0180000 {
143
+
status = "okay";
144
+
};
145
+
146
+
kbd@a0000000 {
147
+
linux,keymap = < 0x00000001
148
+
0x00010002
149
+
0x00020003
150
+
0x00030004
151
+
0x00040005
152
+
0x00050006
153
+
0x00060007
154
+
0x00070008
155
+
0x00080009
156
+
0x0100000a
157
+
0x0101000c
158
+
0x0102000d
159
+
0x0103000e
160
+
0x0104000f
161
+
0x01050010
162
+
0x01060011
163
+
0x01070012
164
+
0x01080013
165
+
0x02000014
166
+
0x02010015
167
+
0x02020016
168
+
0x02030017
169
+
0x02040018
170
+
0x02050019
171
+
0x0206001a
172
+
0x0207001b
173
+
0x0208001c
174
+
0x0300001d
175
+
0x0301001e
176
+
0x0302001f
177
+
0x03030020
178
+
0x03040021
179
+
0x03050022
180
+
0x03060023
181
+
0x03070024
182
+
0x03080025
183
+
0x04000026
184
+
0x04010027
185
+
0x04020028
186
+
0x04030029
187
+
0x0404002a
188
+
0x0405002b
189
+
0x0406002c
190
+
0x0407002d
191
+
0x0408002e
192
+
0x0500002f
193
+
0x05010030
194
+
0x05020031
195
+
0x05030032
196
+
0x05040033
197
+
0x05050034
198
+
0x05060035
199
+
0x05070036
200
+
0x05080037
201
+
0x06000038
202
+
0x06010039
203
+
0x0602003a
204
+
0x0603003b
205
+
0x0604003c
206
+
0x0605003d
207
+
0x0606003e
208
+
0x0607003f
209
+
0x06080040
210
+
0x07000041
211
+
0x07010042
212
+
0x07020043
213
+
0x07030044
214
+
0x07040045
215
+
0x07050046
216
+
0x07060047
217
+
0x07070048
218
+
0x07080049
219
+
0x0800004a
220
+
0x0801004b
221
+
0x0802004c
222
+
0x0803004d
223
+
0x0804004e
224
+
0x0805004f
225
+
0x08060050
226
+
0x08070051
227
+
0x08080052 >;
228
+
autorepeat;
229
+
st,mode = <0>;
230
+
status = "okay";
231
+
};
232
+
233
+
rtc@fc900000 {
234
+
status = "okay";
235
+
};
236
+
237
+
serial@d0000000 {
238
+
status = "okay";
239
+
};
240
+
241
+
wdt@fc880000 {
242
+
status = "okay";
243
+
};
244
+
};
245
+
};
246
+
};
+77
arch/arm/boot/dts/spear300.dtsi
+77
arch/arm/boot/dts/spear300.dtsi
···
1
+
/*
2
+
* DTS file for SPEAr300 SoC
3
+
*
4
+
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5
+
*
6
+
* The code contained herein is licensed under the GNU General Public
7
+
* License. You may obtain a copy of the GNU General Public License
8
+
* Version 2 or later at the following locations:
9
+
*
10
+
* http://www.opensource.org/licenses/gpl-license.html
11
+
* http://www.gnu.org/copyleft/gpl.html
12
+
*/
13
+
14
+
/include/ "spear3xx.dtsi"
15
+
16
+
/ {
17
+
ahb {
18
+
#address-cells = <1>;
19
+
#size-cells = <1>;
20
+
compatible = "simple-bus";
21
+
ranges = <0x60000000 0x60000000 0x50000000
22
+
0xd0000000 0xd0000000 0x30000000>;
23
+
24
+
pinmux@99000000 {
25
+
compatible = "st,spear300-pinmux";
26
+
reg = <0x99000000 0x1000>;
27
+
};
28
+
29
+
clcd@60000000 {
30
+
compatible = "arm,clcd-pl110", "arm,primecell";
31
+
reg = <0x60000000 0x1000>;
32
+
interrupts = <30>;
33
+
status = "disabled";
34
+
};
35
+
36
+
fsmc: flash@94000000 {
37
+
compatible = "st,spear600-fsmc-nand";
38
+
#address-cells = <1>;
39
+
#size-cells = <1>;
40
+
reg = <0x94000000 0x1000 /* FSMC Register */
41
+
0x80000000 0x0010>; /* NAND Base */
42
+
reg-names = "fsmc_regs", "nand_data";
43
+
st,ale-off = <0x20000>;
44
+
st,cle-off = <0x10000>;
45
+
status = "disabled";
46
+
};
47
+
48
+
sdhci@70000000 {
49
+
compatible = "st,sdhci-spear";
50
+
reg = <0x70000000 0x100>;
51
+
interrupts = <1>;
52
+
status = "disabled";
53
+
};
54
+
55
+
apb {
56
+
#address-cells = <1>;
57
+
#size-cells = <1>;
58
+
compatible = "simple-bus";
59
+
ranges = <0xa0000000 0xa0000000 0x10000000
60
+
0xd0000000 0xd0000000 0x30000000>;
61
+
62
+
gpio1: gpio@a9000000 {
63
+
#gpio-cells = <2>;
64
+
compatible = "arm,pl061", "arm,primecell";
65
+
gpio-controller;
66
+
reg = <0xa9000000 0x1000>;
67
+
status = "disabled";
68
+
};
69
+
70
+
kbd@a0000000 {
71
+
compatible = "st,spear300-kbd";
72
+
reg = <0xa0000000 0x1000>;
73
+
status = "disabled";
74
+
};
75
+
};
76
+
};
77
+
};
+188
arch/arm/boot/dts/spear310-evb.dts
+188
arch/arm/boot/dts/spear310-evb.dts
···
1
+
/*
2
+
* DTS file for SPEAr310 Evaluation Baord
3
+
*
4
+
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5
+
*
6
+
* The code contained herein is licensed under the GNU General Public
7
+
* License. You may obtain a copy of the GNU General Public License
8
+
* Version 2 or later at the following locations:
9
+
*
10
+
* http://www.opensource.org/licenses/gpl-license.html
11
+
* http://www.gnu.org/copyleft/gpl.html
12
+
*/
13
+
14
+
/dts-v1/;
15
+
/include/ "spear310.dtsi"
16
+
17
+
/ {
18
+
model = "ST SPEAr310 Evaluation Board";
19
+
compatible = "st,spear310-evb", "st,spear310";
20
+
#address-cells = <1>;
21
+
#size-cells = <1>;
22
+
23
+
memory {
24
+
reg = <0 0x40000000>;
25
+
};
26
+
27
+
ahb {
28
+
pinmux@b4000000 {
29
+
pinctrl-names = "default";
30
+
pinctrl-0 = <&state_default>;
31
+
32
+
state_default: pinmux {
33
+
gpio0 {
34
+
st,pins = "gpio0_pin0_grp",
35
+
"gpio0_pin1_grp",
36
+
"gpio0_pin2_grp",
37
+
"gpio0_pin3_grp",
38
+
"gpio0_pin4_grp",
39
+
"gpio0_pin5_grp";
40
+
st,function = "gpio0";
41
+
};
42
+
i2c0 {
43
+
st,pins = "i2c0_grp";
44
+
st,function = "i2c0";
45
+
};
46
+
mii0 {
47
+
st,pins = "mii0_grp";
48
+
st,function = "mii0";
49
+
};
50
+
ssp0 {
51
+
st,pins = "ssp0_grp";
52
+
st,function = "ssp0";
53
+
};
54
+
uart0 {
55
+
st,pins = "uart0_grp";
56
+
st,function = "uart0";
57
+
};
58
+
emi {
59
+
st,pins = "emi_cs_0_to_5_grp";
60
+
st,function = "emi";
61
+
};
62
+
fsmc {
63
+
st,pins = "fsmc_grp";
64
+
st,function = "fsmc";
65
+
};
66
+
uart1 {
67
+
st,pins = "uart1_grp";
68
+
st,function = "uart1";
69
+
};
70
+
uart2 {
71
+
st,pins = "uart2_grp";
72
+
st,function = "uart2";
73
+
};
74
+
uart3 {
75
+
st,pins = "uart3_grp";
76
+
st,function = "uart3";
77
+
};
78
+
uart4 {
79
+
st,pins = "uart4_grp";
80
+
st,function = "uart4";
81
+
};
82
+
uart5 {
83
+
st,pins = "uart5_grp";
84
+
st,function = "uart5";
85
+
};
86
+
};
87
+
};
88
+
89
+
dma@fc400000 {
90
+
status = "okay";
91
+
};
92
+
93
+
fsmc: flash@44000000 {
94
+
status = "okay";
95
+
};
96
+
97
+
gmac: eth@e0800000 {
98
+
status = "okay";
99
+
};
100
+
101
+
smi: flash@fc000000 {
102
+
status = "okay";
103
+
clock-rate=<50000000>;
104
+
105
+
flash@f8000000 {
106
+
#address-cells = <1>;
107
+
#size-cells = <1>;
108
+
reg = <0xf8000000 0x800000>;
109
+
st,smi-fast-mode;
110
+
111
+
partition@0 {
112
+
label = "xloader";
113
+
reg = <0x0 0x10000>;
114
+
};
115
+
partition@10000 {
116
+
label = "u-boot";
117
+
reg = <0x10000 0x40000>;
118
+
};
119
+
partition@50000 {
120
+
label = "linux";
121
+
reg = <0x50000 0x2c0000>;
122
+
};
123
+
partition@310000 {
124
+
label = "rootfs";
125
+
reg = <0x310000 0x4f0000>;
126
+
};
127
+
};
128
+
};
129
+
130
+
spi0: spi@d0100000 {
131
+
status = "okay";
132
+
};
133
+
134
+
ehci@e1800000 {
135
+
status = "okay";
136
+
};
137
+
138
+
ohci@e1900000 {
139
+
status = "okay";
140
+
};
141
+
142
+
ohci@e2100000 {
143
+
status = "okay";
144
+
};
145
+
146
+
apb {
147
+
gpio0: gpio@fc980000 {
148
+
status = "okay";
149
+
};
150
+
151
+
i2c0: i2c@d0180000 {
152
+
status = "okay";
153
+
};
154
+
155
+
rtc@fc900000 {
156
+
status = "okay";
157
+
};
158
+
159
+
serial@d0000000 {
160
+
status = "okay";
161
+
};
162
+
163
+
serial@b2000000 {
164
+
status = "okay";
165
+
};
166
+
167
+
serial@b2080000 {
168
+
status = "okay";
169
+
};
170
+
171
+
serial@b2100000 {
172
+
status = "okay";
173
+
};
174
+
175
+
serial@b2180000 {
176
+
status = "okay";
177
+
};
178
+
179
+
serial@b2200000 {
180
+
status = "okay";
181
+
};
182
+
183
+
wdt@fc880000 {
184
+
status = "okay";
185
+
};
186
+
};
187
+
};
188
+
};
+80
arch/arm/boot/dts/spear310.dtsi
+80
arch/arm/boot/dts/spear310.dtsi
···
1
+
/*
2
+
* DTS file for SPEAr310 SoC
3
+
*
4
+
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5
+
*
6
+
* The code contained herein is licensed under the GNU General Public
7
+
* License. You may obtain a copy of the GNU General Public License
8
+
* Version 2 or later at the following locations:
9
+
*
10
+
* http://www.opensource.org/licenses/gpl-license.html
11
+
* http://www.gnu.org/copyleft/gpl.html
12
+
*/
13
+
14
+
/include/ "spear3xx.dtsi"
15
+
16
+
/ {
17
+
ahb {
18
+
#address-cells = <1>;
19
+
#size-cells = <1>;
20
+
compatible = "simple-bus";
21
+
ranges = <0x40000000 0x40000000 0x10000000
22
+
0xb0000000 0xb0000000 0x10000000
23
+
0xd0000000 0xd0000000 0x30000000>;
24
+
25
+
pinmux@b4000000 {
26
+
compatible = "st,spear310-pinmux";
27
+
reg = <0xb4000000 0x1000>;
28
+
};
29
+
30
+
fsmc: flash@44000000 {
31
+
compatible = "st,spear600-fsmc-nand";
32
+
#address-cells = <1>;
33
+
#size-cells = <1>;
34
+
reg = <0x44000000 0x1000 /* FSMC Register */
35
+
0x40000000 0x0010>; /* NAND Base */
36
+
reg-names = "fsmc_regs", "nand_data";
37
+
st,ale-off = <0x10000>;
38
+
st,cle-off = <0x20000>;
39
+
status = "disabled";
40
+
};
41
+
42
+
apb {
43
+
#address-cells = <1>;
44
+
#size-cells = <1>;
45
+
compatible = "simple-bus";
46
+
ranges = <0xb0000000 0xb0000000 0x10000000
47
+
0xd0000000 0xd0000000 0x30000000>;
48
+
49
+
serial@b2000000 {
50
+
compatible = "arm,pl011", "arm,primecell";
51
+
reg = <0xb2000000 0x1000>;
52
+
status = "disabled";
53
+
};
54
+
55
+
serial@b2080000 {
56
+
compatible = "arm,pl011", "arm,primecell";
57
+
reg = <0xb2080000 0x1000>;
58
+
status = "disabled";
59
+
};
60
+
61
+
serial@b2100000 {
62
+
compatible = "arm,pl011", "arm,primecell";
63
+
reg = <0xb2100000 0x1000>;
64
+
status = "disabled";
65
+
};
66
+
67
+
serial@b2180000 {
68
+
compatible = "arm,pl011", "arm,primecell";
69
+
reg = <0xb2180000 0x1000>;
70
+
status = "disabled";
71
+
};
72
+
73
+
serial@b2200000 {
74
+
compatible = "arm,pl011", "arm,primecell";
75
+
reg = <0xb2200000 0x1000>;
76
+
status = "disabled";
77
+
};
78
+
};
79
+
};
80
+
};
+198
arch/arm/boot/dts/spear320-evb.dts
+198
arch/arm/boot/dts/spear320-evb.dts
···
1
+
/*
2
+
* DTS file for SPEAr320 Evaluation Baord
3
+
*
4
+
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5
+
*
6
+
* The code contained herein is licensed under the GNU General Public
7
+
* License. You may obtain a copy of the GNU General Public License
8
+
* Version 2 or later at the following locations:
9
+
*
10
+
* http://www.opensource.org/licenses/gpl-license.html
11
+
* http://www.gnu.org/copyleft/gpl.html
12
+
*/
13
+
14
+
/dts-v1/;
15
+
/include/ "spear320.dtsi"
16
+
17
+
/ {
18
+
model = "ST SPEAr300 Evaluation Board";
19
+
compatible = "st,spear300-evb", "st,spear300";
20
+
#address-cells = <1>;
21
+
#size-cells = <1>;
22
+
23
+
memory {
24
+
reg = <0 0x40000000>;
25
+
};
26
+
27
+
ahb {
28
+
pinmux@b3000000 {
29
+
st,pinmux-mode = <3>;
30
+
pinctrl-names = "default";
31
+
pinctrl-0 = <&state_default>;
32
+
33
+
state_default: pinmux {
34
+
i2c0 {
35
+
st,pins = "i2c0_grp";
36
+
st,function = "i2c0";
37
+
};
38
+
mii0 {
39
+
st,pins = "mii0_grp";
40
+
st,function = "mii0";
41
+
};
42
+
ssp0 {
43
+
st,pins = "ssp0_grp";
44
+
st,function = "ssp0";
45
+
};
46
+
uart0 {
47
+
st,pins = "uart0_grp";
48
+
st,function = "uart0";
49
+
};
50
+
sdhci {
51
+
st,pins = "sdhci_cd_51_grp";
52
+
st,function = "sdhci";
53
+
};
54
+
i2s {
55
+
st,pins = "i2s_grp";
56
+
st,function = "i2s";
57
+
};
58
+
uart1 {
59
+
st,pins = "uart1_grp";
60
+
st,function = "uart1";
61
+
};
62
+
uart2 {
63
+
st,pins = "uart2_grp";
64
+
st,function = "uart2";
65
+
};
66
+
can0 {
67
+
st,pins = "can0_grp";
68
+
st,function = "can0";
69
+
};
70
+
can1 {
71
+
st,pins = "can1_grp";
72
+
st,function = "can1";
73
+
};
74
+
mii2 {
75
+
st,pins = "mii2_grp";
76
+
st,function = "mii2";
77
+
};
78
+
pwm0_1 {
79
+
st,pins = "pwm0_1_pin_14_15_grp";
80
+
st,function = "pwm0_1";
81
+
};
82
+
pwm2 {
83
+
st,pins = "pwm2_pin_13_grp";
84
+
st,function = "pwm2";
85
+
};
86
+
};
87
+
};
88
+
89
+
clcd@90000000 {
90
+
status = "okay";
91
+
};
92
+
93
+
dma@fc400000 {
94
+
status = "okay";
95
+
};
96
+
97
+
fsmc: flash@4c000000 {
98
+
status = "okay";
99
+
};
100
+
101
+
gmac: eth@e0800000 {
102
+
status = "okay";
103
+
};
104
+
105
+
sdhci@70000000 {
106
+
power-gpio = <&gpio0 2 1>;
107
+
power_always_enb;
108
+
status = "okay";
109
+
};
110
+
111
+
smi: flash@fc000000 {
112
+
status = "okay";
113
+
clock-rate=<50000000>;
114
+
115
+
flash@f8000000 {
116
+
#address-cells = <1>;
117
+
#size-cells = <1>;
118
+
reg = <0xf8000000 0x800000>;
119
+
st,smi-fast-mode;
120
+
121
+
partition@0 {
122
+
label = "xloader";
123
+
reg = <0x0 0x10000>;
124
+
};
125
+
partition@10000 {
126
+
label = "u-boot";
127
+
reg = <0x10000 0x40000>;
128
+
};
129
+
partition@50000 {
130
+
label = "linux";
131
+
reg = <0x50000 0x2c0000>;
132
+
};
133
+
partition@310000 {
134
+
label = "rootfs";
135
+
reg = <0x310000 0x4f0000>;
136
+
};
137
+
};
138
+
};
139
+
140
+
spi0: spi@d0100000 {
141
+
status = "okay";
142
+
};
143
+
144
+
spi1: spi@a5000000 {
145
+
status = "okay";
146
+
};
147
+
148
+
spi2: spi@a6000000 {
149
+
status = "okay";
150
+
};
151
+
152
+
ehci@e1800000 {
153
+
status = "okay";
154
+
};
155
+
156
+
ohci@e1900000 {
157
+
status = "okay";
158
+
};
159
+
160
+
ohci@e2100000 {
161
+
status = "okay";
162
+
};
163
+
164
+
apb {
165
+
gpio0: gpio@fc980000 {
166
+
status = "okay";
167
+
};
168
+
169
+
i2c0: i2c@d0180000 {
170
+
status = "okay";
171
+
};
172
+
173
+
i2c1: i2c@a7000000 {
174
+
status = "okay";
175
+
};
176
+
177
+
rtc@fc900000 {
178
+
status = "okay";
179
+
};
180
+
181
+
serial@d0000000 {
182
+
status = "okay";
183
+
};
184
+
185
+
serial@a3000000 {
186
+
status = "okay";
187
+
};
188
+
189
+
serial@a4000000 {
190
+
status = "okay";
191
+
};
192
+
193
+
wdt@fc880000 {
194
+
status = "okay";
195
+
};
196
+
};
197
+
};
198
+
};
+95
arch/arm/boot/dts/spear320.dtsi
+95
arch/arm/boot/dts/spear320.dtsi
···
1
+
/*
2
+
* DTS file for SPEAr320 SoC
3
+
*
4
+
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5
+
*
6
+
* The code contained herein is licensed under the GNU General Public
7
+
* License. You may obtain a copy of the GNU General Public License
8
+
* Version 2 or later at the following locations:
9
+
*
10
+
* http://www.opensource.org/licenses/gpl-license.html
11
+
* http://www.gnu.org/copyleft/gpl.html
12
+
*/
13
+
14
+
/include/ "spear3xx.dtsi"
15
+
16
+
/ {
17
+
ahb {
18
+
#address-cells = <1>;
19
+
#size-cells = <1>;
20
+
compatible = "simple-bus";
21
+
ranges = <0x40000000 0x40000000 0x80000000
22
+
0xd0000000 0xd0000000 0x30000000>;
23
+
24
+
pinmux@b3000000 {
25
+
compatible = "st,spear320-pinmux";
26
+
reg = <0xb3000000 0x1000>;
27
+
};
28
+
29
+
clcd@90000000 {
30
+
compatible = "arm,clcd-pl110", "arm,primecell";
31
+
reg = <0x90000000 0x1000>;
32
+
interrupts = <33>;
33
+
status = "disabled";
34
+
};
35
+
36
+
fsmc: flash@4c000000 {
37
+
compatible = "st,spear600-fsmc-nand";
38
+
#address-cells = <1>;
39
+
#size-cells = <1>;
40
+
reg = <0x4c000000 0x1000 /* FSMC Register */
41
+
0x50000000 0x0010>; /* NAND Base */
42
+
reg-names = "fsmc_regs", "nand_data";
43
+
st,ale-off = <0x20000>;
44
+
st,cle-off = <0x10000>;
45
+
status = "disabled";
46
+
};
47
+
48
+
sdhci@70000000 {
49
+
compatible = "st,sdhci-spear";
50
+
reg = <0x70000000 0x100>;
51
+
interrupts = <29>;
52
+
status = "disabled";
53
+
};
54
+
55
+
spi1: spi@a5000000 {
56
+
compatible = "arm,pl022", "arm,primecell";
57
+
reg = <0xa5000000 0x1000>;
58
+
status = "disabled";
59
+
};
60
+
61
+
spi2: spi@a6000000 {
62
+
compatible = "arm,pl022", "arm,primecell";
63
+
reg = <0xa6000000 0x1000>;
64
+
status = "disabled";
65
+
};
66
+
67
+
apb {
68
+
#address-cells = <1>;
69
+
#size-cells = <1>;
70
+
compatible = "simple-bus";
71
+
ranges = <0xa0000000 0xa0000000 0x10000000
72
+
0xd0000000 0xd0000000 0x30000000>;
73
+
74
+
i2c1: i2c@a7000000 {
75
+
#address-cells = <1>;
76
+
#size-cells = <0>;
77
+
compatible = "snps,designware-i2c";
78
+
reg = <0xa7000000 0x1000>;
79
+
status = "disabled";
80
+
};
81
+
82
+
serial@a3000000 {
83
+
compatible = "arm,pl011", "arm,primecell";
84
+
reg = <0xa3000000 0x1000>;
85
+
status = "disabled";
86
+
};
87
+
88
+
serial@a4000000 {
89
+
compatible = "arm,pl011", "arm,primecell";
90
+
reg = <0xa4000000 0x1000>;
91
+
status = "disabled";
92
+
};
93
+
};
94
+
};
95
+
};
+150
arch/arm/boot/dts/spear3xx.dtsi
+150
arch/arm/boot/dts/spear3xx.dtsi
···
1
+
/*
2
+
* DTS file for all SPEAr3xx SoCs
3
+
*
4
+
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5
+
*
6
+
* The code contained herein is licensed under the GNU General Public
7
+
* License. You may obtain a copy of the GNU General Public License
8
+
* Version 2 or later at the following locations:
9
+
*
10
+
* http://www.opensource.org/licenses/gpl-license.html
11
+
* http://www.gnu.org/copyleft/gpl.html
12
+
*/
13
+
14
+
/include/ "skeleton.dtsi"
15
+
16
+
/ {
17
+
interrupt-parent = <&vic>;
18
+
19
+
cpus {
20
+
cpu@0 {
21
+
compatible = "arm,arm926ejs";
22
+
};
23
+
};
24
+
25
+
memory {
26
+
device_type = "memory";
27
+
reg = <0 0x40000000>;
28
+
};
29
+
30
+
ahb {
31
+
#address-cells = <1>;
32
+
#size-cells = <1>;
33
+
compatible = "simple-bus";
34
+
ranges = <0xd0000000 0xd0000000 0x30000000>;
35
+
36
+
vic: interrupt-controller@f1100000 {
37
+
compatible = "arm,pl190-vic";
38
+
interrupt-controller;
39
+
reg = <0xf1100000 0x1000>;
40
+
#interrupt-cells = <1>;
41
+
};
42
+
43
+
dma@fc400000 {
44
+
compatible = "arm,pl080", "arm,primecell";
45
+
reg = <0xfc400000 0x1000>;
46
+
interrupt-parent = <&vic>;
47
+
interrupts = <8>;
48
+
status = "disabled";
49
+
};
50
+
51
+
gmac: eth@e0800000 {
52
+
compatible = "st,spear600-gmac";
53
+
reg = <0xe0800000 0x8000>;
54
+
interrupts = <23 22>;
55
+
interrupt-names = "macirq", "eth_wake_irq";
56
+
status = "disabled";
57
+
};
58
+
59
+
smi: flash@fc000000 {
60
+
compatible = "st,spear600-smi";
61
+
#address-cells = <1>;
62
+
#size-cells = <1>;
63
+
reg = <0xfc000000 0x1000>;
64
+
interrupts = <9>;
65
+
status = "disabled";
66
+
};
67
+
68
+
spi0: spi@d0100000 {
69
+
compatible = "arm,pl022", "arm,primecell";
70
+
reg = <0xd0100000 0x1000>;
71
+
interrupts = <20>;
72
+
status = "disabled";
73
+
};
74
+
75
+
ehci@e1800000 {
76
+
compatible = "st,spear600-ehci", "usb-ehci";
77
+
reg = <0xe1800000 0x1000>;
78
+
interrupts = <26>;
79
+
status = "disabled";
80
+
};
81
+
82
+
ohci@e1900000 {
83
+
compatible = "st,spear600-ohci", "usb-ohci";
84
+
reg = <0xe1900000 0x1000>;
85
+
interrupts = <25>;
86
+
status = "disabled";
87
+
};
88
+
89
+
ohci@e2100000 {
90
+
compatible = "st,spear600-ohci", "usb-ohci";
91
+
reg = <0xe2100000 0x1000>;
92
+
interrupts = <27>;
93
+
status = "disabled";
94
+
};
95
+
96
+
apb {
97
+
#address-cells = <1>;
98
+
#size-cells = <1>;
99
+
compatible = "simple-bus";
100
+
ranges = <0xd0000000 0xd0000000 0x30000000>;
101
+
102
+
gpio0: gpio@fc980000 {
103
+
compatible = "arm,pl061", "arm,primecell";
104
+
reg = <0xfc980000 0x1000>;
105
+
interrupts = <11>;
106
+
gpio-controller;
107
+
#gpio-cells = <2>;
108
+
interrupt-controller;
109
+
#interrupt-cells = <2>;
110
+
status = "disabled";
111
+
};
112
+
113
+
i2c0: i2c@d0180000 {
114
+
#address-cells = <1>;
115
+
#size-cells = <0>;
116
+
compatible = "snps,designware-i2c";
117
+
reg = <0xd0180000 0x1000>;
118
+
interrupts = <21>;
119
+
status = "disabled";
120
+
};
121
+
122
+
rtc@fc900000 {
123
+
compatible = "st,spear-rtc";
124
+
reg = <0xfc900000 0x1000>;
125
+
interrupts = <10>;
126
+
status = "disabled";
127
+
};
128
+
129
+
serial@d0000000 {
130
+
compatible = "arm,pl011", "arm,primecell";
131
+
reg = <0xd0000000 0x1000>;
132
+
interrupts = <19>;
133
+
status = "disabled";
134
+
};
135
+
136
+
wdt@fc880000 {
137
+
compatible = "arm,sp805", "arm,primecell";
138
+
reg = <0xfc880000 0x1000>;
139
+
interrupts = <12>;
140
+
status = "disabled";
141
+
};
142
+
143
+
timer@f0000000 {
144
+
compatible = "st,spear-timer";
145
+
reg = <0xf0000000 0x400>;
146
+
interrupts = <2>;
147
+
};
148
+
};
149
+
};
150
+
};
+33
arch/arm/boot/dts/spear600-evb.dts
+33
arch/arm/boot/dts/spear600-evb.dts
···
24
24
};
25
25
26
26
ahb {
27
+
dma@fc400000 {
28
+
status = "okay";
29
+
};
30
+
27
31
gmac: ethernet@e0800000 {
28
32
phy-mode = "gmii";
29
33
status = "okay";
34
+
};
35
+
36
+
smi: flash@fc000000 {
37
+
status = "okay";
38
+
clock-rate=<50000000>;
39
+
40
+
flash@f8000000 {
41
+
#address-cells = <1>;
42
+
#size-cells = <1>;
43
+
reg = <0xf8000000 0x800000>;
44
+
st,smi-fast-mode;
45
+
46
+
partition@0 {
47
+
label = "xloader";
48
+
reg = <0x0 0x10000>;
49
+
};
50
+
partition@10000 {
51
+
label = "u-boot";
52
+
reg = <0x10000 0x40000>;
53
+
};
54
+
partition@50000 {
55
+
label = "linux";
56
+
reg = <0x50000 0x2c0000>;
57
+
};
58
+
partition@310000 {
59
+
label = "rootfs";
60
+
reg = <0x310000 0x4f0000>;
61
+
};
62
+
};
30
63
};
31
64
32
65
apb {
+14
arch/arm/boot/dts/spear600.dtsi
+14
arch/arm/boot/dts/spear600.dtsi
···
45
45
#interrupt-cells = <1>;
46
46
};
47
47
48
+
dma@fc400000 {
49
+
compatible = "arm,pl080", "arm,primecell";
50
+
reg = <0xfc400000 0x1000>;
51
+
interrupt-parent = <&vic1>;
52
+
interrupts = <10>;
53
+
status = "disabled";
54
+
};
55
+
48
56
gmac: ethernet@e0800000 {
49
57
compatible = "st,spear600-gmac";
50
58
reg = <0xe0800000 0x8000>;
···
176
168
interrupt-parent = <&vic0>;
177
169
interrupts = <28>;
178
170
status = "disabled";
171
+
};
172
+
173
+
timer@f0000000 {
174
+
compatible = "st,spear-timer";
175
+
reg = <0xf0000000 0x400>;
176
+
interrupts = <16>;
179
177
};
180
178
};
181
179
};
+45
-11
arch/arm/configs/spear3xx_defconfig
+45
-11
arch/arm/configs/spear3xx_defconfig
···
2
2
CONFIG_SYSVIPC=y
3
3
CONFIG_BSD_PROCESS_ACCT=y
4
4
CONFIG_BLK_DEV_INITRD=y
5
-
CONFIG_KALLSYMS_EXTRA_PASS=y
6
5
CONFIG_MODULES=y
7
6
CONFIG_MODULE_UNLOAD=y
8
7
CONFIG_MODVERSIONS=y
8
+
CONFIG_PARTITION_ADVANCED=y
9
9
CONFIG_PLAT_SPEAR=y
10
-
CONFIG_BOARD_SPEAR300_EVB=y
11
-
CONFIG_BOARD_SPEAR310_EVB=y
12
-
CONFIG_BOARD_SPEAR320_EVB=y
10
+
CONFIG_MACH_SPEAR300=y
11
+
CONFIG_MACH_SPEAR310=y
12
+
CONFIG_MACH_SPEAR320=y
13
13
CONFIG_BINFMT_MISC=y
14
+
CONFIG_NET=y
14
15
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
16
+
CONFIG_MTD=y
17
+
CONFIG_MTD_OF_PARTS=y
18
+
CONFIG_MTD_CHAR=y
19
+
CONFIG_MTD_BLOCK=y
20
+
CONFIG_MTD_NAND=y
21
+
CONFIG_MTD_NAND_FSMC=y
15
22
CONFIG_BLK_DEV_RAM=y
16
23
CONFIG_BLK_DEV_RAM_SIZE=16384
24
+
CONFIG_NETDEVICES=y
25
+
# CONFIG_NET_VENDOR_BROADCOM is not set
26
+
# CONFIG_NET_VENDOR_CIRRUS is not set
27
+
# CONFIG_NET_VENDOR_FARADAY is not set
28
+
# CONFIG_NET_VENDOR_INTEL is not set
29
+
# CONFIG_NET_VENDOR_MICREL is not set
30
+
# CONFIG_NET_VENDOR_NATSEMI is not set
31
+
# CONFIG_NET_VENDOR_SEEQ is not set
32
+
# CONFIG_NET_VENDOR_SMSC is not set
33
+
CONFIG_STMMAC_ETH=y
34
+
# CONFIG_WLAN is not set
17
35
CONFIG_INPUT_FF_MEMLESS=y
18
36
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
19
-
# CONFIG_INPUT_KEYBOARD is not set
37
+
# CONFIG_KEYBOARD_ATKBD is not set
38
+
CONFIG_KEYBOARD_SPEAR=y
20
39
# CONFIG_INPUT_MOUSE is not set
40
+
# CONFIG_LEGACY_PTYS is not set
21
41
CONFIG_SERIAL_AMBA_PL011=y
22
42
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
23
-
# CONFIG_LEGACY_PTYS is not set
24
43
# CONFIG_HW_RANDOM is not set
25
44
CONFIG_RAW_DRIVER=y
26
45
CONFIG_MAX_RAW_DEVS=8192
46
+
CONFIG_I2C=y
47
+
CONFIG_I2C_DESIGNWARE_PLATFORM=y
48
+
CONFIG_SPI=y
49
+
CONFIG_SPI_PL022=y
27
50
CONFIG_GPIO_SYSFS=y
28
51
CONFIG_GPIO_PL061=y
29
52
# CONFIG_HWMON is not set
53
+
CONFIG_WATCHDOG=y
54
+
CONFIG_ARM_SP805_WATCHDOG=y
55
+
CONFIG_FB=y
56
+
CONFIG_FB_ARMCLCD=y
30
57
# CONFIG_HID_SUPPORT is not set
31
-
# CONFIG_USB_SUPPORT is not set
58
+
CONFIG_USB=y
59
+
# CONFIG_USB_DEVICE_CLASS is not set
60
+
CONFIG_USB_EHCI_HCD=y
61
+
CONFIG_USB_OHCI_HCD=y
62
+
CONFIG_MMC=y
63
+
CONFIG_MMC_SDHCI=y
64
+
CONFIG_MMC_SDHCI_SPEAR=y
65
+
CONFIG_RTC_CLASS=y
66
+
CONFIG_DMADEVICES=y
67
+
CONFIG_AMBA_PL08X=y
68
+
CONFIG_DMATEST=m
32
69
CONFIG_EXT2_FS=y
33
70
CONFIG_EXT2_FS_XATTR=y
34
71
CONFIG_EXT2_FS_SECURITY=y
···
76
39
CONFIG_VFAT_FS=m
77
40
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
78
41
CONFIG_TMPFS=y
79
-
CONFIG_PARTITION_ADVANCED=y
80
-
CONFIG_NLS=y
42
+
CONFIG_JFFS2_FS=y
81
43
CONFIG_NLS_DEFAULT="utf8"
82
44
CONFIG_NLS_CODEPAGE_437=y
83
45
CONFIG_NLS_ASCII=m
···
84
48
CONFIG_DEBUG_FS=y
85
49
CONFIG_DEBUG_KERNEL=y
86
50
CONFIG_DEBUG_SPINLOCK=y
87
-
CONFIG_DEBUG_SPINLOCK_SLEEP=y
88
51
CONFIG_DEBUG_INFO=y
89
-
# CONFIG_CRC32 is not set
+36
-8
arch/arm/configs/spear6xx_defconfig
+36
-8
arch/arm/configs/spear6xx_defconfig
···
2
2
CONFIG_SYSVIPC=y
3
3
CONFIG_BSD_PROCESS_ACCT=y
4
4
CONFIG_BLK_DEV_INITRD=y
5
-
CONFIG_KALLSYMS_EXTRA_PASS=y
6
5
CONFIG_MODULES=y
7
6
CONFIG_MODULE_UNLOAD=y
8
7
CONFIG_MODVERSIONS=y
8
+
CONFIG_PARTITION_ADVANCED=y
9
9
CONFIG_PLAT_SPEAR=y
10
10
CONFIG_ARCH_SPEAR6XX=y
11
-
CONFIG_BOARD_SPEAR600_EVB=y
12
11
CONFIG_BINFMT_MISC=y
12
+
CONFIG_NET=y
13
13
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
14
+
CONFIG_MTD=y
15
+
CONFIG_MTD_OF_PARTS=y
16
+
CONFIG_MTD_CHAR=y
17
+
CONFIG_MTD_BLOCK=y
18
+
CONFIG_MTD_NAND=y
19
+
CONFIG_MTD_NAND_FSMC=y
14
20
CONFIG_BLK_DEV_RAM=y
15
21
CONFIG_BLK_DEV_RAM_SIZE=16384
22
+
CONFIG_NETDEVICES=y
23
+
# CONFIG_NET_VENDOR_BROADCOM is not set
24
+
# CONFIG_NET_VENDOR_CIRRUS is not set
25
+
# CONFIG_NET_VENDOR_FARADAY is not set
26
+
# CONFIG_NET_VENDOR_INTEL is not set
27
+
# CONFIG_NET_VENDOR_MICREL is not set
28
+
# CONFIG_NET_VENDOR_NATSEMI is not set
29
+
# CONFIG_NET_VENDOR_SEEQ is not set
30
+
# CONFIG_NET_VENDOR_SMSC is not set
31
+
CONFIG_STMMAC_ETH=y
32
+
# CONFIG_WLAN is not set
16
33
CONFIG_INPUT_FF_MEMLESS=y
17
34
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
35
+
# CONFIG_INPUT_KEYBOARD is not set
36
+
# CONFIG_INPUT_MOUSE is not set
37
+
# CONFIG_LEGACY_PTYS is not set
18
38
CONFIG_SERIAL_AMBA_PL011=y
19
39
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
20
-
# CONFIG_LEGACY_PTYS is not set
21
40
CONFIG_RAW_DRIVER=y
22
41
CONFIG_MAX_RAW_DEVS=8192
42
+
CONFIG_I2C=y
43
+
CONFIG_I2C_DESIGNWARE_PLATFORM=y
44
+
CONFIG_SPI=y
45
+
CONFIG_SPI_PL022=y
23
46
CONFIG_GPIO_SYSFS=y
24
47
CONFIG_GPIO_PL061=y
25
48
# CONFIG_HWMON is not set
49
+
CONFIG_WATCHDOG=y
50
+
CONFIG_ARM_SP805_WATCHDOG=y
26
51
# CONFIG_HID_SUPPORT is not set
27
-
# CONFIG_USB_SUPPORT is not set
52
+
CONFIG_USB=y
53
+
CONFIG_USB_EHCI_HCD=y
54
+
CONFIG_USB_OHCI_HCD=y
55
+
CONFIG_RTC_CLASS=y
56
+
CONFIG_DMADEVICES=y
57
+
CONFIG_AMBA_PL08X=y
58
+
CONFIG_DMATEST=m
28
59
CONFIG_EXT2_FS=y
29
60
CONFIG_EXT2_FS_XATTR=y
30
61
CONFIG_EXT2_FS_SECURITY=y
···
66
35
CONFIG_VFAT_FS=m
67
36
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
68
37
CONFIG_TMPFS=y
69
-
CONFIG_PARTITION_ADVANCED=y
70
-
CONFIG_NLS=y
38
+
CONFIG_JFFS2_FS=y
71
39
CONFIG_NLS_DEFAULT="utf8"
72
40
CONFIG_NLS_CODEPAGE_437=y
73
41
CONFIG_NLS_ASCII=m
···
74
44
CONFIG_DEBUG_FS=y
75
45
CONFIG_DEBUG_KERNEL=y
76
46
CONFIG_DEBUG_SPINLOCK=y
77
-
CONFIG_DEBUG_SPINLOCK_SLEEP=y
78
47
CONFIG_DEBUG_INFO=y
79
-
# CONFIG_CRC32 is not set
+2
arch/arm/mach-imx/Kconfig
+2
arch/arm/mach-imx/Kconfig
+3
arch/arm/mach-imx/imx51-dt.c
+3
arch/arm/mach-imx/imx51-dt.c
···
14
14
#include <linux/irqdomain.h>
15
15
#include <linux/of_irq.h>
16
16
#include <linux/of_platform.h>
17
+
#include <linux/pinctrl/machine.h>
17
18
#include <asm/mach/arch.h>
18
19
#include <asm/mach/time.h>
19
20
#include <mach/common.h>
···
81
80
void (*func)(void);
82
81
83
82
of_irq_init(imx51_irq_match);
83
+
84
+
pinctrl_provide_dummies();
84
85
85
86
node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
86
87
if (node) {
+3
arch/arm/mach-imx/imx53-dt.c
+3
arch/arm/mach-imx/imx53-dt.c
···
15
15
#include <linux/irqdomain.h>
16
16
#include <linux/of_irq.h>
17
17
#include <linux/of_platform.h>
18
+
#include <linux/pinctrl/machine.h>
18
19
#include <asm/mach/arch.h>
19
20
#include <asm/mach/time.h>
20
21
#include <mach/common.h>
···
88
87
void (*func)(void);
89
88
90
89
of_irq_init(imx53_irq_match);
90
+
91
+
pinctrl_provide_dummies();
91
92
92
93
node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
93
94
if (node) {
+7
arch/arm/mach-imx/mach-imx6q.c
+7
arch/arm/mach-imx/mach-imx6q.c
···
19
19
#include <linux/of_address.h>
20
20
#include <linux/of_irq.h>
21
21
#include <linux/of_platform.h>
22
+
#include <linux/pinctrl/machine.h>
22
23
#include <linux/phy.h>
23
24
#include <linux/micrel_phy.h>
24
25
#include <asm/smp_twd.h>
···
78
77
79
78
static void __init imx6q_init_machine(void)
80
79
{
80
+
/*
81
+
* This should be removed when all imx6q boards have pinctrl
82
+
* states for devices defined in device tree.
83
+
*/
84
+
pinctrl_provide_dummies();
85
+
81
86
if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
82
87
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
83
88
ksz9021rn_phy_fixup);
+2
arch/arm/mach-imx/mm-imx1.c
+2
arch/arm/mach-imx/mm-imx1.c
···
18
18
#include <linux/kernel.h>
19
19
#include <linux/init.h>
20
20
#include <linux/io.h>
21
+
#include <linux/pinctrl/machine.h>
21
22
22
23
#include <asm/mach/map.h>
23
24
···
59
58
MX1_GPIO_INT_PORTC, 0);
60
59
mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
61
60
MX1_GPIO_INT_PORTD, 0);
61
+
pinctrl_provide_dummies();
62
62
}
+2
arch/arm/mach-imx/mm-imx21.c
+2
arch/arm/mach-imx/mm-imx21.c
···
20
20
21
21
#include <linux/mm.h>
22
22
#include <linux/init.h>
23
+
#include <linux/pinctrl/machine.h>
23
24
#include <mach/hardware.h>
24
25
#include <mach/common.h>
25
26
#include <mach/devices-common.h>
···
89
88
mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
90
89
mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
91
90
91
+
pinctrl_provide_dummies();
92
92
imx_add_imx_dma();
93
93
platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
94
94
ARRAY_SIZE(imx21_audmux_res));
+2
arch/arm/mach-imx/mm-imx25.c
+2
arch/arm/mach-imx/mm-imx25.c
···
19
19
#include <linux/mm.h>
20
20
#include <linux/init.h>
21
21
#include <linux/err.h>
22
+
#include <linux/pinctrl/machine.h>
22
23
23
24
#include <asm/pgtable.h>
24
25
#include <asm/mach/map.h>
···
96
95
mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
97
96
mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
98
97
98
+
pinctrl_provide_dummies();
99
99
/* i.mx25 has the i.mx35 type sdma */
100
100
imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
101
101
/* i.mx25 has the i.mx31 type audmux */
+2
arch/arm/mach-imx/mm-imx27.c
+2
arch/arm/mach-imx/mm-imx27.c
···
20
20
21
21
#include <linux/mm.h>
22
22
#include <linux/init.h>
23
+
#include <linux/pinctrl/machine.h>
23
24
#include <mach/hardware.h>
24
25
#include <mach/common.h>
25
26
#include <mach/devices-common.h>
···
90
89
mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
91
90
mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
92
91
92
+
pinctrl_provide_dummies();
93
93
imx_add_imx_dma();
94
94
/* imx27 has the imx21 type audmux */
95
95
platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
+2
arch/arm/mach-imx/mm-imx3.c
+2
arch/arm/mach-imx/mm-imx3.c
···
19
19
#include <linux/mm.h>
20
20
#include <linux/init.h>
21
21
#include <linux/err.h>
22
+
#include <linux/pinctrl/machine.h>
22
23
23
24
#include <asm/pgtable.h>
24
25
#include <asm/system_misc.h>
···
274
273
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
275
274
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
276
275
276
+
pinctrl_provide_dummies();
277
277
if (to_version == 1) {
278
278
strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
279
279
strlen(imx35_sdma_pdata.fw_name));
+2
arch/arm/mach-imx/mm-imx5.c
+2
arch/arm/mach-imx/mm-imx5.c
···
14
14
#include <linux/mm.h>
15
15
#include <linux/init.h>
16
16
#include <linux/clk.h>
17
+
#include <linux/pinctrl/machine.h>
17
18
18
19
#include <asm/system_misc.h>
19
20
#include <asm/mach/map.h>
···
225
224
mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
226
225
mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
227
226
227
+
pinctrl_provide_dummies();
228
228
/* i.mx53 has the i.mx35 type sdma */
229
229
imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
230
230
+2
arch/arm/mach-mxs/Kconfig
+2
arch/arm/mach-mxs/Kconfig
+2
arch/arm/mach-mxs/include/mach/common.h
+2
arch/arm/mach-mxs/include/mach/common.h
···
17
17
extern void mxs_restart(char, const char *);
18
18
extern int mxs_saif_clkmux_select(unsigned int clkmux);
19
19
20
+
extern void mx23_soc_init(void);
20
21
extern int mx23_register_gpios(void);
21
22
extern int mx23_clocks_init(void);
22
23
extern void mx23_map_io(void);
23
24
extern void mx23_init_irq(void);
24
25
26
+
extern void mx28_soc_init(void);
25
27
extern int mx28_register_gpios(void);
26
28
extern int mx28_clocks_init(void);
27
29
extern void mx28_map_io(void);
+2
arch/arm/mach-mxs/mach-apx4devkit.c
+2
arch/arm/mach-mxs/mach-apx4devkit.c
+2
arch/arm/mach-mxs/mach-m28evk.c
+2
arch/arm/mach-mxs/mach-m28evk.c
+2
arch/arm/mach-mxs/mach-mx23evk.c
+2
arch/arm/mach-mxs/mach-mx23evk.c
+2
arch/arm/mach-mxs/mach-mx28evk.c
+2
arch/arm/mach-mxs/mach-mx28evk.c
+2
arch/arm/mach-mxs/mach-stmp378x_devb.c
+2
arch/arm/mach-mxs/mach-stmp378x_devb.c
+2
arch/arm/mach-mxs/mach-tx28.c
+2
arch/arm/mach-mxs/mach-tx28.c
+11
arch/arm/mach-mxs/mm.c
+11
arch/arm/mach-mxs/mm.c
···
13
13
14
14
#include <linux/mm.h>
15
15
#include <linux/init.h>
16
+
#include <linux/pinctrl/machine.h>
16
17
17
18
#include <asm/mach/map.h>
18
19
···
61
60
void __init mx28_init_irq(void)
62
61
{
63
62
icoll_init_irq();
63
+
}
64
+
65
+
void __init mx23_soc_init(void)
66
+
{
67
+
pinctrl_provide_dummies();
68
+
}
69
+
70
+
void __init mx28_soc_init(void)
71
+
{
72
+
pinctrl_provide_dummies();
64
73
}
+10
-27
arch/arm/mach-spear3xx/Kconfig
+10
-27
arch/arm/mach-spear3xx/Kconfig
···
5
5
if ARCH_SPEAR3XX
6
6
7
7
menu "SPEAr3xx Implementations"
8
-
config BOARD_SPEAR300_EVB
9
-
bool "SPEAr300 Evaluation Board"
10
-
select MACH_SPEAR300
11
-
help
12
-
Supports ST SPEAr300 Evaluation Board
13
-
14
-
config BOARD_SPEAR310_EVB
15
-
bool "SPEAr310 Evaluation Board"
16
-
select MACH_SPEAR310
17
-
help
18
-
Supports ST SPEAr310 Evaluation Board
19
-
20
-
config BOARD_SPEAR320_EVB
21
-
bool "SPEAr320 Evaluation Board"
22
-
select MACH_SPEAR320
23
-
help
24
-
Supports ST SPEAr320 Evaluation Board
25
-
26
-
endmenu
27
-
28
8
config MACH_SPEAR300
29
-
bool "SPEAr300"
9
+
bool "SPEAr300 Machine support with Device Tree"
10
+
select PINCTRL_SPEAR300
30
11
help
31
-
Supports ST SPEAr300 Machine
12
+
Supports ST SPEAr300 machine configured via the device-tree
32
13
33
14
config MACH_SPEAR310
34
-
bool "SPEAr310"
15
+
bool "SPEAr310 Machine support with Device Tree"
16
+
select PINCTRL_SPEAR310
35
17
help
36
-
Supports ST SPEAr310 Machine
18
+
Supports ST SPEAr310 machine configured via the device-tree
37
19
38
20
config MACH_SPEAR320
39
-
bool "SPEAr320"
21
+
bool "SPEAr320 Machine support with Device Tree"
22
+
select PINCTRL_SPEAR320
40
23
help
41
-
Supports ST SPEAr320 Machine
42
-
24
+
Supports ST SPEAr320 machine configured via the device-tree
25
+
endmenu
43
26
endif #ARCH_SPEAR3XX
+1
-12
arch/arm/mach-spear3xx/Makefile
+1
-12
arch/arm/mach-spear3xx/Makefile
···
3
3
#
4
4
5
5
# common files
6
-
obj-y += spear3xx.o
6
+
obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
7
7
8
8
# spear300 specific files
9
9
obj-$(CONFIG_MACH_SPEAR300) += spear300.o
10
10
11
-
# spear300 boards files
12
-
obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
13
-
14
-
15
11
# spear310 specific files
16
12
obj-$(CONFIG_MACH_SPEAR310) += spear310.o
17
13
18
-
# spear310 boards files
19
-
obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
20
-
21
-
22
14
# spear320 specific files
23
15
obj-$(CONFIG_MACH_SPEAR320) += spear320.o
24
-
25
-
# spear320 boards files
26
-
obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
+4
arch/arm/mach-spear3xx/Makefile.boot
+4
arch/arm/mach-spear3xx/Makefile.boot
+5
-169
arch/arm/mach-spear3xx/include/mach/generic.h
+5
-169
arch/arm/mach-spear3xx/include/mach/generic.h
···
14
14
#ifndef __MACH_GENERIC_H
15
15
#define __MACH_GENERIC_H
16
16
17
+
#include <linux/amba/pl08x.h>
17
18
#include <linux/init.h>
18
19
#include <linux/platform_device.h>
19
20
#include <linux/amba/bus.h>
20
21
#include <asm/mach/time.h>
21
22
#include <asm/mach/map.h>
22
-
#include <plat/padmux.h>
23
-
24
-
/* spear3xx declarations */
25
-
/*
26
-
* Each GPT has 2 timer channels
27
-
* Following GPT channels will be used as clock source and clockevent
28
-
*/
29
-
#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
30
-
#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
31
-
#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
32
23
33
24
/* Add spear3xx family device structure declarations here */
34
-
extern struct amba_device spear3xx_gpio_device;
35
-
extern struct amba_device spear3xx_uart_device;
36
25
extern struct sys_timer spear3xx_timer;
26
+
extern struct pl022_ssp_controller pl022_plat_data;
27
+
extern struct pl08x_platform_data pl080_plat_data;
37
28
38
29
/* Add spear3xx family function declarations here */
39
-
void __init spear_setup_timer(void);
30
+
void __init spear_setup_of_timer(void);
40
31
void __init spear3xx_clk_init(void);
41
32
void __init spear3xx_map_io(void);
42
-
void __init spear3xx_init_irq(void);
43
-
void __init spear3xx_init(void);
33
+
void __init spear3xx_dt_init_irq(void);
44
34
45
35
void spear_restart(char, const char *);
46
-
47
-
/* pad mux declarations */
48
-
#define PMX_FIRDA_MASK (1 << 14)
49
-
#define PMX_I2C_MASK (1 << 13)
50
-
#define PMX_SSP_CS_MASK (1 << 12)
51
-
#define PMX_SSP_MASK (1 << 11)
52
-
#define PMX_MII_MASK (1 << 10)
53
-
#define PMX_GPIO_PIN0_MASK (1 << 9)
54
-
#define PMX_GPIO_PIN1_MASK (1 << 8)
55
-
#define PMX_GPIO_PIN2_MASK (1 << 7)
56
-
#define PMX_GPIO_PIN3_MASK (1 << 6)
57
-
#define PMX_GPIO_PIN4_MASK (1 << 5)
58
-
#define PMX_GPIO_PIN5_MASK (1 << 4)
59
-
#define PMX_UART0_MODEM_MASK (1 << 3)
60
-
#define PMX_UART0_MASK (1 << 2)
61
-
#define PMX_TIMER_3_4_MASK (1 << 1)
62
-
#define PMX_TIMER_1_2_MASK (1 << 0)
63
-
64
-
/* pad mux devices */
65
-
extern struct pmx_dev spear3xx_pmx_firda;
66
-
extern struct pmx_dev spear3xx_pmx_i2c;
67
-
extern struct pmx_dev spear3xx_pmx_ssp_cs;
68
-
extern struct pmx_dev spear3xx_pmx_ssp;
69
-
extern struct pmx_dev spear3xx_pmx_mii;
70
-
extern struct pmx_dev spear3xx_pmx_gpio_pin0;
71
-
extern struct pmx_dev spear3xx_pmx_gpio_pin1;
72
-
extern struct pmx_dev spear3xx_pmx_gpio_pin2;
73
-
extern struct pmx_dev spear3xx_pmx_gpio_pin3;
74
-
extern struct pmx_dev spear3xx_pmx_gpio_pin4;
75
-
extern struct pmx_dev spear3xx_pmx_gpio_pin5;
76
-
extern struct pmx_dev spear3xx_pmx_uart0_modem;
77
-
extern struct pmx_dev spear3xx_pmx_uart0;
78
-
extern struct pmx_dev spear3xx_pmx_timer_3_4;
79
-
extern struct pmx_dev spear3xx_pmx_timer_1_2;
80
-
81
-
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
82
-
/* padmux plgpio devices */
83
-
extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
84
-
extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
85
-
extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
86
-
extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
87
-
extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
88
-
extern struct pmx_dev spear3xx_pmx_plgpio_28;
89
-
extern struct pmx_dev spear3xx_pmx_plgpio_29;
90
-
extern struct pmx_dev spear3xx_pmx_plgpio_30;
91
-
extern struct pmx_dev spear3xx_pmx_plgpio_31;
92
-
extern struct pmx_dev spear3xx_pmx_plgpio_32;
93
-
extern struct pmx_dev spear3xx_pmx_plgpio_33;
94
-
extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
95
-
extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
96
-
extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
97
-
extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
98
-
#endif
99
-
100
-
/* spear300 declarations */
101
-
#ifdef CONFIG_MACH_SPEAR300
102
-
/* Add spear300 machine device structure declarations here */
103
-
extern struct amba_device spear300_gpio1_device;
104
-
105
-
/* pad mux modes */
106
-
extern struct pmx_mode spear300_nand_mode;
107
-
extern struct pmx_mode spear300_nor_mode;
108
-
extern struct pmx_mode spear300_photo_frame_mode;
109
-
extern struct pmx_mode spear300_lend_ip_phone_mode;
110
-
extern struct pmx_mode spear300_hend_ip_phone_mode;
111
-
extern struct pmx_mode spear300_lend_wifi_phone_mode;
112
-
extern struct pmx_mode spear300_hend_wifi_phone_mode;
113
-
extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
114
-
extern struct pmx_mode spear300_ata_pabx_i2s_mode;
115
-
extern struct pmx_mode spear300_caml_lcdw_mode;
116
-
extern struct pmx_mode spear300_camu_lcd_mode;
117
-
extern struct pmx_mode spear300_camu_wlcd_mode;
118
-
extern struct pmx_mode spear300_caml_lcd_mode;
119
-
120
-
/* pad mux devices */
121
-
extern struct pmx_dev spear300_pmx_fsmc_2_chips;
122
-
extern struct pmx_dev spear300_pmx_fsmc_4_chips;
123
-
extern struct pmx_dev spear300_pmx_keyboard;
124
-
extern struct pmx_dev spear300_pmx_clcd;
125
-
extern struct pmx_dev spear300_pmx_telecom_gpio;
126
-
extern struct pmx_dev spear300_pmx_telecom_tdm;
127
-
extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
128
-
extern struct pmx_dev spear300_pmx_telecom_camera;
129
-
extern struct pmx_dev spear300_pmx_telecom_dac;
130
-
extern struct pmx_dev spear300_pmx_telecom_i2s;
131
-
extern struct pmx_dev spear300_pmx_telecom_boot_pins;
132
-
extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
133
-
extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
134
-
extern struct pmx_dev spear300_pmx_gpio1;
135
-
136
-
/* Add spear300 machine function declarations here */
137
-
void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
138
-
u8 pmx_dev_count);
139
-
140
-
#endif /* CONFIG_MACH_SPEAR300 */
141
-
142
-
/* spear310 declarations */
143
-
#ifdef CONFIG_MACH_SPEAR310
144
-
/* Add spear310 machine device structure declarations here */
145
-
146
-
/* pad mux devices */
147
-
extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
148
-
extern struct pmx_dev spear310_pmx_emi_cs_2_3;
149
-
extern struct pmx_dev spear310_pmx_uart1;
150
-
extern struct pmx_dev spear310_pmx_uart2;
151
-
extern struct pmx_dev spear310_pmx_uart3_4_5;
152
-
extern struct pmx_dev spear310_pmx_fsmc;
153
-
extern struct pmx_dev spear310_pmx_rs485_0_1;
154
-
extern struct pmx_dev spear310_pmx_tdm0;
155
-
156
-
/* Add spear310 machine function declarations here */
157
-
void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
158
-
u8 pmx_dev_count);
159
-
#endif /* CONFIG_MACH_SPEAR310 */
160
-
161
-
/* spear320 declarations */
162
-
#ifdef CONFIG_MACH_SPEAR320
163
-
/* Add spear320 machine device structure declarations here */
164
-
165
-
/* pad mux modes */
166
-
extern struct pmx_mode spear320_auto_net_smii_mode;
167
-
extern struct pmx_mode spear320_auto_net_mii_mode;
168
-
extern struct pmx_mode spear320_auto_exp_mode;
169
-
extern struct pmx_mode spear320_small_printers_mode;
170
-
171
-
/* pad mux devices */
172
-
extern struct pmx_dev spear320_pmx_clcd;
173
-
extern struct pmx_dev spear320_pmx_emi;
174
-
extern struct pmx_dev spear320_pmx_fsmc;
175
-
extern struct pmx_dev spear320_pmx_spp;
176
-
extern struct pmx_dev spear320_pmx_sdhci;
177
-
extern struct pmx_dev spear320_pmx_i2s;
178
-
extern struct pmx_dev spear320_pmx_uart1;
179
-
extern struct pmx_dev spear320_pmx_uart1_modem;
180
-
extern struct pmx_dev spear320_pmx_uart2;
181
-
extern struct pmx_dev spear320_pmx_touchscreen;
182
-
extern struct pmx_dev spear320_pmx_can;
183
-
extern struct pmx_dev spear320_pmx_sdhci_led;
184
-
extern struct pmx_dev spear320_pmx_pwm0;
185
-
extern struct pmx_dev spear320_pmx_pwm1;
186
-
extern struct pmx_dev spear320_pmx_pwm2;
187
-
extern struct pmx_dev spear320_pmx_pwm3;
188
-
extern struct pmx_dev spear320_pmx_ssp1;
189
-
extern struct pmx_dev spear320_pmx_ssp2;
190
-
extern struct pmx_dev spear320_pmx_mii1;
191
-
extern struct pmx_dev spear320_pmx_smii0;
192
-
extern struct pmx_dev spear320_pmx_smii1;
193
-
extern struct pmx_dev spear320_pmx_i2c1;
194
-
195
-
/* Add spear320 machine function declarations here */
196
-
void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
197
-
u8 pmx_dev_count);
198
-
199
-
#endif /* CONFIG_MACH_SPEAR320 */
200
36
201
37
#endif /* __MACH_GENERIC_H */
+1
-23
arch/arm/mach-spear3xx/include/mach/hardware.h
+1
-23
arch/arm/mach-spear3xx/include/mach/hardware.h
···
1
-
/*
2
-
* arch/arm/mach-spear3xx/include/mach/hardware.h
3
-
*
4
-
* Hardware definitions for SPEAr3xx machine family
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#ifndef __MACH_HARDWARE_H
15
-
#define __MACH_HARDWARE_H
16
-
17
-
#include <plat/hardware.h>
18
-
#include <mach/spear.h>
19
-
20
-
/* Vitual to physical translation of statically mapped space */
21
-
#define IO_ADDRESS(x) (x | 0xF0000000)
22
-
23
-
#endif /* __MACH_HARDWARE_H */
1
+
/* empty */
+2
-129
arch/arm/mach-spear3xx/include/mach/irqs.h
+2
-129
arch/arm/mach-spear3xx/include/mach/irqs.h
···
14
14
#ifndef __MACH_IRQS_H
15
15
#define __MACH_IRQS_H
16
16
17
-
/* SPEAr3xx IRQ definitions */
18
-
#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
17
+
/* FIXME: probe all these from DT */
19
18
#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
20
-
#define SPEAR3XX_IRQ_CPU_GPT1_1 2
21
-
#define SPEAR3XX_IRQ_CPU_GPT1_2 3
22
-
#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
23
-
#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
24
-
#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
25
-
#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
26
-
#define SPEAR3XX_IRQ_BASIC_DMA 8
27
-
#define SPEAR3XX_IRQ_BASIC_SMI 9
28
-
#define SPEAR3XX_IRQ_BASIC_RTC 10
29
-
#define SPEAR3XX_IRQ_BASIC_GPIO 11
30
-
#define SPEAR3XX_IRQ_BASIC_WDT 12
31
-
#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
32
-
#define SPEAR3XX_IRQ_SYS_ERROR 14
33
-
#define SPEAR3XX_IRQ_WAKEUP_RCV 15
34
-
#define SPEAR3XX_IRQ_JPEG 16
35
-
#define SPEAR3XX_IRQ_IRDA 17
36
-
#define SPEAR3XX_IRQ_ADC 18
37
-
#define SPEAR3XX_IRQ_UART 19
38
-
#define SPEAR3XX_IRQ_SSP 20
39
-
#define SPEAR3XX_IRQ_I2C 21
40
-
#define SPEAR3XX_IRQ_MAC_1 22
41
-
#define SPEAR3XX_IRQ_MAC_2 23
42
-
#define SPEAR3XX_IRQ_USB_DEV 24
43
-
#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
44
-
#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
45
-
#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
46
-
#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
47
19
#define SPEAR3XX_IRQ_GEN_RAS_1 28
48
20
#define SPEAR3XX_IRQ_GEN_RAS_2 29
49
21
#define SPEAR3XX_IRQ_GEN_RAS_3 30
50
-
#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
51
22
#define SPEAR3XX_IRQ_VIC_END 32
52
-
53
23
#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
54
24
55
-
/* SPEAr300 Virtual irq definitions */
56
-
/* IRQs sharing IRQ_GEN_RAS_1 */
57
-
#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
58
-
#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
59
-
#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
60
-
#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
61
-
#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
62
-
#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
63
-
#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
64
-
#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
65
-
#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
66
-
67
-
/* IRQs sharing IRQ_GEN_RAS_3 */
68
-
#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
69
-
70
-
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
71
-
#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
72
-
73
-
/* SPEAr310 Virtual irq definitions */
74
-
/* IRQs sharing IRQ_GEN_RAS_1 */
75
-
#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
76
-
#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
77
-
#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
78
-
#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
79
-
#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
80
-
#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
81
-
#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
82
-
#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
83
-
84
-
/* IRQs sharing IRQ_GEN_RAS_2 */
85
-
#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
86
-
#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
87
-
#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
88
-
#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
89
-
#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
90
-
91
-
/* IRQs sharing IRQ_GEN_RAS_3 */
92
-
#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
93
-
#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
94
-
95
-
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
96
-
#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
97
-
#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
98
-
#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
99
-
100
-
/* SPEAr320 Virtual irq definitions */
101
-
/* IRQs sharing IRQ_GEN_RAS_1 */
102
-
#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
103
-
#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
104
-
#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
105
-
106
-
/* IRQs sharing IRQ_GEN_RAS_2 */
107
-
#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
108
-
109
-
/* IRQs sharing IRQ_GEN_RAS_3 */
110
-
#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
111
-
#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
112
-
#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
113
-
114
-
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
115
-
#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
116
-
#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
117
-
#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
118
-
#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
119
-
#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
120
-
#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
121
-
#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
122
-
#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
123
-
#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
124
-
#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
125
-
#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
126
-
127
-
/*
128
-
* GPIO pins virtual irqs
129
-
* Use the lowest number for the GPIO virtual IRQs base on which subarchs
130
-
* we have compiled in
131
-
*/
132
-
#if defined(CONFIG_MACH_SPEAR310)
133
-
#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
134
-
#elif defined(CONFIG_MACH_SPEAR320)
135
-
#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
136
-
#else
137
-
#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
138
-
#endif
139
-
140
-
#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
141
-
#define SPEAR3XX_PLGPIO_COUNT 102
142
-
143
-
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
144
-
#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
145
-
#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
146
-
SPEAR3XX_PLGPIO_COUNT)
147
-
#else
148
-
#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
149
-
#endif
150
-
151
-
#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
152
-
#define NR_IRQS SPEAR3XX_VIRQ_END
25
+
#define NR_IRQS 160
153
26
154
27
#endif /* __MACH_IRQS_H */
+1
-1
arch/arm/mach-spear3xx/include/mach/misc_regs.h
+1
-1
arch/arm/mach-spear3xx/include/mach/misc_regs.h
+6
-40
arch/arm/mach-spear3xx/include/mach/spear.h
+6
-40
arch/arm/mach-spear3xx/include/mach/spear.h
···
15
15
#define __MACH_SPEAR3XX_H
16
16
17
17
#include <asm/memory.h>
18
-
#include <mach/spear300.h>
19
-
#include <mach/spear310.h>
20
-
#include <mach/spear320.h>
21
-
22
-
#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
23
-
24
-
#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
25
18
26
19
/* ICM1 - Low speed connection */
27
20
#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
21
+
#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
28
22
#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
29
-
#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
30
-
#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
23
+
#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
31
24
#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
32
-
#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
33
-
#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
34
-
#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
35
-
#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
36
-
37
-
/* ICM2 - Application Subsystem */
38
-
#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
39
-
#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
40
-
41
-
/* ICM4 - High Speed Connection */
42
-
#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
43
-
#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
44
-
#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
45
-
#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
46
-
#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
47
-
#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
48
-
#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
49
-
#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
50
-
#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
51
25
52
26
/* ML1 - Multi Layer CPU Subsystem */
53
27
#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
54
-
#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
55
-
#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
56
-
#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
28
+
#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
57
29
58
30
/* ICM3 - Basic Subsystem */
59
-
#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
60
31
#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
32
+
#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61
33
#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
62
-
#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
63
-
#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
64
-
#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
65
-
#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
66
-
#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
67
34
#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
68
-
#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
35
+
#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
69
36
#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
70
-
#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
71
-
#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
37
+
#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
72
38
73
39
/* Debug uart for linux, will be used for debug and uncompress messages */
74
40
#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
-54
arch/arm/mach-spear3xx/include/mach/spear300.h
-54
arch/arm/mach-spear3xx/include/mach/spear300.h
···
1
-
/*
2
-
* arch/arm/mach-spear3xx/include/mach/spear300.h
3
-
*
4
-
* SPEAr300 Machine specific definition
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#ifdef CONFIG_MACH_SPEAR300
15
-
16
-
#ifndef __MACH_SPEAR300_H
17
-
#define __MACH_SPEAR300_H
18
-
19
-
/* Base address of various IPs */
20
-
#define SPEAR300_TELECOM_BASE UL(0x50000000)
21
-
22
-
/* Interrupt registers offsets and masks */
23
-
#define SPEAR300_INT_ENB_MASK_REG 0x54
24
-
#define SPEAR300_INT_STS_MASK_REG 0x58
25
-
#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
26
-
#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
27
-
#define SPEAR300_I2S_IRQ_MASK (1 << 2)
28
-
#define SPEAR300_TDM_IRQ_MASK (1 << 3)
29
-
#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
30
-
#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
31
-
#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
32
-
#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
33
-
#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
34
-
35
-
#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
36
-
37
-
#define SPEAR300_CLCD_BASE UL(0x60000000)
38
-
#define SPEAR300_SDHCI_BASE UL(0x70000000)
39
-
#define SPEAR300_NAND_0_BASE UL(0x80000000)
40
-
#define SPEAR300_NAND_1_BASE UL(0x84000000)
41
-
#define SPEAR300_NAND_2_BASE UL(0x88000000)
42
-
#define SPEAR300_NAND_3_BASE UL(0x8c000000)
43
-
#define SPEAR300_NOR_0_BASE UL(0x90000000)
44
-
#define SPEAR300_NOR_1_BASE UL(0x91000000)
45
-
#define SPEAR300_NOR_2_BASE UL(0x92000000)
46
-
#define SPEAR300_NOR_3_BASE UL(0x93000000)
47
-
#define SPEAR300_FSMC_BASE UL(0x94000000)
48
-
#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
49
-
#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
50
-
#define SPEAR300_GPIO_BASE UL(0xA9000000)
51
-
52
-
#endif /* __MACH_SPEAR300_H */
53
-
54
-
#endif /* CONFIG_MACH_SPEAR300 */
-58
arch/arm/mach-spear3xx/include/mach/spear310.h
-58
arch/arm/mach-spear3xx/include/mach/spear310.h
···
1
-
/*
2
-
* arch/arm/mach-spear3xx/include/mach/spear310.h
3
-
*
4
-
* SPEAr310 Machine specific definition
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#ifdef CONFIG_MACH_SPEAR310
15
-
16
-
#ifndef __MACH_SPEAR310_H
17
-
#define __MACH_SPEAR310_H
18
-
19
-
#define SPEAR310_NAND_BASE UL(0x40000000)
20
-
#define SPEAR310_FSMC_BASE UL(0x44000000)
21
-
#define SPEAR310_UART1_BASE UL(0xB2000000)
22
-
#define SPEAR310_UART2_BASE UL(0xB2080000)
23
-
#define SPEAR310_UART3_BASE UL(0xB2100000)
24
-
#define SPEAR310_UART4_BASE UL(0xB2180000)
25
-
#define SPEAR310_UART5_BASE UL(0xB2200000)
26
-
#define SPEAR310_HDLC_BASE UL(0xB2800000)
27
-
#define SPEAR310_RS485_0_BASE UL(0xB3000000)
28
-
#define SPEAR310_RS485_1_BASE UL(0xB3800000)
29
-
#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30
-
31
-
/* Interrupt registers offsets and masks */
32
-
#define SPEAR310_INT_STS_MASK_REG 0x04
33
-
#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
34
-
#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
35
-
#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
36
-
#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
37
-
#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
38
-
#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
39
-
#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
40
-
#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
41
-
#define SPEAR310_UART1_IRQ_MASK (1 << 8)
42
-
#define SPEAR310_UART2_IRQ_MASK (1 << 9)
43
-
#define SPEAR310_UART3_IRQ_MASK (1 << 10)
44
-
#define SPEAR310_UART4_IRQ_MASK (1 << 11)
45
-
#define SPEAR310_UART5_IRQ_MASK (1 << 12)
46
-
#define SPEAR310_EMI_IRQ_MASK (1 << 13)
47
-
#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
48
-
#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
49
-
#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
50
-
51
-
#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
52
-
#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
53
-
#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
54
-
#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
55
-
56
-
#endif /* __MACH_SPEAR310_H */
57
-
58
-
#endif /* CONFIG_MACH_SPEAR310 */
-67
arch/arm/mach-spear3xx/include/mach/spear320.h
-67
arch/arm/mach-spear3xx/include/mach/spear320.h
···
1
-
/*
2
-
* arch/arm/mach-spear3xx/include/mach/spear320.h
3
-
*
4
-
* SPEAr320 Machine specific definition
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#ifdef CONFIG_MACH_SPEAR320
15
-
16
-
#ifndef __MACH_SPEAR320_H
17
-
#define __MACH_SPEAR320_H
18
-
19
-
#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
20
-
#define SPEAR320_FSMC_BASE UL(0x4C000000)
21
-
#define SPEAR320_NAND_BASE UL(0x50000000)
22
-
#define SPEAR320_I2S_BASE UL(0x60000000)
23
-
#define SPEAR320_SDHCI_BASE UL(0x70000000)
24
-
#define SPEAR320_CLCD_BASE UL(0x90000000)
25
-
#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
26
-
#define SPEAR320_CAN0_BASE UL(0xA1000000)
27
-
#define SPEAR320_CAN1_BASE UL(0xA2000000)
28
-
#define SPEAR320_UART1_BASE UL(0xA3000000)
29
-
#define SPEAR320_UART2_BASE UL(0xA4000000)
30
-
#define SPEAR320_SSP0_BASE UL(0xA5000000)
31
-
#define SPEAR320_SSP1_BASE UL(0xA6000000)
32
-
#define SPEAR320_I2C_BASE UL(0xA7000000)
33
-
#define SPEAR320_PWM_BASE UL(0xA8000000)
34
-
#define SPEAR320_SMII0_BASE UL(0xAA000000)
35
-
#define SPEAR320_SMII1_BASE UL(0xAB000000)
36
-
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
37
-
38
-
/* Interrupt registers offsets and masks */
39
-
#define SPEAR320_INT_STS_MASK_REG 0x04
40
-
#define SPEAR320_INT_CLR_MASK_REG 0x04
41
-
#define SPEAR320_INT_ENB_MASK_REG 0x08
42
-
#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
43
-
#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
44
-
#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
45
-
#define SPEAR320_EMI_IRQ_MASK (1 << 7)
46
-
#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
47
-
#define SPEAR320_SPP_IRQ_MASK (1 << 9)
48
-
#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
49
-
#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
50
-
#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
51
-
#define SPEAR320_UART1_IRQ_MASK (1 << 13)
52
-
#define SPEAR320_UART2_IRQ_MASK (1 << 14)
53
-
#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
54
-
#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
55
-
#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
56
-
#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
57
-
#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
58
-
#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
59
-
#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
60
-
61
-
#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
62
-
#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
63
-
#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
64
-
65
-
#endif /* __MACH_SPEAR320_H */
66
-
67
-
#endif /* CONFIG_MACH_SPEAR320 */
+262
-379
arch/arm/mach-spear3xx/spear300.c
+262
-379
arch/arm/mach-spear3xx/spear300.c
···
3
3
*
4
4
* SPEAr300 machine source file
5
5
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
6
+
* Copyright (C) 2009-2012 ST Microelectronics
7
+
* Viresh Kumar <viresh.kumar@st.com>
8
8
*
9
9
* This file is licensed under the terms of the GNU General Public
10
10
* License version 2. This program is licensed "as is" without any
11
11
* warranty of any kind, whether express or implied.
12
12
*/
13
13
14
-
#include <linux/types.h>
15
-
#include <linux/amba/pl061.h>
16
-
#include <linux/ptrace.h>
17
-
#include <asm/irq.h>
14
+
#define pr_fmt(fmt) "SPEAr300: " fmt
15
+
16
+
#include <linux/amba/pl08x.h>
17
+
#include <linux/of_platform.h>
18
+
#include <asm/hardware/vic.h>
19
+
#include <asm/mach/arch.h>
18
20
#include <plat/shirq.h>
19
21
#include <mach/generic.h>
20
-
#include <mach/hardware.h>
22
+
#include <mach/spear.h>
21
23
22
-
/* pad multiplexing support */
23
-
/* muxing registers */
24
-
#define PAD_MUX_CONFIG_REG 0x00
25
-
#define MODE_CONFIG_REG 0x04
24
+
/* Base address of various IPs */
25
+
#define SPEAR300_TELECOM_BASE UL(0x50000000)
26
26
27
-
/* modes */
28
-
#define NAND_MODE (1 << 0)
29
-
#define NOR_MODE (1 << 1)
30
-
#define PHOTO_FRAME_MODE (1 << 2)
31
-
#define LEND_IP_PHONE_MODE (1 << 3)
32
-
#define HEND_IP_PHONE_MODE (1 << 4)
33
-
#define LEND_WIFI_PHONE_MODE (1 << 5)
34
-
#define HEND_WIFI_PHONE_MODE (1 << 6)
35
-
#define ATA_PABX_WI2S_MODE (1 << 7)
36
-
#define ATA_PABX_I2S_MODE (1 << 8)
37
-
#define CAML_LCDW_MODE (1 << 9)
38
-
#define CAMU_LCD_MODE (1 << 10)
39
-
#define CAMU_WLCD_MODE (1 << 11)
40
-
#define CAML_LCD_MODE (1 << 12)
41
-
#define ALL_MODES 0x1FFF
27
+
/* Interrupt registers offsets and masks */
28
+
#define SPEAR300_INT_ENB_MASK_REG 0x54
29
+
#define SPEAR300_INT_STS_MASK_REG 0x58
30
+
#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
31
+
#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
32
+
#define SPEAR300_I2S_IRQ_MASK (1 << 2)
33
+
#define SPEAR300_TDM_IRQ_MASK (1 << 3)
34
+
#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
35
+
#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
36
+
#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
37
+
#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
38
+
#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
42
39
43
-
struct pmx_mode spear300_nand_mode = {
44
-
.id = NAND_MODE,
45
-
.name = "nand mode",
46
-
.mask = 0x00,
47
-
};
40
+
#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
48
41
49
-
struct pmx_mode spear300_nor_mode = {
50
-
.id = NOR_MODE,
51
-
.name = "nor mode",
52
-
.mask = 0x01,
53
-
};
42
+
#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
54
43
55
-
struct pmx_mode spear300_photo_frame_mode = {
56
-
.id = PHOTO_FRAME_MODE,
57
-
.name = "photo frame mode",
58
-
.mask = 0x02,
59
-
};
60
44
61
-
struct pmx_mode spear300_lend_ip_phone_mode = {
62
-
.id = LEND_IP_PHONE_MODE,
63
-
.name = "lend ip phone mode",
64
-
.mask = 0x03,
65
-
};
45
+
/* SPEAr300 Virtual irq definitions */
46
+
/* IRQs sharing IRQ_GEN_RAS_1 */
47
+
#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
48
+
#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
49
+
#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
50
+
#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
51
+
#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
52
+
#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
53
+
#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
54
+
#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
55
+
#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
66
56
67
-
struct pmx_mode spear300_hend_ip_phone_mode = {
68
-
.id = HEND_IP_PHONE_MODE,
69
-
.name = "hend ip phone mode",
70
-
.mask = 0x04,
71
-
};
57
+
/* IRQs sharing IRQ_GEN_RAS_3 */
58
+
#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
72
59
73
-
struct pmx_mode spear300_lend_wifi_phone_mode = {
74
-
.id = LEND_WIFI_PHONE_MODE,
75
-
.name = "lend wifi phone mode",
76
-
.mask = 0x05,
77
-
};
78
-
79
-
struct pmx_mode spear300_hend_wifi_phone_mode = {
80
-
.id = HEND_WIFI_PHONE_MODE,
81
-
.name = "hend wifi phone mode",
82
-
.mask = 0x06,
83
-
};
84
-
85
-
struct pmx_mode spear300_ata_pabx_wi2s_mode = {
86
-
.id = ATA_PABX_WI2S_MODE,
87
-
.name = "ata pabx wi2s mode",
88
-
.mask = 0x07,
89
-
};
90
-
91
-
struct pmx_mode spear300_ata_pabx_i2s_mode = {
92
-
.id = ATA_PABX_I2S_MODE,
93
-
.name = "ata pabx i2s mode",
94
-
.mask = 0x08,
95
-
};
96
-
97
-
struct pmx_mode spear300_caml_lcdw_mode = {
98
-
.id = CAML_LCDW_MODE,
99
-
.name = "caml lcdw mode",
100
-
.mask = 0x0C,
101
-
};
102
-
103
-
struct pmx_mode spear300_camu_lcd_mode = {
104
-
.id = CAMU_LCD_MODE,
105
-
.name = "camu lcd mode",
106
-
.mask = 0x0D,
107
-
};
108
-
109
-
struct pmx_mode spear300_camu_wlcd_mode = {
110
-
.id = CAMU_WLCD_MODE,
111
-
.name = "camu wlcd mode",
112
-
.mask = 0x0E,
113
-
};
114
-
115
-
struct pmx_mode spear300_caml_lcd_mode = {
116
-
.id = CAML_LCD_MODE,
117
-
.name = "caml lcd mode",
118
-
.mask = 0x0F,
119
-
};
120
-
121
-
/* devices */
122
-
static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
123
-
{
124
-
.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
125
-
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
126
-
.mask = PMX_FIRDA_MASK,
127
-
},
128
-
};
129
-
130
-
struct pmx_dev spear300_pmx_fsmc_2_chips = {
131
-
.name = "fsmc_2_chips",
132
-
.modes = pmx_fsmc_2_chips_modes,
133
-
.mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
134
-
.enb_on_reset = 1,
135
-
};
136
-
137
-
static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
138
-
{
139
-
.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
140
-
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
141
-
.mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
142
-
},
143
-
};
144
-
145
-
struct pmx_dev spear300_pmx_fsmc_4_chips = {
146
-
.name = "fsmc_4_chips",
147
-
.modes = pmx_fsmc_4_chips_modes,
148
-
.mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
149
-
.enb_on_reset = 1,
150
-
};
151
-
152
-
static struct pmx_dev_mode pmx_keyboard_modes[] = {
153
-
{
154
-
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
155
-
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
156
-
CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
157
-
CAML_LCD_MODE,
158
-
.mask = 0x0,
159
-
},
160
-
};
161
-
162
-
struct pmx_dev spear300_pmx_keyboard = {
163
-
.name = "keyboard",
164
-
.modes = pmx_keyboard_modes,
165
-
.mode_count = ARRAY_SIZE(pmx_keyboard_modes),
166
-
.enb_on_reset = 1,
167
-
};
168
-
169
-
static struct pmx_dev_mode pmx_clcd_modes[] = {
170
-
{
171
-
.ids = PHOTO_FRAME_MODE,
172
-
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
173
-
}, {
174
-
.ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
175
-
CAMU_LCD_MODE | CAML_LCD_MODE,
176
-
.mask = PMX_TIMER_3_4_MASK,
177
-
},
178
-
};
179
-
180
-
struct pmx_dev spear300_pmx_clcd = {
181
-
.name = "clcd",
182
-
.modes = pmx_clcd_modes,
183
-
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
184
-
.enb_on_reset = 1,
185
-
};
186
-
187
-
static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
188
-
{
189
-
.ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
190
-
.mask = PMX_MII_MASK,
191
-
}, {
192
-
.ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
193
-
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
194
-
}, {
195
-
.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
196
-
.mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
197
-
}, {
198
-
.ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
199
-
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
200
-
}, {
201
-
.ids = ATA_PABX_WI2S_MODE,
202
-
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
203
-
| PMX_UART0_MODEM_MASK,
204
-
},
205
-
};
206
-
207
-
struct pmx_dev spear300_pmx_telecom_gpio = {
208
-
.name = "telecom_gpio",
209
-
.modes = pmx_telecom_gpio_modes,
210
-
.mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
211
-
.enb_on_reset = 1,
212
-
};
213
-
214
-
static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
215
-
{
216
-
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
217
-
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
218
-
| HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
219
-
| ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
220
-
| CAMU_WLCD_MODE | CAML_LCD_MODE,
221
-
.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
222
-
},
223
-
};
224
-
225
-
struct pmx_dev spear300_pmx_telecom_tdm = {
226
-
.name = "telecom_tdm",
227
-
.modes = pmx_telecom_tdm_modes,
228
-
.mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
229
-
.enb_on_reset = 1,
230
-
};
231
-
232
-
static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
233
-
{
234
-
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
235
-
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
236
-
| ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
237
-
CAML_LCDW_MODE | CAML_LCD_MODE,
238
-
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
239
-
},
240
-
};
241
-
242
-
struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
243
-
.name = "telecom_spi_cs_i2c_clk",
244
-
.modes = pmx_telecom_spi_cs_i2c_clk_modes,
245
-
.mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
246
-
.enb_on_reset = 1,
247
-
};
248
-
249
-
static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
250
-
{
251
-
.ids = CAML_LCDW_MODE | CAML_LCD_MODE,
252
-
.mask = PMX_MII_MASK,
253
-
}, {
254
-
.ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
255
-
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
256
-
},
257
-
};
258
-
259
-
struct pmx_dev spear300_pmx_telecom_camera = {
260
-
.name = "telecom_camera",
261
-
.modes = pmx_telecom_camera_modes,
262
-
.mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
263
-
.enb_on_reset = 1,
264
-
};
265
-
266
-
static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
267
-
{
268
-
.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
269
-
| CAMU_WLCD_MODE | CAML_LCD_MODE,
270
-
.mask = PMX_TIMER_1_2_MASK,
271
-
},
272
-
};
273
-
274
-
struct pmx_dev spear300_pmx_telecom_dac = {
275
-
.name = "telecom_dac",
276
-
.modes = pmx_telecom_dac_modes,
277
-
.mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
278
-
.enb_on_reset = 1,
279
-
};
280
-
281
-
static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
282
-
{
283
-
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
284
-
| LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
285
-
ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
286
-
| CAMU_WLCD_MODE | CAML_LCD_MODE,
287
-
.mask = PMX_UART0_MODEM_MASK,
288
-
},
289
-
};
290
-
291
-
struct pmx_dev spear300_pmx_telecom_i2s = {
292
-
.name = "telecom_i2s",
293
-
.modes = pmx_telecom_i2s_modes,
294
-
.mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
295
-
.enb_on_reset = 1,
296
-
};
297
-
298
-
static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
299
-
{
300
-
.ids = NAND_MODE | NOR_MODE,
301
-
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
302
-
PMX_TIMER_3_4_MASK,
303
-
},
304
-
};
305
-
306
-
struct pmx_dev spear300_pmx_telecom_boot_pins = {
307
-
.name = "telecom_boot_pins",
308
-
.modes = pmx_telecom_boot_pins_modes,
309
-
.mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
310
-
.enb_on_reset = 1,
311
-
};
312
-
313
-
static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
314
-
{
315
-
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
316
-
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
317
-
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
318
-
CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
319
-
ATA_PABX_I2S_MODE,
320
-
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
321
-
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
322
-
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
323
-
},
324
-
};
325
-
326
-
struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
327
-
.name = "telecom_sdhci_4bit",
328
-
.modes = pmx_telecom_sdhci_4bit_modes,
329
-
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
330
-
.enb_on_reset = 1,
331
-
};
332
-
333
-
static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
334
-
{
335
-
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
336
-
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
337
-
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
338
-
CAMU_WLCD_MODE | CAML_LCD_MODE,
339
-
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
340
-
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
341
-
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
342
-
},
343
-
};
344
-
345
-
struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
346
-
.name = "telecom_sdhci_8bit",
347
-
.modes = pmx_telecom_sdhci_8bit_modes,
348
-
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
349
-
.enb_on_reset = 1,
350
-
};
351
-
352
-
static struct pmx_dev_mode pmx_gpio1_modes[] = {
353
-
{
354
-
.ids = PHOTO_FRAME_MODE,
355
-
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
356
-
PMX_TIMER_3_4_MASK,
357
-
},
358
-
};
359
-
360
-
struct pmx_dev spear300_pmx_gpio1 = {
361
-
.name = "arm gpio1",
362
-
.modes = pmx_gpio1_modes,
363
-
.mode_count = ARRAY_SIZE(pmx_gpio1_modes),
364
-
.enb_on_reset = 1,
365
-
};
366
-
367
-
/* pmx driver structure */
368
-
static struct pmx_driver pmx_driver = {
369
-
.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
370
-
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
371
-
};
60
+
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61
+
#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
372
62
373
63
/* spear3xx shared irq */
374
64
static struct shirq_dev_config shirq_ras1_config[] = {
···
113
423
},
114
424
};
115
425
116
-
/* Add spear300 specific devices here */
117
-
/* arm gpio1 device registration */
118
-
static struct pl061_platform_data gpio1_plat_data = {
119
-
.gpio_base = 8,
120
-
.irq_base = SPEAR300_GPIO1_INT_BASE,
426
+
/* DMAC platform data's slave info */
427
+
struct pl08x_channel_data spear300_dma_info[] = {
428
+
{
429
+
.bus_id = "uart0_rx",
430
+
.min_signal = 2,
431
+
.max_signal = 2,
432
+
.muxval = 0,
433
+
.cctl = 0,
434
+
.periph_buses = PL08X_AHB1,
435
+
}, {
436
+
.bus_id = "uart0_tx",
437
+
.min_signal = 3,
438
+
.max_signal = 3,
439
+
.muxval = 0,
440
+
.cctl = 0,
441
+
.periph_buses = PL08X_AHB1,
442
+
}, {
443
+
.bus_id = "ssp0_rx",
444
+
.min_signal = 8,
445
+
.max_signal = 8,
446
+
.muxval = 0,
447
+
.cctl = 0,
448
+
.periph_buses = PL08X_AHB1,
449
+
}, {
450
+
.bus_id = "ssp0_tx",
451
+
.min_signal = 9,
452
+
.max_signal = 9,
453
+
.muxval = 0,
454
+
.cctl = 0,
455
+
.periph_buses = PL08X_AHB1,
456
+
}, {
457
+
.bus_id = "i2c_rx",
458
+
.min_signal = 10,
459
+
.max_signal = 10,
460
+
.muxval = 0,
461
+
.cctl = 0,
462
+
.periph_buses = PL08X_AHB1,
463
+
}, {
464
+
.bus_id = "i2c_tx",
465
+
.min_signal = 11,
466
+
.max_signal = 11,
467
+
.muxval = 0,
468
+
.cctl = 0,
469
+
.periph_buses = PL08X_AHB1,
470
+
}, {
471
+
.bus_id = "irda",
472
+
.min_signal = 12,
473
+
.max_signal = 12,
474
+
.muxval = 0,
475
+
.cctl = 0,
476
+
.periph_buses = PL08X_AHB1,
477
+
}, {
478
+
.bus_id = "adc",
479
+
.min_signal = 13,
480
+
.max_signal = 13,
481
+
.muxval = 0,
482
+
.cctl = 0,
483
+
.periph_buses = PL08X_AHB1,
484
+
}, {
485
+
.bus_id = "to_jpeg",
486
+
.min_signal = 14,
487
+
.max_signal = 14,
488
+
.muxval = 0,
489
+
.cctl = 0,
490
+
.periph_buses = PL08X_AHB1,
491
+
}, {
492
+
.bus_id = "from_jpeg",
493
+
.min_signal = 15,
494
+
.max_signal = 15,
495
+
.muxval = 0,
496
+
.cctl = 0,
497
+
.periph_buses = PL08X_AHB1,
498
+
}, {
499
+
.bus_id = "ras0_rx",
500
+
.min_signal = 0,
501
+
.max_signal = 0,
502
+
.muxval = 1,
503
+
.cctl = 0,
504
+
.periph_buses = PL08X_AHB1,
505
+
}, {
506
+
.bus_id = "ras0_tx",
507
+
.min_signal = 1,
508
+
.max_signal = 1,
509
+
.muxval = 1,
510
+
.cctl = 0,
511
+
.periph_buses = PL08X_AHB1,
512
+
}, {
513
+
.bus_id = "ras1_rx",
514
+
.min_signal = 2,
515
+
.max_signal = 2,
516
+
.muxval = 1,
517
+
.cctl = 0,
518
+
.periph_buses = PL08X_AHB1,
519
+
}, {
520
+
.bus_id = "ras1_tx",
521
+
.min_signal = 3,
522
+
.max_signal = 3,
523
+
.muxval = 1,
524
+
.cctl = 0,
525
+
.periph_buses = PL08X_AHB1,
526
+
}, {
527
+
.bus_id = "ras2_rx",
528
+
.min_signal = 4,
529
+
.max_signal = 4,
530
+
.muxval = 1,
531
+
.cctl = 0,
532
+
.periph_buses = PL08X_AHB1,
533
+
}, {
534
+
.bus_id = "ras2_tx",
535
+
.min_signal = 5,
536
+
.max_signal = 5,
537
+
.muxval = 1,
538
+
.cctl = 0,
539
+
.periph_buses = PL08X_AHB1,
540
+
}, {
541
+
.bus_id = "ras3_rx",
542
+
.min_signal = 6,
543
+
.max_signal = 6,
544
+
.muxval = 1,
545
+
.cctl = 0,
546
+
.periph_buses = PL08X_AHB1,
547
+
}, {
548
+
.bus_id = "ras3_tx",
549
+
.min_signal = 7,
550
+
.max_signal = 7,
551
+
.muxval = 1,
552
+
.cctl = 0,
553
+
.periph_buses = PL08X_AHB1,
554
+
}, {
555
+
.bus_id = "ras4_rx",
556
+
.min_signal = 8,
557
+
.max_signal = 8,
558
+
.muxval = 1,
559
+
.cctl = 0,
560
+
.periph_buses = PL08X_AHB1,
561
+
}, {
562
+
.bus_id = "ras4_tx",
563
+
.min_signal = 9,
564
+
.max_signal = 9,
565
+
.muxval = 1,
566
+
.cctl = 0,
567
+
.periph_buses = PL08X_AHB1,
568
+
}, {
569
+
.bus_id = "ras5_rx",
570
+
.min_signal = 10,
571
+
.max_signal = 10,
572
+
.muxval = 1,
573
+
.cctl = 0,
574
+
.periph_buses = PL08X_AHB1,
575
+
}, {
576
+
.bus_id = "ras5_tx",
577
+
.min_signal = 11,
578
+
.max_signal = 11,
579
+
.muxval = 1,
580
+
.cctl = 0,
581
+
.periph_buses = PL08X_AHB1,
582
+
}, {
583
+
.bus_id = "ras6_rx",
584
+
.min_signal = 12,
585
+
.max_signal = 12,
586
+
.muxval = 1,
587
+
.cctl = 0,
588
+
.periph_buses = PL08X_AHB1,
589
+
}, {
590
+
.bus_id = "ras6_tx",
591
+
.min_signal = 13,
592
+
.max_signal = 13,
593
+
.muxval = 1,
594
+
.cctl = 0,
595
+
.periph_buses = PL08X_AHB1,
596
+
}, {
597
+
.bus_id = "ras7_rx",
598
+
.min_signal = 14,
599
+
.max_signal = 14,
600
+
.muxval = 1,
601
+
.cctl = 0,
602
+
.periph_buses = PL08X_AHB1,
603
+
}, {
604
+
.bus_id = "ras7_tx",
605
+
.min_signal = 15,
606
+
.max_signal = 15,
607
+
.muxval = 1,
608
+
.cctl = 0,
609
+
.periph_buses = PL08X_AHB1,
610
+
},
121
611
};
122
612
123
-
AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
124
-
{SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
613
+
/* Add SPEAr300 auxdata to pass platform data */
614
+
static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
615
+
OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
616
+
&pl022_plat_data),
617
+
OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
618
+
&pl080_plat_data),
619
+
{}
620
+
};
125
621
126
-
/* spear300 routines */
127
-
void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
128
-
u8 pmx_dev_count)
622
+
static void __init spear300_dt_init(void)
129
623
{
130
-
int ret = 0;
624
+
int ret;
131
625
132
-
/* call spear3xx family common init function */
133
-
spear3xx_init();
626
+
pl080_plat_data.slave_channels = spear300_dma_info;
627
+
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
628
+
629
+
of_platform_populate(NULL, of_default_bus_match_table,
630
+
spear300_auxdata_lookup, NULL);
134
631
135
632
/* shared irq registration */
136
633
shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
137
634
if (shirq_ras1.regs.base) {
138
635
ret = spear_shirq_register(&shirq_ras1);
139
636
if (ret)
140
-
printk(KERN_ERR "Error registering Shared IRQ\n");
141
-
}
142
-
143
-
/* pmx initialization */
144
-
pmx_driver.mode = pmx_mode;
145
-
pmx_driver.devs = pmx_devs;
146
-
pmx_driver.devs_count = pmx_dev_count;
147
-
148
-
pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
149
-
if (pmx_driver.base) {
150
-
ret = pmx_register(&pmx_driver);
151
-
if (ret)
152
-
printk(KERN_ERR "padmux: registration failed. err no"
153
-
": %d\n", ret);
154
-
/* Free Mapping, device selection already done */
155
-
iounmap(pmx_driver.base);
637
+
pr_err("Error registering Shared IRQ\n");
156
638
}
157
639
}
640
+
641
+
static const char * const spear300_dt_board_compat[] = {
642
+
"st,spear300",
643
+
"st,spear300-evb",
644
+
NULL,
645
+
};
646
+
647
+
static void __init spear300_map_io(void)
648
+
{
649
+
spear3xx_map_io();
650
+
}
651
+
652
+
DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
653
+
.map_io = spear300_map_io,
654
+
.init_irq = spear3xx_dt_init_irq,
655
+
.handle_irq = vic_handle_irq,
656
+
.timer = &spear3xx_timer,
657
+
.init_machine = spear300_dt_init,
658
+
.restart = spear_restart,
659
+
.dt_compat = spear300_dt_board_compat,
660
+
MACHINE_END
-75
arch/arm/mach-spear3xx/spear300_evb.c
-75
arch/arm/mach-spear3xx/spear300_evb.c
···
1
-
/*
2
-
* arch/arm/mach-spear3xx/spear300_evb.c
3
-
*
4
-
* SPEAr300 evaluation board source file
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#include <asm/hardware/vic.h>
15
-
#include <asm/mach/arch.h>
16
-
#include <asm/mach-types.h>
17
-
#include <mach/generic.h>
18
-
#include <mach/hardware.h>
19
-
20
-
/* padmux devices to enable */
21
-
static struct pmx_dev *pmx_devs[] = {
22
-
/* spear3xx specific devices */
23
-
&spear3xx_pmx_i2c,
24
-
&spear3xx_pmx_ssp_cs,
25
-
&spear3xx_pmx_ssp,
26
-
&spear3xx_pmx_mii,
27
-
&spear3xx_pmx_uart0,
28
-
29
-
/* spear300 specific devices */
30
-
&spear300_pmx_fsmc_2_chips,
31
-
&spear300_pmx_clcd,
32
-
&spear300_pmx_telecom_sdhci_4bit,
33
-
&spear300_pmx_gpio1,
34
-
};
35
-
36
-
static struct amba_device *amba_devs[] __initdata = {
37
-
/* spear3xx specific devices */
38
-
&spear3xx_gpio_device,
39
-
&spear3xx_uart_device,
40
-
41
-
/* spear300 specific devices */
42
-
&spear300_gpio1_device,
43
-
};
44
-
45
-
static struct platform_device *plat_devs[] __initdata = {
46
-
/* spear3xx specific devices */
47
-
48
-
/* spear300 specific devices */
49
-
};
50
-
51
-
static void __init spear300_evb_init(void)
52
-
{
53
-
unsigned int i;
54
-
55
-
/* call spear300 machine init function */
56
-
spear300_init(&spear300_photo_frame_mode, pmx_devs,
57
-
ARRAY_SIZE(pmx_devs));
58
-
59
-
/* Add Platform Devices */
60
-
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
61
-
62
-
/* Add Amba Devices */
63
-
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
64
-
amba_device_register(amba_devs[i], &iomem_resource);
65
-
}
66
-
67
-
MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
68
-
.atag_offset = 0x100,
69
-
.map_io = spear3xx_map_io,
70
-
.init_irq = spear3xx_init_irq,
71
-
.handle_irq = vic_handle_irq,
72
-
.timer = &spear3xx_timer,
73
-
.init_machine = spear300_evb_init,
74
-
.restart = spear_restart,
75
-
MACHINE_END
+324
-141
arch/arm/mach-spear3xx/spear310.c
+324
-141
arch/arm/mach-spear3xx/spear310.c
···
3
3
*
4
4
* SPEAr310 machine source file
5
5
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
6
+
* Copyright (C) 2009-2012 ST Microelectronics
7
+
* Viresh Kumar <viresh.kumar@st.com>
8
8
*
9
9
* This file is licensed under the terms of the GNU General Public
10
10
* License version 2. This program is licensed "as is" without any
11
11
* warranty of any kind, whether express or implied.
12
12
*/
13
13
14
-
#include <linux/ptrace.h>
15
-
#include <asm/irq.h>
14
+
#define pr_fmt(fmt) "SPEAr310: " fmt
15
+
16
+
#include <linux/amba/pl08x.h>
17
+
#include <linux/amba/serial.h>
18
+
#include <linux/of_platform.h>
19
+
#include <asm/hardware/vic.h>
20
+
#include <asm/mach/arch.h>
16
21
#include <plat/shirq.h>
17
22
#include <mach/generic.h>
18
-
#include <mach/hardware.h>
23
+
#include <mach/spear.h>
19
24
20
-
/* pad multiplexing support */
21
-
/* muxing registers */
22
-
#define PAD_MUX_CONFIG_REG 0x08
25
+
#define SPEAR310_UART1_BASE UL(0xB2000000)
26
+
#define SPEAR310_UART2_BASE UL(0xB2080000)
27
+
#define SPEAR310_UART3_BASE UL(0xB2100000)
28
+
#define SPEAR310_UART4_BASE UL(0xB2180000)
29
+
#define SPEAR310_UART5_BASE UL(0xB2200000)
30
+
#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
23
31
24
-
/* devices */
25
-
static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
26
-
{
27
-
.ids = 0x00,
28
-
.mask = PMX_TIMER_3_4_MASK,
29
-
},
30
-
};
32
+
/* Interrupt registers offsets and masks */
33
+
#define SPEAR310_INT_STS_MASK_REG 0x04
34
+
#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
35
+
#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
36
+
#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
37
+
#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
38
+
#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
39
+
#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
40
+
#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
41
+
#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
42
+
#define SPEAR310_UART1_IRQ_MASK (1 << 8)
43
+
#define SPEAR310_UART2_IRQ_MASK (1 << 9)
44
+
#define SPEAR310_UART3_IRQ_MASK (1 << 10)
45
+
#define SPEAR310_UART4_IRQ_MASK (1 << 11)
46
+
#define SPEAR310_UART5_IRQ_MASK (1 << 12)
47
+
#define SPEAR310_EMI_IRQ_MASK (1 << 13)
48
+
#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
49
+
#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
50
+
#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
31
51
32
-
struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
33
-
.name = "emi_cs_0_1_4_5",
34
-
.modes = pmx_emi_cs_0_1_4_5_modes,
35
-
.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
36
-
.enb_on_reset = 1,
37
-
};
52
+
#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
53
+
#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
54
+
#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
55
+
#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
38
56
39
-
static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
40
-
{
41
-
.ids = 0x00,
42
-
.mask = PMX_TIMER_1_2_MASK,
43
-
},
44
-
};
57
+
/* SPEAr310 Virtual irq definitions */
58
+
/* IRQs sharing IRQ_GEN_RAS_1 */
59
+
#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
60
+
#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
61
+
#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
62
+
#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
63
+
#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
64
+
#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
65
+
#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
66
+
#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
45
67
46
-
struct pmx_dev spear310_pmx_emi_cs_2_3 = {
47
-
.name = "emi_cs_2_3",
48
-
.modes = pmx_emi_cs_2_3_modes,
49
-
.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
50
-
.enb_on_reset = 1,
51
-
};
68
+
/* IRQs sharing IRQ_GEN_RAS_2 */
69
+
#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
70
+
#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
71
+
#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
72
+
#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
73
+
#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
52
74
53
-
static struct pmx_dev_mode pmx_uart1_modes[] = {
54
-
{
55
-
.ids = 0x00,
56
-
.mask = PMX_FIRDA_MASK,
57
-
},
58
-
};
75
+
/* IRQs sharing IRQ_GEN_RAS_3 */
76
+
#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
77
+
#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
59
78
60
-
struct pmx_dev spear310_pmx_uart1 = {
61
-
.name = "uart1",
62
-
.modes = pmx_uart1_modes,
63
-
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
64
-
.enb_on_reset = 1,
65
-
};
79
+
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
80
+
#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
81
+
#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
82
+
#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
66
83
67
-
static struct pmx_dev_mode pmx_uart2_modes[] = {
68
-
{
69
-
.ids = 0x00,
70
-
.mask = PMX_TIMER_1_2_MASK,
71
-
},
72
-
};
73
-
74
-
struct pmx_dev spear310_pmx_uart2 = {
75
-
.name = "uart2",
76
-
.modes = pmx_uart2_modes,
77
-
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
78
-
.enb_on_reset = 1,
79
-
};
80
-
81
-
static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
82
-
{
83
-
.ids = 0x00,
84
-
.mask = PMX_UART0_MODEM_MASK,
85
-
},
86
-
};
87
-
88
-
struct pmx_dev spear310_pmx_uart3_4_5 = {
89
-
.name = "uart3_4_5",
90
-
.modes = pmx_uart3_4_5_modes,
91
-
.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
92
-
.enb_on_reset = 1,
93
-
};
94
-
95
-
static struct pmx_dev_mode pmx_fsmc_modes[] = {
96
-
{
97
-
.ids = 0x00,
98
-
.mask = PMX_SSP_CS_MASK,
99
-
},
100
-
};
101
-
102
-
struct pmx_dev spear310_pmx_fsmc = {
103
-
.name = "fsmc",
104
-
.modes = pmx_fsmc_modes,
105
-
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
106
-
.enb_on_reset = 1,
107
-
};
108
-
109
-
static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
110
-
{
111
-
.ids = 0x00,
112
-
.mask = PMX_MII_MASK,
113
-
},
114
-
};
115
-
116
-
struct pmx_dev spear310_pmx_rs485_0_1 = {
117
-
.name = "rs485_0_1",
118
-
.modes = pmx_rs485_0_1_modes,
119
-
.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
120
-
.enb_on_reset = 1,
121
-
};
122
-
123
-
static struct pmx_dev_mode pmx_tdm0_modes[] = {
124
-
{
125
-
.ids = 0x00,
126
-
.mask = PMX_MII_MASK,
127
-
},
128
-
};
129
-
130
-
struct pmx_dev spear310_pmx_tdm0 = {
131
-
.name = "tdm0",
132
-
.modes = pmx_tdm0_modes,
133
-
.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
134
-
.enb_on_reset = 1,
135
-
};
136
-
137
-
/* pmx driver structure */
138
-
static struct pmx_driver pmx_driver = {
139
-
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
140
-
};
141
84
142
85
/* spear3xx shared irq */
143
86
static struct shirq_dev_config shirq_ras1_config[] = {
···
198
255
},
199
256
};
200
257
201
-
/* Add spear310 specific devices here */
258
+
/* DMAC platform data's slave info */
259
+
struct pl08x_channel_data spear310_dma_info[] = {
260
+
{
261
+
.bus_id = "uart0_rx",
262
+
.min_signal = 2,
263
+
.max_signal = 2,
264
+
.muxval = 0,
265
+
.cctl = 0,
266
+
.periph_buses = PL08X_AHB1,
267
+
}, {
268
+
.bus_id = "uart0_tx",
269
+
.min_signal = 3,
270
+
.max_signal = 3,
271
+
.muxval = 0,
272
+
.cctl = 0,
273
+
.periph_buses = PL08X_AHB1,
274
+
}, {
275
+
.bus_id = "ssp0_rx",
276
+
.min_signal = 8,
277
+
.max_signal = 8,
278
+
.muxval = 0,
279
+
.cctl = 0,
280
+
.periph_buses = PL08X_AHB1,
281
+
}, {
282
+
.bus_id = "ssp0_tx",
283
+
.min_signal = 9,
284
+
.max_signal = 9,
285
+
.muxval = 0,
286
+
.cctl = 0,
287
+
.periph_buses = PL08X_AHB1,
288
+
}, {
289
+
.bus_id = "i2c_rx",
290
+
.min_signal = 10,
291
+
.max_signal = 10,
292
+
.muxval = 0,
293
+
.cctl = 0,
294
+
.periph_buses = PL08X_AHB1,
295
+
}, {
296
+
.bus_id = "i2c_tx",
297
+
.min_signal = 11,
298
+
.max_signal = 11,
299
+
.muxval = 0,
300
+
.cctl = 0,
301
+
.periph_buses = PL08X_AHB1,
302
+
}, {
303
+
.bus_id = "irda",
304
+
.min_signal = 12,
305
+
.max_signal = 12,
306
+
.muxval = 0,
307
+
.cctl = 0,
308
+
.periph_buses = PL08X_AHB1,
309
+
}, {
310
+
.bus_id = "adc",
311
+
.min_signal = 13,
312
+
.max_signal = 13,
313
+
.muxval = 0,
314
+
.cctl = 0,
315
+
.periph_buses = PL08X_AHB1,
316
+
}, {
317
+
.bus_id = "to_jpeg",
318
+
.min_signal = 14,
319
+
.max_signal = 14,
320
+
.muxval = 0,
321
+
.cctl = 0,
322
+
.periph_buses = PL08X_AHB1,
323
+
}, {
324
+
.bus_id = "from_jpeg",
325
+
.min_signal = 15,
326
+
.max_signal = 15,
327
+
.muxval = 0,
328
+
.cctl = 0,
329
+
.periph_buses = PL08X_AHB1,
330
+
}, {
331
+
.bus_id = "uart1_rx",
332
+
.min_signal = 0,
333
+
.max_signal = 0,
334
+
.muxval = 1,
335
+
.cctl = 0,
336
+
.periph_buses = PL08X_AHB1,
337
+
}, {
338
+
.bus_id = "uart1_tx",
339
+
.min_signal = 1,
340
+
.max_signal = 1,
341
+
.muxval = 1,
342
+
.cctl = 0,
343
+
.periph_buses = PL08X_AHB1,
344
+
}, {
345
+
.bus_id = "uart2_rx",
346
+
.min_signal = 2,
347
+
.max_signal = 2,
348
+
.muxval = 1,
349
+
.cctl = 0,
350
+
.periph_buses = PL08X_AHB1,
351
+
}, {
352
+
.bus_id = "uart2_tx",
353
+
.min_signal = 3,
354
+
.max_signal = 3,
355
+
.muxval = 1,
356
+
.cctl = 0,
357
+
.periph_buses = PL08X_AHB1,
358
+
}, {
359
+
.bus_id = "uart3_rx",
360
+
.min_signal = 4,
361
+
.max_signal = 4,
362
+
.muxval = 1,
363
+
.cctl = 0,
364
+
.periph_buses = PL08X_AHB1,
365
+
}, {
366
+
.bus_id = "uart3_tx",
367
+
.min_signal = 5,
368
+
.max_signal = 5,
369
+
.muxval = 1,
370
+
.cctl = 0,
371
+
.periph_buses = PL08X_AHB1,
372
+
}, {
373
+
.bus_id = "uart4_rx",
374
+
.min_signal = 6,
375
+
.max_signal = 6,
376
+
.muxval = 1,
377
+
.cctl = 0,
378
+
.periph_buses = PL08X_AHB1,
379
+
}, {
380
+
.bus_id = "uart4_tx",
381
+
.min_signal = 7,
382
+
.max_signal = 7,
383
+
.muxval = 1,
384
+
.cctl = 0,
385
+
.periph_buses = PL08X_AHB1,
386
+
}, {
387
+
.bus_id = "uart5_rx",
388
+
.min_signal = 8,
389
+
.max_signal = 8,
390
+
.muxval = 1,
391
+
.cctl = 0,
392
+
.periph_buses = PL08X_AHB1,
393
+
}, {
394
+
.bus_id = "uart5_tx",
395
+
.min_signal = 9,
396
+
.max_signal = 9,
397
+
.muxval = 1,
398
+
.cctl = 0,
399
+
.periph_buses = PL08X_AHB1,
400
+
}, {
401
+
.bus_id = "ras5_rx",
402
+
.min_signal = 10,
403
+
.max_signal = 10,
404
+
.muxval = 1,
405
+
.cctl = 0,
406
+
.periph_buses = PL08X_AHB1,
407
+
}, {
408
+
.bus_id = "ras5_tx",
409
+
.min_signal = 11,
410
+
.max_signal = 11,
411
+
.muxval = 1,
412
+
.cctl = 0,
413
+
.periph_buses = PL08X_AHB1,
414
+
}, {
415
+
.bus_id = "ras6_rx",
416
+
.min_signal = 12,
417
+
.max_signal = 12,
418
+
.muxval = 1,
419
+
.cctl = 0,
420
+
.periph_buses = PL08X_AHB1,
421
+
}, {
422
+
.bus_id = "ras6_tx",
423
+
.min_signal = 13,
424
+
.max_signal = 13,
425
+
.muxval = 1,
426
+
.cctl = 0,
427
+
.periph_buses = PL08X_AHB1,
428
+
}, {
429
+
.bus_id = "ras7_rx",
430
+
.min_signal = 14,
431
+
.max_signal = 14,
432
+
.muxval = 1,
433
+
.cctl = 0,
434
+
.periph_buses = PL08X_AHB1,
435
+
}, {
436
+
.bus_id = "ras7_tx",
437
+
.min_signal = 15,
438
+
.max_signal = 15,
439
+
.muxval = 1,
440
+
.cctl = 0,
441
+
.periph_buses = PL08X_AHB1,
442
+
},
443
+
};
202
444
203
-
/* spear310 routines */
204
-
void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
205
-
u8 pmx_dev_count)
445
+
/* uart devices plat data */
446
+
static struct amba_pl011_data spear310_uart_data[] = {
447
+
{
448
+
.dma_filter = pl08x_filter_id,
449
+
.dma_tx_param = "uart1_tx",
450
+
.dma_rx_param = "uart1_rx",
451
+
}, {
452
+
.dma_filter = pl08x_filter_id,
453
+
.dma_tx_param = "uart2_tx",
454
+
.dma_rx_param = "uart2_rx",
455
+
}, {
456
+
.dma_filter = pl08x_filter_id,
457
+
.dma_tx_param = "uart3_tx",
458
+
.dma_rx_param = "uart3_rx",
459
+
}, {
460
+
.dma_filter = pl08x_filter_id,
461
+
.dma_tx_param = "uart4_tx",
462
+
.dma_rx_param = "uart4_rx",
463
+
}, {
464
+
.dma_filter = pl08x_filter_id,
465
+
.dma_tx_param = "uart5_tx",
466
+
.dma_rx_param = "uart5_rx",
467
+
},
468
+
};
469
+
470
+
/* Add SPEAr310 auxdata to pass platform data */
471
+
static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
472
+
OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
473
+
&pl022_plat_data),
474
+
OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
475
+
&pl080_plat_data),
476
+
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
477
+
&spear310_uart_data[0]),
478
+
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
479
+
&spear310_uart_data[1]),
480
+
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
481
+
&spear310_uart_data[2]),
482
+
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
483
+
&spear310_uart_data[3]),
484
+
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
485
+
&spear310_uart_data[4]),
486
+
{}
487
+
};
488
+
489
+
static void __init spear310_dt_init(void)
206
490
{
207
491
void __iomem *base;
208
-
int ret = 0;
492
+
int ret;
209
493
210
-
/* call spear3xx family common init function */
211
-
spear3xx_init();
494
+
pl080_plat_data.slave_channels = spear310_dma_info;
495
+
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
496
+
497
+
of_platform_populate(NULL, of_default_bus_match_table,
498
+
spear310_auxdata_lookup, NULL);
212
499
213
500
/* shared irq registration */
214
501
base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
···
447
274
shirq_ras1.regs.base = base;
448
275
ret = spear_shirq_register(&shirq_ras1);
449
276
if (ret)
450
-
printk(KERN_ERR "Error registering Shared IRQ 1\n");
277
+
pr_err("Error registering Shared IRQ 1\n");
451
278
452
279
/* shirq 2 */
453
280
shirq_ras2.regs.base = base;
454
281
ret = spear_shirq_register(&shirq_ras2);
455
282
if (ret)
456
-
printk(KERN_ERR "Error registering Shared IRQ 2\n");
283
+
pr_err("Error registering Shared IRQ 2\n");
457
284
458
285
/* shirq 3 */
459
286
shirq_ras3.regs.base = base;
460
287
ret = spear_shirq_register(&shirq_ras3);
461
288
if (ret)
462
-
printk(KERN_ERR "Error registering Shared IRQ 3\n");
289
+
pr_err("Error registering Shared IRQ 3\n");
463
290
464
291
/* shirq 4 */
465
292
shirq_intrcomm_ras.regs.base = base;
466
293
ret = spear_shirq_register(&shirq_intrcomm_ras);
467
294
if (ret)
468
-
printk(KERN_ERR "Error registering Shared IRQ 4\n");
295
+
pr_err("Error registering Shared IRQ 4\n");
469
296
}
470
-
471
-
/* pmx initialization */
472
-
pmx_driver.base = base;
473
-
pmx_driver.mode = pmx_mode;
474
-
pmx_driver.devs = pmx_devs;
475
-
pmx_driver.devs_count = pmx_dev_count;
476
-
477
-
ret = pmx_register(&pmx_driver);
478
-
if (ret)
479
-
printk(KERN_ERR "padmux: registration failed. err no: %d\n",
480
-
ret);
481
297
}
298
+
299
+
static const char * const spear310_dt_board_compat[] = {
300
+
"st,spear310",
301
+
"st,spear310-evb",
302
+
NULL,
303
+
};
304
+
305
+
static void __init spear310_map_io(void)
306
+
{
307
+
spear3xx_map_io();
308
+
}
309
+
310
+
DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
311
+
.map_io = spear310_map_io,
312
+
.init_irq = spear3xx_dt_init_irq,
313
+
.handle_irq = vic_handle_irq,
314
+
.timer = &spear3xx_timer,
315
+
.init_machine = spear310_dt_init,
316
+
.restart = spear_restart,
317
+
.dt_compat = spear310_dt_board_compat,
318
+
MACHINE_END
-81
arch/arm/mach-spear3xx/spear310_evb.c
-81
arch/arm/mach-spear3xx/spear310_evb.c
···
1
-
/*
2
-
* arch/arm/mach-spear3xx/spear310_evb.c
3
-
*
4
-
* SPEAr310 evaluation board source file
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#include <asm/hardware/vic.h>
15
-
#include <asm/mach/arch.h>
16
-
#include <asm/mach-types.h>
17
-
#include <mach/generic.h>
18
-
#include <mach/hardware.h>
19
-
20
-
/* padmux devices to enable */
21
-
static struct pmx_dev *pmx_devs[] = {
22
-
/* spear3xx specific devices */
23
-
&spear3xx_pmx_i2c,
24
-
&spear3xx_pmx_ssp,
25
-
&spear3xx_pmx_gpio_pin0,
26
-
&spear3xx_pmx_gpio_pin1,
27
-
&spear3xx_pmx_gpio_pin2,
28
-
&spear3xx_pmx_gpio_pin3,
29
-
&spear3xx_pmx_gpio_pin4,
30
-
&spear3xx_pmx_gpio_pin5,
31
-
&spear3xx_pmx_uart0,
32
-
33
-
/* spear310 specific devices */
34
-
&spear310_pmx_emi_cs_0_1_4_5,
35
-
&spear310_pmx_emi_cs_2_3,
36
-
&spear310_pmx_uart1,
37
-
&spear310_pmx_uart2,
38
-
&spear310_pmx_uart3_4_5,
39
-
&spear310_pmx_fsmc,
40
-
&spear310_pmx_rs485_0_1,
41
-
&spear310_pmx_tdm0,
42
-
};
43
-
44
-
static struct amba_device *amba_devs[] __initdata = {
45
-
/* spear3xx specific devices */
46
-
&spear3xx_gpio_device,
47
-
&spear3xx_uart_device,
48
-
49
-
/* spear310 specific devices */
50
-
};
51
-
52
-
static struct platform_device *plat_devs[] __initdata = {
53
-
/* spear3xx specific devices */
54
-
55
-
/* spear310 specific devices */
56
-
};
57
-
58
-
static void __init spear310_evb_init(void)
59
-
{
60
-
unsigned int i;
61
-
62
-
/* call spear310 machine init function */
63
-
spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
64
-
65
-
/* Add Platform Devices */
66
-
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
67
-
68
-
/* Add Amba Devices */
69
-
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
70
-
amba_device_register(amba_devs[i], &iomem_resource);
71
-
}
72
-
73
-
MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
74
-
.atag_offset = 0x100,
75
-
.map_io = spear3xx_map_io,
76
-
.init_irq = spear3xx_init_irq,
77
-
.handle_irq = vic_handle_irq,
78
-
.timer = &spear3xx_timer,
79
-
.init_machine = spear310_evb_init,
80
-
.restart = spear_restart,
81
-
MACHINE_END
+336
-386
arch/arm/mach-spear3xx/spear320.c
+336
-386
arch/arm/mach-spear3xx/spear320.c
···
3
3
*
4
4
* SPEAr320 machine source file
5
5
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
6
+
* Copyright (C) 2009-2012 ST Microelectronics
7
+
* Viresh Kumar <viresh.kumar@st.com>
8
8
*
9
9
* This file is licensed under the terms of the GNU General Public
10
10
* License version 2. This program is licensed "as is" without any
11
11
* warranty of any kind, whether express or implied.
12
12
*/
13
13
14
-
#include <linux/ptrace.h>
15
-
#include <asm/irq.h>
14
+
#define pr_fmt(fmt) "SPEAr320: " fmt
15
+
16
+
#include <linux/amba/pl022.h>
17
+
#include <linux/amba/pl08x.h>
18
+
#include <linux/amba/serial.h>
19
+
#include <linux/of_platform.h>
20
+
#include <asm/hardware/vic.h>
21
+
#include <asm/mach/arch.h>
16
22
#include <plat/shirq.h>
17
23
#include <mach/generic.h>
18
-
#include <mach/hardware.h>
19
24
#include <mach/spear.h>
20
25
21
-
/* pad multiplexing support */
22
-
/* muxing registers */
23
-
#define PAD_MUX_CONFIG_REG 0x0C
24
-
#define MODE_CONFIG_REG 0x10
26
+
#define SPEAR320_UART1_BASE UL(0xA3000000)
27
+
#define SPEAR320_UART2_BASE UL(0xA4000000)
28
+
#define SPEAR320_SSP0_BASE UL(0xA5000000)
29
+
#define SPEAR320_SSP1_BASE UL(0xA6000000)
25
30
26
-
/* modes */
27
-
#define AUTO_NET_SMII_MODE (1 << 0)
28
-
#define AUTO_NET_MII_MODE (1 << 1)
29
-
#define AUTO_EXP_MODE (1 << 2)
30
-
#define SMALL_PRINTERS_MODE (1 << 3)
31
-
#define ALL_MODES 0xF
31
+
/* Interrupt registers offsets and masks */
32
+
#define SPEAR320_INT_STS_MASK_REG 0x04
33
+
#define SPEAR320_INT_CLR_MASK_REG 0x04
34
+
#define SPEAR320_INT_ENB_MASK_REG 0x08
35
+
#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
36
+
#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
37
+
#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
38
+
#define SPEAR320_EMI_IRQ_MASK (1 << 7)
39
+
#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
40
+
#define SPEAR320_SPP_IRQ_MASK (1 << 9)
41
+
#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
42
+
#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
43
+
#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
44
+
#define SPEAR320_UART1_IRQ_MASK (1 << 13)
45
+
#define SPEAR320_UART2_IRQ_MASK (1 << 14)
46
+
#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
47
+
#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
48
+
#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
49
+
#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
50
+
#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
51
+
#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
52
+
#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
32
53
33
-
struct pmx_mode spear320_auto_net_smii_mode = {
34
-
.id = AUTO_NET_SMII_MODE,
35
-
.name = "Automation Networking SMII Mode",
36
-
.mask = 0x00,
37
-
};
54
+
#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
55
+
#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
56
+
#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
38
57
39
-
struct pmx_mode spear320_auto_net_mii_mode = {
40
-
.id = AUTO_NET_MII_MODE,
41
-
.name = "Automation Networking MII Mode",
42
-
.mask = 0x01,
43
-
};
58
+
/* SPEAr320 Virtual irq definitions */
59
+
/* IRQs sharing IRQ_GEN_RAS_1 */
60
+
#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
61
+
#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
62
+
#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
44
63
45
-
struct pmx_mode spear320_auto_exp_mode = {
46
-
.id = AUTO_EXP_MODE,
47
-
.name = "Automation Expanded Mode",
48
-
.mask = 0x02,
49
-
};
64
+
/* IRQs sharing IRQ_GEN_RAS_2 */
65
+
#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
50
66
51
-
struct pmx_mode spear320_small_printers_mode = {
52
-
.id = SMALL_PRINTERS_MODE,
53
-
.name = "Small Printers Mode",
54
-
.mask = 0x03,
55
-
};
67
+
/* IRQs sharing IRQ_GEN_RAS_3 */
68
+
#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
69
+
#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
70
+
#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
56
71
57
-
/* devices */
58
-
static struct pmx_dev_mode pmx_clcd_modes[] = {
59
-
{
60
-
.ids = AUTO_NET_SMII_MODE,
61
-
.mask = 0x0,
62
-
},
63
-
};
64
-
65
-
struct pmx_dev spear320_pmx_clcd = {
66
-
.name = "clcd",
67
-
.modes = pmx_clcd_modes,
68
-
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
69
-
.enb_on_reset = 1,
70
-
};
71
-
72
-
static struct pmx_dev_mode pmx_emi_modes[] = {
73
-
{
74
-
.ids = AUTO_EXP_MODE,
75
-
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
76
-
},
77
-
};
78
-
79
-
struct pmx_dev spear320_pmx_emi = {
80
-
.name = "emi",
81
-
.modes = pmx_emi_modes,
82
-
.mode_count = ARRAY_SIZE(pmx_emi_modes),
83
-
.enb_on_reset = 1,
84
-
};
85
-
86
-
static struct pmx_dev_mode pmx_fsmc_modes[] = {
87
-
{
88
-
.ids = ALL_MODES,
89
-
.mask = 0x0,
90
-
},
91
-
};
92
-
93
-
struct pmx_dev spear320_pmx_fsmc = {
94
-
.name = "fsmc",
95
-
.modes = pmx_fsmc_modes,
96
-
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
97
-
.enb_on_reset = 1,
98
-
};
99
-
100
-
static struct pmx_dev_mode pmx_spp_modes[] = {
101
-
{
102
-
.ids = SMALL_PRINTERS_MODE,
103
-
.mask = 0x0,
104
-
},
105
-
};
106
-
107
-
struct pmx_dev spear320_pmx_spp = {
108
-
.name = "spp",
109
-
.modes = pmx_spp_modes,
110
-
.mode_count = ARRAY_SIZE(pmx_spp_modes),
111
-
.enb_on_reset = 1,
112
-
};
113
-
114
-
static struct pmx_dev_mode pmx_sdhci_modes[] = {
115
-
{
116
-
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
117
-
SMALL_PRINTERS_MODE,
118
-
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
119
-
},
120
-
};
121
-
122
-
struct pmx_dev spear320_pmx_sdhci = {
123
-
.name = "sdhci",
124
-
.modes = pmx_sdhci_modes,
125
-
.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
126
-
.enb_on_reset = 1,
127
-
};
128
-
129
-
static struct pmx_dev_mode pmx_i2s_modes[] = {
130
-
{
131
-
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
132
-
.mask = PMX_UART0_MODEM_MASK,
133
-
},
134
-
};
135
-
136
-
struct pmx_dev spear320_pmx_i2s = {
137
-
.name = "i2s",
138
-
.modes = pmx_i2s_modes,
139
-
.mode_count = ARRAY_SIZE(pmx_i2s_modes),
140
-
.enb_on_reset = 1,
141
-
};
142
-
143
-
static struct pmx_dev_mode pmx_uart1_modes[] = {
144
-
{
145
-
.ids = ALL_MODES,
146
-
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
147
-
},
148
-
};
149
-
150
-
struct pmx_dev spear320_pmx_uart1 = {
151
-
.name = "uart1",
152
-
.modes = pmx_uart1_modes,
153
-
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
154
-
.enb_on_reset = 1,
155
-
};
156
-
157
-
static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
158
-
{
159
-
.ids = AUTO_EXP_MODE,
160
-
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
161
-
PMX_SSP_CS_MASK,
162
-
}, {
163
-
.ids = SMALL_PRINTERS_MODE,
164
-
.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
165
-
PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
166
-
},
167
-
};
168
-
169
-
struct pmx_dev spear320_pmx_uart1_modem = {
170
-
.name = "uart1_modem",
171
-
.modes = pmx_uart1_modem_modes,
172
-
.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
173
-
.enb_on_reset = 1,
174
-
};
175
-
176
-
static struct pmx_dev_mode pmx_uart2_modes[] = {
177
-
{
178
-
.ids = ALL_MODES,
179
-
.mask = PMX_FIRDA_MASK,
180
-
},
181
-
};
182
-
183
-
struct pmx_dev spear320_pmx_uart2 = {
184
-
.name = "uart2",
185
-
.modes = pmx_uart2_modes,
186
-
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
187
-
.enb_on_reset = 1,
188
-
};
189
-
190
-
static struct pmx_dev_mode pmx_touchscreen_modes[] = {
191
-
{
192
-
.ids = AUTO_NET_SMII_MODE,
193
-
.mask = PMX_SSP_CS_MASK,
194
-
},
195
-
};
196
-
197
-
struct pmx_dev spear320_pmx_touchscreen = {
198
-
.name = "touchscreen",
199
-
.modes = pmx_touchscreen_modes,
200
-
.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
201
-
.enb_on_reset = 1,
202
-
};
203
-
204
-
static struct pmx_dev_mode pmx_can_modes[] = {
205
-
{
206
-
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
207
-
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
208
-
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
209
-
},
210
-
};
211
-
212
-
struct pmx_dev spear320_pmx_can = {
213
-
.name = "can",
214
-
.modes = pmx_can_modes,
215
-
.mode_count = ARRAY_SIZE(pmx_can_modes),
216
-
.enb_on_reset = 1,
217
-
};
218
-
219
-
static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
220
-
{
221
-
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
222
-
.mask = PMX_SSP_CS_MASK,
223
-
},
224
-
};
225
-
226
-
struct pmx_dev spear320_pmx_sdhci_led = {
227
-
.name = "sdhci_led",
228
-
.modes = pmx_sdhci_led_modes,
229
-
.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
230
-
.enb_on_reset = 1,
231
-
};
232
-
233
-
static struct pmx_dev_mode pmx_pwm0_modes[] = {
234
-
{
235
-
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
236
-
.mask = PMX_UART0_MODEM_MASK,
237
-
}, {
238
-
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
239
-
.mask = PMX_MII_MASK,
240
-
},
241
-
};
242
-
243
-
struct pmx_dev spear320_pmx_pwm0 = {
244
-
.name = "pwm0",
245
-
.modes = pmx_pwm0_modes,
246
-
.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
247
-
.enb_on_reset = 1,
248
-
};
249
-
250
-
static struct pmx_dev_mode pmx_pwm1_modes[] = {
251
-
{
252
-
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
253
-
.mask = PMX_UART0_MODEM_MASK,
254
-
}, {
255
-
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
256
-
.mask = PMX_MII_MASK,
257
-
},
258
-
};
259
-
260
-
struct pmx_dev spear320_pmx_pwm1 = {
261
-
.name = "pwm1",
262
-
.modes = pmx_pwm1_modes,
263
-
.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
264
-
.enb_on_reset = 1,
265
-
};
266
-
267
-
static struct pmx_dev_mode pmx_pwm2_modes[] = {
268
-
{
269
-
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
270
-
.mask = PMX_SSP_CS_MASK,
271
-
}, {
272
-
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
273
-
.mask = PMX_MII_MASK,
274
-
},
275
-
};
276
-
277
-
struct pmx_dev spear320_pmx_pwm2 = {
278
-
.name = "pwm2",
279
-
.modes = pmx_pwm2_modes,
280
-
.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
281
-
.enb_on_reset = 1,
282
-
};
283
-
284
-
static struct pmx_dev_mode pmx_pwm3_modes[] = {
285
-
{
286
-
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
287
-
.mask = PMX_MII_MASK,
288
-
},
289
-
};
290
-
291
-
struct pmx_dev spear320_pmx_pwm3 = {
292
-
.name = "pwm3",
293
-
.modes = pmx_pwm3_modes,
294
-
.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
295
-
.enb_on_reset = 1,
296
-
};
297
-
298
-
static struct pmx_dev_mode pmx_ssp1_modes[] = {
299
-
{
300
-
.ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
301
-
.mask = PMX_MII_MASK,
302
-
},
303
-
};
304
-
305
-
struct pmx_dev spear320_pmx_ssp1 = {
306
-
.name = "ssp1",
307
-
.modes = pmx_ssp1_modes,
308
-
.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
309
-
.enb_on_reset = 1,
310
-
};
311
-
312
-
static struct pmx_dev_mode pmx_ssp2_modes[] = {
313
-
{
314
-
.ids = AUTO_NET_SMII_MODE,
315
-
.mask = PMX_MII_MASK,
316
-
},
317
-
};
318
-
319
-
struct pmx_dev spear320_pmx_ssp2 = {
320
-
.name = "ssp2",
321
-
.modes = pmx_ssp2_modes,
322
-
.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
323
-
.enb_on_reset = 1,
324
-
};
325
-
326
-
static struct pmx_dev_mode pmx_mii1_modes[] = {
327
-
{
328
-
.ids = AUTO_NET_MII_MODE,
329
-
.mask = 0x0,
330
-
},
331
-
};
332
-
333
-
struct pmx_dev spear320_pmx_mii1 = {
334
-
.name = "mii1",
335
-
.modes = pmx_mii1_modes,
336
-
.mode_count = ARRAY_SIZE(pmx_mii1_modes),
337
-
.enb_on_reset = 1,
338
-
};
339
-
340
-
static struct pmx_dev_mode pmx_smii0_modes[] = {
341
-
{
342
-
.ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
343
-
.mask = PMX_MII_MASK,
344
-
},
345
-
};
346
-
347
-
struct pmx_dev spear320_pmx_smii0 = {
348
-
.name = "smii0",
349
-
.modes = pmx_smii0_modes,
350
-
.mode_count = ARRAY_SIZE(pmx_smii0_modes),
351
-
.enb_on_reset = 1,
352
-
};
353
-
354
-
static struct pmx_dev_mode pmx_smii1_modes[] = {
355
-
{
356
-
.ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
357
-
.mask = PMX_MII_MASK,
358
-
},
359
-
};
360
-
361
-
struct pmx_dev spear320_pmx_smii1 = {
362
-
.name = "smii1",
363
-
.modes = pmx_smii1_modes,
364
-
.mode_count = ARRAY_SIZE(pmx_smii1_modes),
365
-
.enb_on_reset = 1,
366
-
};
367
-
368
-
static struct pmx_dev_mode pmx_i2c1_modes[] = {
369
-
{
370
-
.ids = AUTO_EXP_MODE,
371
-
.mask = 0x0,
372
-
},
373
-
};
374
-
375
-
struct pmx_dev spear320_pmx_i2c1 = {
376
-
.name = "i2c1",
377
-
.modes = pmx_i2c1_modes,
378
-
.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
379
-
.enb_on_reset = 1,
380
-
};
381
-
382
-
/* pmx driver structure */
383
-
static struct pmx_driver pmx_driver = {
384
-
.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
385
-
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
386
-
};
72
+
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
73
+
#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
74
+
#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
75
+
#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
76
+
#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
77
+
#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
78
+
#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
79
+
#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
80
+
#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
81
+
#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
82
+
#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
83
+
#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
387
84
388
85
/* spear3xx shared irq */
389
86
static struct shirq_dev_config shirq_ras1_config[] = {
···
206
509
},
207
510
};
208
511
209
-
/* Add spear320 specific devices here */
512
+
/* DMAC platform data's slave info */
513
+
struct pl08x_channel_data spear320_dma_info[] = {
514
+
{
515
+
.bus_id = "uart0_rx",
516
+
.min_signal = 2,
517
+
.max_signal = 2,
518
+
.muxval = 0,
519
+
.cctl = 0,
520
+
.periph_buses = PL08X_AHB1,
521
+
}, {
522
+
.bus_id = "uart0_tx",
523
+
.min_signal = 3,
524
+
.max_signal = 3,
525
+
.muxval = 0,
526
+
.cctl = 0,
527
+
.periph_buses = PL08X_AHB1,
528
+
}, {
529
+
.bus_id = "ssp0_rx",
530
+
.min_signal = 8,
531
+
.max_signal = 8,
532
+
.muxval = 0,
533
+
.cctl = 0,
534
+
.periph_buses = PL08X_AHB1,
535
+
}, {
536
+
.bus_id = "ssp0_tx",
537
+
.min_signal = 9,
538
+
.max_signal = 9,
539
+
.muxval = 0,
540
+
.cctl = 0,
541
+
.periph_buses = PL08X_AHB1,
542
+
}, {
543
+
.bus_id = "i2c0_rx",
544
+
.min_signal = 10,
545
+
.max_signal = 10,
546
+
.muxval = 0,
547
+
.cctl = 0,
548
+
.periph_buses = PL08X_AHB1,
549
+
}, {
550
+
.bus_id = "i2c0_tx",
551
+
.min_signal = 11,
552
+
.max_signal = 11,
553
+
.muxval = 0,
554
+
.cctl = 0,
555
+
.periph_buses = PL08X_AHB1,
556
+
}, {
557
+
.bus_id = "irda",
558
+
.min_signal = 12,
559
+
.max_signal = 12,
560
+
.muxval = 0,
561
+
.cctl = 0,
562
+
.periph_buses = PL08X_AHB1,
563
+
}, {
564
+
.bus_id = "adc",
565
+
.min_signal = 13,
566
+
.max_signal = 13,
567
+
.muxval = 0,
568
+
.cctl = 0,
569
+
.periph_buses = PL08X_AHB1,
570
+
}, {
571
+
.bus_id = "to_jpeg",
572
+
.min_signal = 14,
573
+
.max_signal = 14,
574
+
.muxval = 0,
575
+
.cctl = 0,
576
+
.periph_buses = PL08X_AHB1,
577
+
}, {
578
+
.bus_id = "from_jpeg",
579
+
.min_signal = 15,
580
+
.max_signal = 15,
581
+
.muxval = 0,
582
+
.cctl = 0,
583
+
.periph_buses = PL08X_AHB1,
584
+
}, {
585
+
.bus_id = "ssp1_rx",
586
+
.min_signal = 0,
587
+
.max_signal = 0,
588
+
.muxval = 1,
589
+
.cctl = 0,
590
+
.periph_buses = PL08X_AHB2,
591
+
}, {
592
+
.bus_id = "ssp1_tx",
593
+
.min_signal = 1,
594
+
.max_signal = 1,
595
+
.muxval = 1,
596
+
.cctl = 0,
597
+
.periph_buses = PL08X_AHB2,
598
+
}, {
599
+
.bus_id = "ssp2_rx",
600
+
.min_signal = 2,
601
+
.max_signal = 2,
602
+
.muxval = 1,
603
+
.cctl = 0,
604
+
.periph_buses = PL08X_AHB2,
605
+
}, {
606
+
.bus_id = "ssp2_tx",
607
+
.min_signal = 3,
608
+
.max_signal = 3,
609
+
.muxval = 1,
610
+
.cctl = 0,
611
+
.periph_buses = PL08X_AHB2,
612
+
}, {
613
+
.bus_id = "uart1_rx",
614
+
.min_signal = 4,
615
+
.max_signal = 4,
616
+
.muxval = 1,
617
+
.cctl = 0,
618
+
.periph_buses = PL08X_AHB2,
619
+
}, {
620
+
.bus_id = "uart1_tx",
621
+
.min_signal = 5,
622
+
.max_signal = 5,
623
+
.muxval = 1,
624
+
.cctl = 0,
625
+
.periph_buses = PL08X_AHB2,
626
+
}, {
627
+
.bus_id = "uart2_rx",
628
+
.min_signal = 6,
629
+
.max_signal = 6,
630
+
.muxval = 1,
631
+
.cctl = 0,
632
+
.periph_buses = PL08X_AHB2,
633
+
}, {
634
+
.bus_id = "uart2_tx",
635
+
.min_signal = 7,
636
+
.max_signal = 7,
637
+
.muxval = 1,
638
+
.cctl = 0,
639
+
.periph_buses = PL08X_AHB2,
640
+
}, {
641
+
.bus_id = "i2c1_rx",
642
+
.min_signal = 8,
643
+
.max_signal = 8,
644
+
.muxval = 1,
645
+
.cctl = 0,
646
+
.periph_buses = PL08X_AHB2,
647
+
}, {
648
+
.bus_id = "i2c1_tx",
649
+
.min_signal = 9,
650
+
.max_signal = 9,
651
+
.muxval = 1,
652
+
.cctl = 0,
653
+
.periph_buses = PL08X_AHB2,
654
+
}, {
655
+
.bus_id = "i2c2_rx",
656
+
.min_signal = 10,
657
+
.max_signal = 10,
658
+
.muxval = 1,
659
+
.cctl = 0,
660
+
.periph_buses = PL08X_AHB2,
661
+
}, {
662
+
.bus_id = "i2c2_tx",
663
+
.min_signal = 11,
664
+
.max_signal = 11,
665
+
.muxval = 1,
666
+
.cctl = 0,
667
+
.periph_buses = PL08X_AHB2,
668
+
}, {
669
+
.bus_id = "i2s_rx",
670
+
.min_signal = 12,
671
+
.max_signal = 12,
672
+
.muxval = 1,
673
+
.cctl = 0,
674
+
.periph_buses = PL08X_AHB2,
675
+
}, {
676
+
.bus_id = "i2s_tx",
677
+
.min_signal = 13,
678
+
.max_signal = 13,
679
+
.muxval = 1,
680
+
.cctl = 0,
681
+
.periph_buses = PL08X_AHB2,
682
+
}, {
683
+
.bus_id = "rs485_rx",
684
+
.min_signal = 14,
685
+
.max_signal = 14,
686
+
.muxval = 1,
687
+
.cctl = 0,
688
+
.periph_buses = PL08X_AHB2,
689
+
}, {
690
+
.bus_id = "rs485_tx",
691
+
.min_signal = 15,
692
+
.max_signal = 15,
693
+
.muxval = 1,
694
+
.cctl = 0,
695
+
.periph_buses = PL08X_AHB2,
696
+
},
697
+
};
210
698
211
-
/* spear320 routines */
212
-
void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
213
-
u8 pmx_dev_count)
699
+
static struct pl022_ssp_controller spear320_ssp_data[] = {
700
+
{
701
+
.bus_id = 1,
702
+
.enable_dma = 1,
703
+
.dma_filter = pl08x_filter_id,
704
+
.dma_tx_param = "ssp1_tx",
705
+
.dma_rx_param = "ssp1_rx",
706
+
.num_chipselect = 2,
707
+
}, {
708
+
.bus_id = 2,
709
+
.enable_dma = 1,
710
+
.dma_filter = pl08x_filter_id,
711
+
.dma_tx_param = "ssp2_tx",
712
+
.dma_rx_param = "ssp2_rx",
713
+
.num_chipselect = 2,
714
+
}
715
+
};
716
+
717
+
static struct amba_pl011_data spear320_uart_data[] = {
718
+
{
719
+
.dma_filter = pl08x_filter_id,
720
+
.dma_tx_param = "uart1_tx",
721
+
.dma_rx_param = "uart1_rx",
722
+
}, {
723
+
.dma_filter = pl08x_filter_id,
724
+
.dma_tx_param = "uart2_tx",
725
+
.dma_rx_param = "uart2_rx",
726
+
},
727
+
};
728
+
729
+
/* Add SPEAr310 auxdata to pass platform data */
730
+
static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
731
+
OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
732
+
&pl022_plat_data),
733
+
OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
734
+
&pl080_plat_data),
735
+
OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
736
+
&spear320_ssp_data[0]),
737
+
OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
738
+
&spear320_ssp_data[1]),
739
+
OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
740
+
&spear320_uart_data[0]),
741
+
OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
742
+
&spear320_uart_data[1]),
743
+
{}
744
+
};
745
+
746
+
static void __init spear320_dt_init(void)
214
747
{
215
748
void __iomem *base;
216
-
int ret = 0;
749
+
int ret;
217
750
218
-
/* call spear3xx family common init function */
219
-
spear3xx_init();
751
+
pl080_plat_data.slave_channels = spear320_dma_info;
752
+
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
753
+
754
+
of_platform_populate(NULL, of_default_bus_match_table,
755
+
spear320_auxdata_lookup, NULL);
220
756
221
757
/* shared irq registration */
222
758
base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
···
458
528
shirq_ras1.regs.base = base;
459
529
ret = spear_shirq_register(&shirq_ras1);
460
530
if (ret)
461
-
printk(KERN_ERR "Error registering Shared IRQ 1\n");
531
+
pr_err("Error registering Shared IRQ 1\n");
462
532
463
533
/* shirq 3 */
464
534
shirq_ras3.regs.base = base;
465
535
ret = spear_shirq_register(&shirq_ras3);
466
536
if (ret)
467
-
printk(KERN_ERR "Error registering Shared IRQ 3\n");
537
+
pr_err("Error registering Shared IRQ 3\n");
468
538
469
539
/* shirq 4 */
470
540
shirq_intrcomm_ras.regs.base = base;
471
541
ret = spear_shirq_register(&shirq_intrcomm_ras);
472
542
if (ret)
473
-
printk(KERN_ERR "Error registering Shared IRQ 4\n");
543
+
pr_err("Error registering Shared IRQ 4\n");
474
544
}
475
-
476
-
/* pmx initialization */
477
-
pmx_driver.base = base;
478
-
pmx_driver.mode = pmx_mode;
479
-
pmx_driver.devs = pmx_devs;
480
-
pmx_driver.devs_count = pmx_dev_count;
481
-
482
-
ret = pmx_register(&pmx_driver);
483
-
if (ret)
484
-
printk(KERN_ERR "padmux: registration failed. err no: %d\n",
485
-
ret);
486
545
}
546
+
547
+
static const char * const spear320_dt_board_compat[] = {
548
+
"st,spear320",
549
+
"st,spear320-evb",
550
+
NULL,
551
+
};
552
+
553
+
struct map_desc spear320_io_desc[] __initdata = {
554
+
{
555
+
.virtual = VA_SPEAR320_SOC_CONFIG_BASE,
556
+
.pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
557
+
.length = SZ_16M,
558
+
.type = MT_DEVICE
559
+
},
560
+
};
561
+
562
+
static void __init spear320_map_io(void)
563
+
{
564
+
iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
565
+
spear3xx_map_io();
566
+
}
567
+
568
+
DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
569
+
.map_io = spear320_map_io,
570
+
.init_irq = spear3xx_dt_init_irq,
571
+
.handle_irq = vic_handle_irq,
572
+
.timer = &spear3xx_timer,
573
+
.init_machine = spear320_dt_init,
574
+
.restart = spear_restart,
575
+
.dt_compat = spear320_dt_board_compat,
576
+
MACHINE_END
-79
arch/arm/mach-spear3xx/spear320_evb.c
-79
arch/arm/mach-spear3xx/spear320_evb.c
···
1
-
/*
2
-
* arch/arm/mach-spear3xx/spear320_evb.c
3
-
*
4
-
* SPEAr320 evaluation board source file
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#include <asm/hardware/vic.h>
15
-
#include <asm/mach/arch.h>
16
-
#include <asm/mach-types.h>
17
-
#include <mach/generic.h>
18
-
#include <mach/hardware.h>
19
-
20
-
/* padmux devices to enable */
21
-
static struct pmx_dev *pmx_devs[] = {
22
-
/* spear3xx specific devices */
23
-
&spear3xx_pmx_i2c,
24
-
&spear3xx_pmx_ssp,
25
-
&spear3xx_pmx_mii,
26
-
&spear3xx_pmx_uart0,
27
-
28
-
/* spear320 specific devices */
29
-
&spear320_pmx_fsmc,
30
-
&spear320_pmx_sdhci,
31
-
&spear320_pmx_i2s,
32
-
&spear320_pmx_uart1,
33
-
&spear320_pmx_uart2,
34
-
&spear320_pmx_can,
35
-
&spear320_pmx_pwm0,
36
-
&spear320_pmx_pwm1,
37
-
&spear320_pmx_pwm2,
38
-
&spear320_pmx_mii1,
39
-
};
40
-
41
-
static struct amba_device *amba_devs[] __initdata = {
42
-
/* spear3xx specific devices */
43
-
&spear3xx_gpio_device,
44
-
&spear3xx_uart_device,
45
-
46
-
/* spear320 specific devices */
47
-
};
48
-
49
-
static struct platform_device *plat_devs[] __initdata = {
50
-
/* spear3xx specific devices */
51
-
52
-
/* spear320 specific devices */
53
-
};
54
-
55
-
static void __init spear320_evb_init(void)
56
-
{
57
-
unsigned int i;
58
-
59
-
/* call spear320 machine init function */
60
-
spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
61
-
ARRAY_SIZE(pmx_devs));
62
-
63
-
/* Add Platform Devices */
64
-
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
65
-
66
-
/* Add Amba Devices */
67
-
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
68
-
amba_device_register(amba_devs[i], &iomem_resource);
69
-
}
70
-
71
-
MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
72
-
.atag_offset = 0x100,
73
-
.map_io = spear3xx_map_io,
74
-
.init_irq = spear3xx_init_irq,
75
-
.handle_irq = vic_handle_irq,
76
-
.timer = &spear3xx_timer,
77
-
.init_machine = spear320_evb_init,
78
-
.restart = spear_restart,
79
-
MACHINE_END
+69
-480
arch/arm/mach-spear3xx/spear3xx.c
+69
-480
arch/arm/mach-spear3xx/spear3xx.c
···
3
3
*
4
4
* SPEAr3XX machines common source file
5
5
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
6
+
* Copyright (C) 2009-2012 ST Microelectronics
7
+
* Viresh Kumar <viresh.kumar@st.com>
8
8
*
9
9
* This file is licensed under the terms of the GNU General Public
10
10
* License version 2. This program is licensed "as is" without any
11
11
* warranty of any kind, whether express or implied.
12
12
*/
13
13
14
-
#include <linux/types.h>
15
-
#include <linux/amba/pl061.h>
16
-
#include <linux/ptrace.h>
17
-
#include <linux/io.h>
18
-
#include <asm/hardware/vic.h>
19
-
#include <asm/irq.h>
20
-
#include <asm/mach/arch.h>
21
-
#include <mach/generic.h>
22
-
#include <mach/hardware.h>
14
+
#define pr_fmt(fmt) "SPEAr3xx: " fmt
23
15
24
-
/* Add spear3xx machines common devices here */
25
-
/* gpio device registration */
26
-
static struct pl061_platform_data gpio_plat_data = {
27
-
.gpio_base = 0,
28
-
.irq_base = SPEAR3XX_GPIO_INT_BASE,
16
+
#include <linux/amba/pl022.h>
17
+
#include <linux/amba/pl08x.h>
18
+
#include <linux/of_irq.h>
19
+
#include <linux/io.h>
20
+
#include <asm/hardware/pl080.h>
21
+
#include <asm/hardware/vic.h>
22
+
#include <plat/pl080.h>
23
+
#include <mach/generic.h>
24
+
#include <mach/spear.h>
25
+
26
+
/* ssp device registration */
27
+
struct pl022_ssp_controller pl022_plat_data = {
28
+
.bus_id = 0,
29
+
.enable_dma = 1,
30
+
.dma_filter = pl08x_filter_id,
31
+
.dma_tx_param = "ssp0_tx",
32
+
.dma_rx_param = "ssp0_rx",
33
+
/*
34
+
* This is number of spi devices that can be connected to spi. There are
35
+
* two type of chipselects on which slave devices can work. One is chip
36
+
* select provided by spi masters other is controlled through external
37
+
* gpio's. We can't use chipselect provided from spi master (because as
38
+
* soon as FIFO becomes empty, CS is disabled and transfer ends). So
39
+
* this number now depends on number of gpios available for spi. each
40
+
* slave on each master requires a separate gpio pin.
41
+
*/
42
+
.num_chipselect = 2,
29
43
};
30
44
31
-
AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
32
-
{SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
45
+
/* dmac device registration */
46
+
struct pl08x_platform_data pl080_plat_data = {
47
+
.memcpy_channel = {
48
+
.bus_id = "memcpy",
49
+
.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
50
+
PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
51
+
PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
52
+
PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
53
+
PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
54
+
PL080_CONTROL_PROT_SYS),
55
+
},
56
+
.lli_buses = PL08X_AHB1,
57
+
.mem_buses = PL08X_AHB1,
58
+
.get_signal = pl080_get_signal,
59
+
.put_signal = pl080_put_signal,
60
+
};
33
61
34
-
/* uart device registration */
35
-
AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
36
-
{SPEAR3XX_IRQ_UART}, NULL);
37
-
38
-
/* Do spear3xx familiy common initialization part here */
39
-
void __init spear3xx_init(void)
40
-
{
41
-
/* nothing to do for now */
42
-
}
43
-
44
-
/* This will initialize vic */
45
-
void __init spear3xx_init_irq(void)
46
-
{
47
-
vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
48
-
}
49
-
50
-
/* Following will create static virtual/physical mappings */
62
+
/*
63
+
* Following will create 16MB static virtual/physical mappings
64
+
* PHYSICAL VIRTUAL
65
+
* 0xD0000000 0xFD000000
66
+
* 0xFC000000 0xFC000000
67
+
*/
51
68
struct map_desc spear3xx_io_desc[] __initdata = {
52
69
{
53
-
.virtual = VA_SPEAR3XX_ICM1_UART_BASE,
54
-
.pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
55
-
.length = SZ_4K,
70
+
.virtual = VA_SPEAR3XX_ICM1_2_BASE,
71
+
.pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
72
+
.length = SZ_16M,
56
73
.type = MT_DEVICE
57
74
}, {
58
-
.virtual = VA_SPEAR3XX_ML1_VIC_BASE,
59
-
.pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
60
-
.length = SZ_4K,
61
-
.type = MT_DEVICE
62
-
}, {
63
-
.virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
64
-
.pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
65
-
.length = SZ_4K,
66
-
.type = MT_DEVICE
67
-
}, {
68
-
.virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
69
-
.pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
70
-
.length = SZ_4K,
75
+
.virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
76
+
.pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
77
+
.length = SZ_16M,
71
78
.type = MT_DEVICE
72
79
},
73
80
};
···
83
76
void __init spear3xx_map_io(void)
84
77
{
85
78
iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
86
-
87
-
/* This will initialize clock framework */
88
-
spear3xx_clk_init();
89
79
}
90
-
91
-
/* pad multiplexing support */
92
-
/* devices */
93
-
static struct pmx_dev_mode pmx_firda_modes[] = {
94
-
{
95
-
.ids = 0xffffffff,
96
-
.mask = PMX_FIRDA_MASK,
97
-
},
98
-
};
99
-
100
-
struct pmx_dev spear3xx_pmx_firda = {
101
-
.name = "firda",
102
-
.modes = pmx_firda_modes,
103
-
.mode_count = ARRAY_SIZE(pmx_firda_modes),
104
-
.enb_on_reset = 0,
105
-
};
106
-
107
-
static struct pmx_dev_mode pmx_i2c_modes[] = {
108
-
{
109
-
.ids = 0xffffffff,
110
-
.mask = PMX_I2C_MASK,
111
-
},
112
-
};
113
-
114
-
struct pmx_dev spear3xx_pmx_i2c = {
115
-
.name = "i2c",
116
-
.modes = pmx_i2c_modes,
117
-
.mode_count = ARRAY_SIZE(pmx_i2c_modes),
118
-
.enb_on_reset = 0,
119
-
};
120
-
121
-
static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
122
-
{
123
-
.ids = 0xffffffff,
124
-
.mask = PMX_SSP_CS_MASK,
125
-
},
126
-
};
127
-
128
-
struct pmx_dev spear3xx_pmx_ssp_cs = {
129
-
.name = "ssp_chip_selects",
130
-
.modes = pmx_ssp_cs_modes,
131
-
.mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
132
-
.enb_on_reset = 0,
133
-
};
134
-
135
-
static struct pmx_dev_mode pmx_ssp_modes[] = {
136
-
{
137
-
.ids = 0xffffffff,
138
-
.mask = PMX_SSP_MASK,
139
-
},
140
-
};
141
-
142
-
struct pmx_dev spear3xx_pmx_ssp = {
143
-
.name = "ssp",
144
-
.modes = pmx_ssp_modes,
145
-
.mode_count = ARRAY_SIZE(pmx_ssp_modes),
146
-
.enb_on_reset = 0,
147
-
};
148
-
149
-
static struct pmx_dev_mode pmx_mii_modes[] = {
150
-
{
151
-
.ids = 0xffffffff,
152
-
.mask = PMX_MII_MASK,
153
-
},
154
-
};
155
-
156
-
struct pmx_dev spear3xx_pmx_mii = {
157
-
.name = "mii",
158
-
.modes = pmx_mii_modes,
159
-
.mode_count = ARRAY_SIZE(pmx_mii_modes),
160
-
.enb_on_reset = 0,
161
-
};
162
-
163
-
static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
164
-
{
165
-
.ids = 0xffffffff,
166
-
.mask = PMX_GPIO_PIN0_MASK,
167
-
},
168
-
};
169
-
170
-
struct pmx_dev spear3xx_pmx_gpio_pin0 = {
171
-
.name = "gpio_pin0",
172
-
.modes = pmx_gpio_pin0_modes,
173
-
.mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
174
-
.enb_on_reset = 0,
175
-
};
176
-
177
-
static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
178
-
{
179
-
.ids = 0xffffffff,
180
-
.mask = PMX_GPIO_PIN1_MASK,
181
-
},
182
-
};
183
-
184
-
struct pmx_dev spear3xx_pmx_gpio_pin1 = {
185
-
.name = "gpio_pin1",
186
-
.modes = pmx_gpio_pin1_modes,
187
-
.mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
188
-
.enb_on_reset = 0,
189
-
};
190
-
191
-
static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
192
-
{
193
-
.ids = 0xffffffff,
194
-
.mask = PMX_GPIO_PIN2_MASK,
195
-
},
196
-
};
197
-
198
-
struct pmx_dev spear3xx_pmx_gpio_pin2 = {
199
-
.name = "gpio_pin2",
200
-
.modes = pmx_gpio_pin2_modes,
201
-
.mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
202
-
.enb_on_reset = 0,
203
-
};
204
-
205
-
static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
206
-
{
207
-
.ids = 0xffffffff,
208
-
.mask = PMX_GPIO_PIN3_MASK,
209
-
},
210
-
};
211
-
212
-
struct pmx_dev spear3xx_pmx_gpio_pin3 = {
213
-
.name = "gpio_pin3",
214
-
.modes = pmx_gpio_pin3_modes,
215
-
.mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
216
-
.enb_on_reset = 0,
217
-
};
218
-
219
-
static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
220
-
{
221
-
.ids = 0xffffffff,
222
-
.mask = PMX_GPIO_PIN4_MASK,
223
-
},
224
-
};
225
-
226
-
struct pmx_dev spear3xx_pmx_gpio_pin4 = {
227
-
.name = "gpio_pin4",
228
-
.modes = pmx_gpio_pin4_modes,
229
-
.mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
230
-
.enb_on_reset = 0,
231
-
};
232
-
233
-
static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
234
-
{
235
-
.ids = 0xffffffff,
236
-
.mask = PMX_GPIO_PIN5_MASK,
237
-
},
238
-
};
239
-
240
-
struct pmx_dev spear3xx_pmx_gpio_pin5 = {
241
-
.name = "gpio_pin5",
242
-
.modes = pmx_gpio_pin5_modes,
243
-
.mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
244
-
.enb_on_reset = 0,
245
-
};
246
-
247
-
static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
248
-
{
249
-
.ids = 0xffffffff,
250
-
.mask = PMX_UART0_MODEM_MASK,
251
-
},
252
-
};
253
-
254
-
struct pmx_dev spear3xx_pmx_uart0_modem = {
255
-
.name = "uart0_modem",
256
-
.modes = pmx_uart0_modem_modes,
257
-
.mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
258
-
.enb_on_reset = 0,
259
-
};
260
-
261
-
static struct pmx_dev_mode pmx_uart0_modes[] = {
262
-
{
263
-
.ids = 0xffffffff,
264
-
.mask = PMX_UART0_MASK,
265
-
},
266
-
};
267
-
268
-
struct pmx_dev spear3xx_pmx_uart0 = {
269
-
.name = "uart0",
270
-
.modes = pmx_uart0_modes,
271
-
.mode_count = ARRAY_SIZE(pmx_uart0_modes),
272
-
.enb_on_reset = 0,
273
-
};
274
-
275
-
static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
276
-
{
277
-
.ids = 0xffffffff,
278
-
.mask = PMX_TIMER_3_4_MASK,
279
-
},
280
-
};
281
-
282
-
struct pmx_dev spear3xx_pmx_timer_3_4 = {
283
-
.name = "timer_3_4",
284
-
.modes = pmx_timer_3_4_modes,
285
-
.mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
286
-
.enb_on_reset = 0,
287
-
};
288
-
289
-
static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
290
-
{
291
-
.ids = 0xffffffff,
292
-
.mask = PMX_TIMER_1_2_MASK,
293
-
},
294
-
};
295
-
296
-
struct pmx_dev spear3xx_pmx_timer_1_2 = {
297
-
.name = "timer_1_2",
298
-
.modes = pmx_timer_1_2_modes,
299
-
.mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
300
-
.enb_on_reset = 0,
301
-
};
302
-
303
-
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
304
-
/* plgpios devices */
305
-
static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
306
-
{
307
-
.ids = 0x00,
308
-
.mask = PMX_FIRDA_MASK,
309
-
},
310
-
};
311
-
312
-
struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
313
-
.name = "plgpio 0 and 1",
314
-
.modes = pmx_plgpio_0_1_modes,
315
-
.mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
316
-
.enb_on_reset = 1,
317
-
};
318
-
319
-
static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
320
-
{
321
-
.ids = 0x00,
322
-
.mask = PMX_UART0_MASK,
323
-
},
324
-
};
325
-
326
-
struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
327
-
.name = "plgpio 2 and 3",
328
-
.modes = pmx_plgpio_2_3_modes,
329
-
.mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
330
-
.enb_on_reset = 1,
331
-
};
332
-
333
-
static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
334
-
{
335
-
.ids = 0x00,
336
-
.mask = PMX_I2C_MASK,
337
-
},
338
-
};
339
-
340
-
struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
341
-
.name = "plgpio 4 and 5",
342
-
.modes = pmx_plgpio_4_5_modes,
343
-
.mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
344
-
.enb_on_reset = 1,
345
-
};
346
-
347
-
static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
348
-
{
349
-
.ids = 0x00,
350
-
.mask = PMX_SSP_MASK,
351
-
},
352
-
};
353
-
354
-
struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
355
-
.name = "plgpio 6 to 9",
356
-
.modes = pmx_plgpio_6_9_modes,
357
-
.mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
358
-
.enb_on_reset = 1,
359
-
};
360
-
361
-
static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
362
-
{
363
-
.ids = 0x00,
364
-
.mask = PMX_MII_MASK,
365
-
},
366
-
};
367
-
368
-
struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
369
-
.name = "plgpio 10 to 27",
370
-
.modes = pmx_plgpio_10_27_modes,
371
-
.mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
372
-
.enb_on_reset = 1,
373
-
};
374
-
375
-
static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
376
-
{
377
-
.ids = 0x00,
378
-
.mask = PMX_GPIO_PIN0_MASK,
379
-
},
380
-
};
381
-
382
-
struct pmx_dev spear3xx_pmx_plgpio_28 = {
383
-
.name = "plgpio 28",
384
-
.modes = pmx_plgpio_28_modes,
385
-
.mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
386
-
.enb_on_reset = 1,
387
-
};
388
-
389
-
static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
390
-
{
391
-
.ids = 0x00,
392
-
.mask = PMX_GPIO_PIN1_MASK,
393
-
},
394
-
};
395
-
396
-
struct pmx_dev spear3xx_pmx_plgpio_29 = {
397
-
.name = "plgpio 29",
398
-
.modes = pmx_plgpio_29_modes,
399
-
.mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
400
-
.enb_on_reset = 1,
401
-
};
402
-
403
-
static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
404
-
{
405
-
.ids = 0x00,
406
-
.mask = PMX_GPIO_PIN2_MASK,
407
-
},
408
-
};
409
-
410
-
struct pmx_dev spear3xx_pmx_plgpio_30 = {
411
-
.name = "plgpio 30",
412
-
.modes = pmx_plgpio_30_modes,
413
-
.mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
414
-
.enb_on_reset = 1,
415
-
};
416
-
417
-
static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
418
-
{
419
-
.ids = 0x00,
420
-
.mask = PMX_GPIO_PIN3_MASK,
421
-
},
422
-
};
423
-
424
-
struct pmx_dev spear3xx_pmx_plgpio_31 = {
425
-
.name = "plgpio 31",
426
-
.modes = pmx_plgpio_31_modes,
427
-
.mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
428
-
.enb_on_reset = 1,
429
-
};
430
-
431
-
static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
432
-
{
433
-
.ids = 0x00,
434
-
.mask = PMX_GPIO_PIN4_MASK,
435
-
},
436
-
};
437
-
438
-
struct pmx_dev spear3xx_pmx_plgpio_32 = {
439
-
.name = "plgpio 32",
440
-
.modes = pmx_plgpio_32_modes,
441
-
.mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
442
-
.enb_on_reset = 1,
443
-
};
444
-
445
-
static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
446
-
{
447
-
.ids = 0x00,
448
-
.mask = PMX_GPIO_PIN5_MASK,
449
-
},
450
-
};
451
-
452
-
struct pmx_dev spear3xx_pmx_plgpio_33 = {
453
-
.name = "plgpio 33",
454
-
.modes = pmx_plgpio_33_modes,
455
-
.mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
456
-
.enb_on_reset = 1,
457
-
};
458
-
459
-
static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
460
-
{
461
-
.ids = 0x00,
462
-
.mask = PMX_SSP_CS_MASK,
463
-
},
464
-
};
465
-
466
-
struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
467
-
.name = "plgpio 34 to 36",
468
-
.modes = pmx_plgpio_34_36_modes,
469
-
.mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
470
-
.enb_on_reset = 1,
471
-
};
472
-
473
-
static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
474
-
{
475
-
.ids = 0x00,
476
-
.mask = PMX_UART0_MODEM_MASK,
477
-
},
478
-
};
479
-
480
-
struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
481
-
.name = "plgpio 37 to 42",
482
-
.modes = pmx_plgpio_37_42_modes,
483
-
.mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
484
-
.enb_on_reset = 1,
485
-
};
486
-
487
-
static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
488
-
{
489
-
.ids = 0x00,
490
-
.mask = PMX_TIMER_1_2_MASK,
491
-
},
492
-
};
493
-
494
-
struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
495
-
.name = "plgpio 43, 44, 47 and 48",
496
-
.modes = pmx_plgpio_43_44_47_48_modes,
497
-
.mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
498
-
.enb_on_reset = 1,
499
-
};
500
-
501
-
static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
502
-
{
503
-
.ids = 0x00,
504
-
.mask = PMX_TIMER_3_4_MASK,
505
-
},
506
-
};
507
-
508
-
struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
509
-
.name = "plgpio 45, 46, 49 and 50",
510
-
.modes = pmx_plgpio_45_46_49_50_modes,
511
-
.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
512
-
.enb_on_reset = 1,
513
-
};
514
-
#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
515
80
516
81
static void __init spear3xx_timer_init(void)
517
82
{
···
111
532
clk_put(gpt_clk);
112
533
clk_put(pclk);
113
534
114
-
spear_setup_timer();
535
+
spear_setup_of_timer();
115
536
}
116
537
117
538
struct sys_timer spear3xx_timer = {
118
539
.init = spear3xx_timer_init,
119
540
};
541
+
542
+
static const struct of_device_id vic_of_match[] __initconst = {
543
+
{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
544
+
{ /* Sentinel */ }
545
+
};
546
+
547
+
void __init spear3xx_dt_init_irq(void)
548
+
{
549
+
of_irq_init(vic_of_match);
550
+
}
+2
arch/arm/mach-spear6xx/Makefile.boot
+2
arch/arm/mach-spear6xx/Makefile.boot
+2
-27
arch/arm/mach-spear6xx/include/mach/generic.h
+2
-27
arch/arm/mach-spear6xx/include/mach/generic.h
···
15
15
#define __MACH_GENERIC_H
16
16
17
17
#include <linux/init.h>
18
-
#include <linux/platform_device.h>
19
-
#include <linux/amba/bus.h>
20
-
#include <asm/mach/time.h>
21
-
#include <asm/mach/map.h>
22
18
23
-
/*
24
-
* Each GPT has 2 timer channels
25
-
* Following GPT channels will be used as clock source and clockevent
26
-
*/
27
-
#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE
28
-
#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
29
-
#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
30
-
31
-
/* Add spear6xx family device structure declarations here */
32
-
extern struct amba_device gpio_device[];
33
-
extern struct amba_device uart_device[];
34
-
extern struct sys_timer spear6xx_timer;
35
-
36
-
/* Add spear6xx family function declarations here */
37
-
void __init spear_setup_timer(void);
38
-
void __init spear6xx_map_io(void);
39
-
void __init spear6xx_init_irq(void);
40
-
void __init spear6xx_init(void);
41
-
void __init spear600_init(void);
42
-
void __init spear6xx_clk_init(void);
43
-
19
+
void __init spear_setup_of_timer(void);
44
20
void spear_restart(char, const char *);
45
-
46
-
/* Add spear600 machine device structure declarations here */
21
+
void __init spear6xx_clk_init(void);
47
22
48
23
#endif /* __MACH_GENERIC_H */
+1
-23
arch/arm/mach-spear6xx/include/mach/hardware.h
+1
-23
arch/arm/mach-spear6xx/include/mach/hardware.h
···
1
-
/*
2
-
* arch/arm/mach-spear6xx/include/mach/hardware.h
3
-
*
4
-
* Hardware definitions for SPEAr6xx machine family
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#ifndef __MACH_HARDWARE_H
15
-
#define __MACH_HARDWARE_H
16
-
17
-
#include <plat/hardware.h>
18
-
#include <mach/spear.h>
19
-
20
-
/* Vitual to physical translation of statically mapped space */
21
-
#define IO_ADDRESS(x) (x | 0xF0000000)
22
-
23
-
#endif /* __MACH_HARDWARE_H */
1
+
/* empty */
+2
-74
arch/arm/mach-spear6xx/include/mach/irqs.h
+2
-74
arch/arm/mach-spear6xx/include/mach/irqs.h
···
16
16
17
17
/* IRQ definitions */
18
18
/* VIC 1 */
19
-
#define IRQ_INTRCOMM_SW_IRQ 0
20
-
#define IRQ_INTRCOMM_CPU_1 1
21
-
#define IRQ_INTRCOMM_CPU_2 2
22
-
#define IRQ_INTRCOMM_RAS2A11_1 3
23
-
#define IRQ_INTRCOMM_RAS2A11_2 4
24
-
#define IRQ_INTRCOMM_RAS2A12_1 5
25
-
#define IRQ_INTRCOMM_RAS2A12_2 6
26
-
#define IRQ_GEN_RAS_0 7
27
-
#define IRQ_GEN_RAS_1 8
28
-
#define IRQ_GEN_RAS_2 9
29
-
#define IRQ_GEN_RAS_3 10
30
-
#define IRQ_GEN_RAS_4 11
31
-
#define IRQ_GEN_RAS_5 12
32
-
#define IRQ_GEN_RAS_6 13
33
-
#define IRQ_GEN_RAS_7 14
34
-
#define IRQ_GEN_RAS_8 15
35
-
#define IRQ_CPU_GPT1_1 16
36
-
#define IRQ_CPU_GPT1_2 17
37
-
#define IRQ_LOCAL_GPIO 18
38
-
#define IRQ_PLL_UNLOCK 19
39
-
#define IRQ_JPEG 20
40
-
#define IRQ_FSMC 21
41
-
#define IRQ_IRDA 22
42
-
#define IRQ_RESERVED 23
43
-
#define IRQ_UART_0 24
44
-
#define IRQ_UART_1 25
45
-
#define IRQ_SSP_1 26
46
-
#define IRQ_SSP_2 27
47
-
#define IRQ_I2C 28
48
-
#define IRQ_GEN_RAS_9 29
49
-
#define IRQ_GEN_RAS_10 30
50
-
#define IRQ_GEN_RAS_11 31
51
-
52
-
/* VIC 2 */
53
-
#define IRQ_APPL_GPT1_1 32
54
-
#define IRQ_APPL_GPT1_2 33
55
-
#define IRQ_APPL_GPT2_1 34
56
-
#define IRQ_APPL_GPT2_2 35
57
-
#define IRQ_APPL_GPIO 36
58
-
#define IRQ_APPL_SSP 37
59
-
#define IRQ_APPL_ADC 38
60
-
#define IRQ_APPL_RESERVED 39
61
-
#define IRQ_AHB_EXP_MASTER 40
62
-
#define IRQ_DDR_CONTROLLER 41
63
-
#define IRQ_BASIC_DMA 42
64
-
#define IRQ_BASIC_RESERVED1 43
65
-
#define IRQ_BASIC_SMI 44
66
-
#define IRQ_BASIC_CLCD 45
67
-
#define IRQ_EXP_AHB_1 46
68
-
#define IRQ_EXP_AHB_2 47
69
-
#define IRQ_BASIC_GPT1_1 48
70
-
#define IRQ_BASIC_GPT1_2 49
71
-
#define IRQ_BASIC_RTC 50
72
-
#define IRQ_BASIC_GPIO 51
73
-
#define IRQ_BASIC_WDT 52
74
-
#define IRQ_BASIC_RESERVED 53
75
-
#define IRQ_AHB_EXP_SLAVE 54
76
-
#define IRQ_GMAC_1 55
77
-
#define IRQ_GMAC_2 56
78
-
#define IRQ_USB_DEV 57
79
-
#define IRQ_USB_H_OHCI_0 58
80
-
#define IRQ_USB_H_EHCI_0 59
81
-
#define IRQ_USB_H_OHCI_1 60
82
-
#define IRQ_USB_H_EHCI_1 61
83
-
#define IRQ_EXP_AHB_3 62
84
-
#define IRQ_EXP_AHB_4 63
85
-
86
19
#define IRQ_VIC_END 64
87
20
88
21
/* GPIO pins virtual irqs */
89
-
#define SPEAR_GPIO_INT_BASE IRQ_VIC_END
90
-
#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE
91
-
#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
92
-
#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8)
93
-
#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8)
94
-
#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END)
95
-
#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
22
+
#define VIRTUAL_IRQS 24
23
+
#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
96
24
97
25
#endif /* __MACH_IRQS_H */
+1
-1
arch/arm/mach-spear6xx/include/mach/misc_regs.h
+1
-1
arch/arm/mach-spear6xx/include/mach/misc_regs.h
+6
-50
arch/arm/mach-spear6xx/include/mach/spear.h
+6
-50
arch/arm/mach-spear6xx/include/mach/spear.h
···
15
15
#define __MACH_SPEAR6XX_H
16
16
17
17
#include <asm/memory.h>
18
-
#include <mach/spear600.h>
19
18
20
-
#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
21
19
/* ICM1 - Low speed connection */
22
20
#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
23
-
21
+
#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000)
24
22
#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
25
-
#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
26
-
27
-
#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
28
-
#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
29
-
#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
30
-
#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
31
-
#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
32
-
#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
33
-
#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
34
-
#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
35
-
#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
36
-
37
-
/* ICM2 - Application Subsystem */
38
-
#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
39
-
#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
40
-
#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
41
-
#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
42
-
#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
43
-
#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
23
+
#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
44
24
45
25
/* ML-1, 2 - Multi Layer CPU Subsystem */
46
26
#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
47
-
#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
48
-
#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
49
-
#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
50
-
#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
51
-
#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
52
-
#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
27
+
#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
53
28
54
29
/* ICM3 - Basic Subsystem */
55
-
#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
56
-
#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
57
30
#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
58
-
#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000)
31
+
#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
59
32
#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
60
-
#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
61
-
#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
62
-
#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
63
-
#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
64
-
#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
65
33
#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
66
-
#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
34
+
#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
67
35
#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
68
-
#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
69
-
70
-
/* ICM4 - High Speed Connection */
71
-
#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
72
-
#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
73
-
#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
74
-
#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
75
-
#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
76
-
#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
77
-
#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
78
-
#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
79
-
#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
80
-
#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
36
+
#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
81
37
82
38
/* Debug uart for linux, will be used for debug and uncompress messages */
83
39
#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
-21
arch/arm/mach-spear6xx/include/mach/spear600.h
-21
arch/arm/mach-spear6xx/include/mach/spear600.h
···
1
-
/*
2
-
* arch/arm/mach-spear66xx/include/mach/spear600.h
3
-
*
4
-
* SPEAr600 Machine specific definition
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#ifdef CONFIG_MACH_SPEAR600
15
-
16
-
#ifndef __MACH_SPEAR600_H
17
-
#define __MACH_SPEAR600_H
18
-
19
-
#endif /* __MACH_SPEAR600_H */
20
-
21
-
#endif /* CONFIG_MACH_SPEAR600 */
+397
-26
arch/arm/mach-spear6xx/spear6xx.c
+397
-26
arch/arm/mach-spear6xx/spear6xx.c
···
13
13
* warranty of any kind, whether express or implied.
14
14
*/
15
15
16
+
#include <linux/amba/pl08x.h>
17
+
#include <linux/clk.h>
18
+
#include <linux/err.h>
16
19
#include <linux/of.h>
17
20
#include <linux/of_address.h>
18
21
#include <linux/of_irq.h>
19
22
#include <linux/of_platform.h>
23
+
#include <asm/hardware/pl080.h>
20
24
#include <asm/hardware/vic.h>
21
25
#include <asm/mach/arch.h>
26
+
#include <asm/mach/time.h>
27
+
#include <asm/mach/map.h>
28
+
#include <plat/pl080.h>
22
29
#include <mach/generic.h>
23
-
#include <mach/hardware.h>
30
+
#include <mach/spear.h>
24
31
25
-
/* Following will create static virtual/physical mappings */
26
-
static struct map_desc spear6xx_io_desc[] __initdata = {
32
+
/* dmac device registration */
33
+
static struct pl08x_channel_data spear600_dma_info[] = {
27
34
{
28
-
.virtual = VA_SPEAR6XX_ICM1_UART0_BASE,
29
-
.pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
30
-
.length = SZ_4K,
35
+
.bus_id = "ssp1_rx",
36
+
.min_signal = 0,
37
+
.max_signal = 0,
38
+
.muxval = 0,
39
+
.cctl = 0,
40
+
.periph_buses = PL08X_AHB1,
41
+
}, {
42
+
.bus_id = "ssp1_tx",
43
+
.min_signal = 1,
44
+
.max_signal = 1,
45
+
.muxval = 0,
46
+
.cctl = 0,
47
+
.periph_buses = PL08X_AHB1,
48
+
}, {
49
+
.bus_id = "uart0_rx",
50
+
.min_signal = 2,
51
+
.max_signal = 2,
52
+
.muxval = 0,
53
+
.cctl = 0,
54
+
.periph_buses = PL08X_AHB1,
55
+
}, {
56
+
.bus_id = "uart0_tx",
57
+
.min_signal = 3,
58
+
.max_signal = 3,
59
+
.muxval = 0,
60
+
.cctl = 0,
61
+
.periph_buses = PL08X_AHB1,
62
+
}, {
63
+
.bus_id = "uart1_rx",
64
+
.min_signal = 4,
65
+
.max_signal = 4,
66
+
.muxval = 0,
67
+
.cctl = 0,
68
+
.periph_buses = PL08X_AHB1,
69
+
}, {
70
+
.bus_id = "uart1_tx",
71
+
.min_signal = 5,
72
+
.max_signal = 5,
73
+
.muxval = 0,
74
+
.cctl = 0,
75
+
.periph_buses = PL08X_AHB1,
76
+
}, {
77
+
.bus_id = "ssp2_rx",
78
+
.min_signal = 6,
79
+
.max_signal = 6,
80
+
.muxval = 0,
81
+
.cctl = 0,
82
+
.periph_buses = PL08X_AHB2,
83
+
}, {
84
+
.bus_id = "ssp2_tx",
85
+
.min_signal = 7,
86
+
.max_signal = 7,
87
+
.muxval = 0,
88
+
.cctl = 0,
89
+
.periph_buses = PL08X_AHB2,
90
+
}, {
91
+
.bus_id = "ssp0_rx",
92
+
.min_signal = 8,
93
+
.max_signal = 8,
94
+
.muxval = 0,
95
+
.cctl = 0,
96
+
.periph_buses = PL08X_AHB1,
97
+
}, {
98
+
.bus_id = "ssp0_tx",
99
+
.min_signal = 9,
100
+
.max_signal = 9,
101
+
.muxval = 0,
102
+
.cctl = 0,
103
+
.periph_buses = PL08X_AHB1,
104
+
}, {
105
+
.bus_id = "i2c_rx",
106
+
.min_signal = 10,
107
+
.max_signal = 10,
108
+
.muxval = 0,
109
+
.cctl = 0,
110
+
.periph_buses = PL08X_AHB1,
111
+
}, {
112
+
.bus_id = "i2c_tx",
113
+
.min_signal = 11,
114
+
.max_signal = 11,
115
+
.muxval = 0,
116
+
.cctl = 0,
117
+
.periph_buses = PL08X_AHB1,
118
+
}, {
119
+
.bus_id = "irda",
120
+
.min_signal = 12,
121
+
.max_signal = 12,
122
+
.muxval = 0,
123
+
.cctl = 0,
124
+
.periph_buses = PL08X_AHB1,
125
+
}, {
126
+
.bus_id = "adc",
127
+
.min_signal = 13,
128
+
.max_signal = 13,
129
+
.muxval = 0,
130
+
.cctl = 0,
131
+
.periph_buses = PL08X_AHB2,
132
+
}, {
133
+
.bus_id = "to_jpeg",
134
+
.min_signal = 14,
135
+
.max_signal = 14,
136
+
.muxval = 0,
137
+
.cctl = 0,
138
+
.periph_buses = PL08X_AHB1,
139
+
}, {
140
+
.bus_id = "from_jpeg",
141
+
.min_signal = 15,
142
+
.max_signal = 15,
143
+
.muxval = 0,
144
+
.cctl = 0,
145
+
.periph_buses = PL08X_AHB1,
146
+
}, {
147
+
.bus_id = "ras0_rx",
148
+
.min_signal = 0,
149
+
.max_signal = 0,
150
+
.muxval = 1,
151
+
.cctl = 0,
152
+
.periph_buses = PL08X_AHB1,
153
+
}, {
154
+
.bus_id = "ras0_tx",
155
+
.min_signal = 1,
156
+
.max_signal = 1,
157
+
.muxval = 1,
158
+
.cctl = 0,
159
+
.periph_buses = PL08X_AHB1,
160
+
}, {
161
+
.bus_id = "ras1_rx",
162
+
.min_signal = 2,
163
+
.max_signal = 2,
164
+
.muxval = 1,
165
+
.cctl = 0,
166
+
.periph_buses = PL08X_AHB1,
167
+
}, {
168
+
.bus_id = "ras1_tx",
169
+
.min_signal = 3,
170
+
.max_signal = 3,
171
+
.muxval = 1,
172
+
.cctl = 0,
173
+
.periph_buses = PL08X_AHB1,
174
+
}, {
175
+
.bus_id = "ras2_rx",
176
+
.min_signal = 4,
177
+
.max_signal = 4,
178
+
.muxval = 1,
179
+
.cctl = 0,
180
+
.periph_buses = PL08X_AHB1,
181
+
}, {
182
+
.bus_id = "ras2_tx",
183
+
.min_signal = 5,
184
+
.max_signal = 5,
185
+
.muxval = 1,
186
+
.cctl = 0,
187
+
.periph_buses = PL08X_AHB1,
188
+
}, {
189
+
.bus_id = "ras3_rx",
190
+
.min_signal = 6,
191
+
.max_signal = 6,
192
+
.muxval = 1,
193
+
.cctl = 0,
194
+
.periph_buses = PL08X_AHB1,
195
+
}, {
196
+
.bus_id = "ras3_tx",
197
+
.min_signal = 7,
198
+
.max_signal = 7,
199
+
.muxval = 1,
200
+
.cctl = 0,
201
+
.periph_buses = PL08X_AHB1,
202
+
}, {
203
+
.bus_id = "ras4_rx",
204
+
.min_signal = 8,
205
+
.max_signal = 8,
206
+
.muxval = 1,
207
+
.cctl = 0,
208
+
.periph_buses = PL08X_AHB1,
209
+
}, {
210
+
.bus_id = "ras4_tx",
211
+
.min_signal = 9,
212
+
.max_signal = 9,
213
+
.muxval = 1,
214
+
.cctl = 0,
215
+
.periph_buses = PL08X_AHB1,
216
+
}, {
217
+
.bus_id = "ras5_rx",
218
+
.min_signal = 10,
219
+
.max_signal = 10,
220
+
.muxval = 1,
221
+
.cctl = 0,
222
+
.periph_buses = PL08X_AHB1,
223
+
}, {
224
+
.bus_id = "ras5_tx",
225
+
.min_signal = 11,
226
+
.max_signal = 11,
227
+
.muxval = 1,
228
+
.cctl = 0,
229
+
.periph_buses = PL08X_AHB1,
230
+
}, {
231
+
.bus_id = "ras6_rx",
232
+
.min_signal = 12,
233
+
.max_signal = 12,
234
+
.muxval = 1,
235
+
.cctl = 0,
236
+
.periph_buses = PL08X_AHB1,
237
+
}, {
238
+
.bus_id = "ras6_tx",
239
+
.min_signal = 13,
240
+
.max_signal = 13,
241
+
.muxval = 1,
242
+
.cctl = 0,
243
+
.periph_buses = PL08X_AHB1,
244
+
}, {
245
+
.bus_id = "ras7_rx",
246
+
.min_signal = 14,
247
+
.max_signal = 14,
248
+
.muxval = 1,
249
+
.cctl = 0,
250
+
.periph_buses = PL08X_AHB1,
251
+
}, {
252
+
.bus_id = "ras7_tx",
253
+
.min_signal = 15,
254
+
.max_signal = 15,
255
+
.muxval = 1,
256
+
.cctl = 0,
257
+
.periph_buses = PL08X_AHB1,
258
+
}, {
259
+
.bus_id = "ext0_rx",
260
+
.min_signal = 0,
261
+
.max_signal = 0,
262
+
.muxval = 2,
263
+
.cctl = 0,
264
+
.periph_buses = PL08X_AHB2,
265
+
}, {
266
+
.bus_id = "ext0_tx",
267
+
.min_signal = 1,
268
+
.max_signal = 1,
269
+
.muxval = 2,
270
+
.cctl = 0,
271
+
.periph_buses = PL08X_AHB2,
272
+
}, {
273
+
.bus_id = "ext1_rx",
274
+
.min_signal = 2,
275
+
.max_signal = 2,
276
+
.muxval = 2,
277
+
.cctl = 0,
278
+
.periph_buses = PL08X_AHB2,
279
+
}, {
280
+
.bus_id = "ext1_tx",
281
+
.min_signal = 3,
282
+
.max_signal = 3,
283
+
.muxval = 2,
284
+
.cctl = 0,
285
+
.periph_buses = PL08X_AHB2,
286
+
}, {
287
+
.bus_id = "ext2_rx",
288
+
.min_signal = 4,
289
+
.max_signal = 4,
290
+
.muxval = 2,
291
+
.cctl = 0,
292
+
.periph_buses = PL08X_AHB2,
293
+
}, {
294
+
.bus_id = "ext2_tx",
295
+
.min_signal = 5,
296
+
.max_signal = 5,
297
+
.muxval = 2,
298
+
.cctl = 0,
299
+
.periph_buses = PL08X_AHB2,
300
+
}, {
301
+
.bus_id = "ext3_rx",
302
+
.min_signal = 6,
303
+
.max_signal = 6,
304
+
.muxval = 2,
305
+
.cctl = 0,
306
+
.periph_buses = PL08X_AHB2,
307
+
}, {
308
+
.bus_id = "ext3_tx",
309
+
.min_signal = 7,
310
+
.max_signal = 7,
311
+
.muxval = 2,
312
+
.cctl = 0,
313
+
.periph_buses = PL08X_AHB2,
314
+
}, {
315
+
.bus_id = "ext4_rx",
316
+
.min_signal = 8,
317
+
.max_signal = 8,
318
+
.muxval = 2,
319
+
.cctl = 0,
320
+
.periph_buses = PL08X_AHB2,
321
+
}, {
322
+
.bus_id = "ext4_tx",
323
+
.min_signal = 9,
324
+
.max_signal = 9,
325
+
.muxval = 2,
326
+
.cctl = 0,
327
+
.periph_buses = PL08X_AHB2,
328
+
}, {
329
+
.bus_id = "ext5_rx",
330
+
.min_signal = 10,
331
+
.max_signal = 10,
332
+
.muxval = 2,
333
+
.cctl = 0,
334
+
.periph_buses = PL08X_AHB2,
335
+
}, {
336
+
.bus_id = "ext5_tx",
337
+
.min_signal = 11,
338
+
.max_signal = 11,
339
+
.muxval = 2,
340
+
.cctl = 0,
341
+
.periph_buses = PL08X_AHB2,
342
+
}, {
343
+
.bus_id = "ext6_rx",
344
+
.min_signal = 12,
345
+
.max_signal = 12,
346
+
.muxval = 2,
347
+
.cctl = 0,
348
+
.periph_buses = PL08X_AHB2,
349
+
}, {
350
+
.bus_id = "ext6_tx",
351
+
.min_signal = 13,
352
+
.max_signal = 13,
353
+
.muxval = 2,
354
+
.cctl = 0,
355
+
.periph_buses = PL08X_AHB2,
356
+
}, {
357
+
.bus_id = "ext7_rx",
358
+
.min_signal = 14,
359
+
.max_signal = 14,
360
+
.muxval = 2,
361
+
.cctl = 0,
362
+
.periph_buses = PL08X_AHB2,
363
+
}, {
364
+
.bus_id = "ext7_tx",
365
+
.min_signal = 15,
366
+
.max_signal = 15,
367
+
.muxval = 2,
368
+
.cctl = 0,
369
+
.periph_buses = PL08X_AHB2,
370
+
},
371
+
};
372
+
373
+
struct pl08x_platform_data pl080_plat_data = {
374
+
.memcpy_channel = {
375
+
.bus_id = "memcpy",
376
+
.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
377
+
PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
378
+
PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
379
+
PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
380
+
PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
381
+
PL080_CONTROL_PROT_SYS),
382
+
},
383
+
.lli_buses = PL08X_AHB1,
384
+
.mem_buses = PL08X_AHB1,
385
+
.get_signal = pl080_get_signal,
386
+
.put_signal = pl080_put_signal,
387
+
.slave_channels = spear600_dma_info,
388
+
.num_slave_channels = ARRAY_SIZE(spear600_dma_info),
389
+
};
390
+
391
+
/*
392
+
* Following will create 16MB static virtual/physical mappings
393
+
* PHYSICAL VIRTUAL
394
+
* 0xF0000000 0xF0000000
395
+
* 0xF1000000 0xF1000000
396
+
* 0xD0000000 0xFD000000
397
+
* 0xFC000000 0xFC000000
398
+
*/
399
+
struct map_desc spear6xx_io_desc[] __initdata = {
400
+
{
401
+
.virtual = VA_SPEAR6XX_ML_CPU_BASE,
402
+
.pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
403
+
.length = 2 * SZ_16M,
404
+
.type = MT_DEVICE
405
+
}, {
406
+
.virtual = VA_SPEAR6XX_ICM1_BASE,
407
+
.pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
408
+
.length = SZ_16M,
31
409
.type = MT_DEVICE
32
410
}, {
33
-
.virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
34
-
.pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
35
-
.length = SZ_4K,
36
-
.type = MT_DEVICE
37
-
}, {
38
-
.virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
39
-
.pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
40
-
.length = SZ_4K,
41
-
.type = MT_DEVICE
42
-
}, {
43
-
.virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
44
-
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
45
-
.length = SZ_4K,
46
-
.type = MT_DEVICE
47
-
}, {
48
-
.virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
49
-
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
50
-
.length = SZ_4K,
411
+
.virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
412
+
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
413
+
.length = SZ_16M,
51
414
.type = MT_DEVICE
52
415
},
53
416
};
···
447
84
clk_put(gpt_clk);
448
85
clk_put(pclk);
449
86
450
-
spear_setup_timer();
87
+
spear_setup_of_timer();
451
88
}
452
89
453
90
struct sys_timer spear6xx_timer = {
454
91
.init = spear6xx_timer_init,
455
92
};
456
93
94
+
/* Add auxdata to pass platform data */
95
+
struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
96
+
OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
97
+
&pl080_plat_data),
98
+
{}
99
+
};
100
+
457
101
static void __init spear600_dt_init(void)
458
102
{
459
-
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
103
+
of_platform_populate(NULL, of_default_bus_match_table,
104
+
spear6xx_auxdata_lookup, NULL);
460
105
}
461
106
462
107
static const char *spear600_dt_board_compat[] = {
+3
-1
arch/arm/plat-spear/Kconfig
+3
-1
arch/arm/plat-spear/Kconfig
+2
-2
arch/arm/plat-spear/Makefile
+2
-2
arch/arm/plat-spear/Makefile
+1
-1
arch/arm/plat-spear/include/plat/debug-macro.S
+1
-1
arch/arm/plat-spear/include/plat/debug-macro.S
-17
arch/arm/plat-spear/include/plat/hardware.h
-17
arch/arm/plat-spear/include/plat/hardware.h
···
1
-
/*
2
-
* arch/arm/plat-spear/include/plat/hardware.h
3
-
*
4
-
* Hardware definitions for SPEAr
5
-
*
6
-
* Copyright (C) 2010 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#ifndef __PLAT_HARDWARE_H
15
-
#define __PLAT_HARDWARE_H
16
-
17
-
#endif /* __PLAT_HARDWARE_H */
-92
arch/arm/plat-spear/include/plat/padmux.h
-92
arch/arm/plat-spear/include/plat/padmux.h
···
1
-
/*
2
-
* arch/arm/plat-spear/include/plat/padmux.h
3
-
*
4
-
* SPEAr platform specific gpio pads muxing file
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#ifndef __PLAT_PADMUX_H
15
-
#define __PLAT_PADMUX_H
16
-
17
-
#include <linux/types.h>
18
-
19
-
/*
20
-
* struct pmx_reg: configuration structure for mode reg and mux reg
21
-
*
22
-
* offset: offset of mode reg
23
-
* mask: mask of mode reg
24
-
*/
25
-
struct pmx_reg {
26
-
u32 offset;
27
-
u32 mask;
28
-
};
29
-
30
-
/*
31
-
* struct pmx_dev_mode: configuration structure every group of modes of a device
32
-
*
33
-
* ids: all modes for this configuration
34
-
* mask: mask for supported mode
35
-
*/
36
-
struct pmx_dev_mode {
37
-
u32 ids;
38
-
u32 mask;
39
-
};
40
-
41
-
/*
42
-
* struct pmx_mode: mode definition structure
43
-
*
44
-
* name: mode name
45
-
* mask: mode mask
46
-
*/
47
-
struct pmx_mode {
48
-
char *name;
49
-
u32 id;
50
-
u32 mask;
51
-
};
52
-
53
-
/*
54
-
* struct pmx_dev: device definition structure
55
-
*
56
-
* name: device name
57
-
* modes: device configuration array for different modes supported
58
-
* mode_count: size of modes array
59
-
* is_active: is peripheral active/enabled
60
-
* enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
61
-
*/
62
-
struct pmx_dev {
63
-
char *name;
64
-
struct pmx_dev_mode *modes;
65
-
u8 mode_count;
66
-
bool is_active;
67
-
bool enb_on_reset;
68
-
};
69
-
70
-
/*
71
-
* struct pmx_driver: driver definition structure
72
-
*
73
-
* mode: mode to be set
74
-
* devs: array of pointer to pmx devices
75
-
* devs_count: ARRAY_SIZE of devs
76
-
* base: base address of soc config registers
77
-
* mode_reg: structure of mode config register
78
-
* mux_reg: structure of device mux config register
79
-
*/
80
-
struct pmx_driver {
81
-
struct pmx_mode *mode;
82
-
struct pmx_dev **devs;
83
-
u8 devs_count;
84
-
u32 *base;
85
-
struct pmx_reg mode_reg;
86
-
struct pmx_reg mux_reg;
87
-
};
88
-
89
-
/* pmx functions */
90
-
int pmx_register(struct pmx_driver *driver);
91
-
92
-
#endif /* __PLAT_PADMUX_H */
+21
arch/arm/plat-spear/include/plat/pl080.h
+21
arch/arm/plat-spear/include/plat/pl080.h
···
1
+
/*
2
+
* arch/arm/plat-spear/include/plat/pl080.h
3
+
*
4
+
* DMAC pl080 definitions for SPEAr platform
5
+
*
6
+
* Copyright (C) 2012 ST Microelectronics
7
+
* Viresh Kumar <viresh.kumar@st.com>
8
+
*
9
+
* This file is licensed under the terms of the GNU General Public
10
+
* License version 2. This program is licensed "as is" without any
11
+
* warranty of any kind, whether express or implied.
12
+
*/
13
+
14
+
#ifndef __PLAT_PL080_H
15
+
#define __PLAT_PL080_H
16
+
17
+
struct pl08x_dma_chan;
18
+
int pl080_get_signal(struct pl08x_dma_chan *ch);
19
+
void pl080_put_signal(struct pl08x_dma_chan *ch);
20
+
21
+
#endif /* __PLAT_PL080_H */
+1
-1
arch/arm/plat-spear/include/plat/uncompress.h
+1
-1
arch/arm/plat-spear/include/plat/uncompress.h
-164
arch/arm/plat-spear/padmux.c
-164
arch/arm/plat-spear/padmux.c
···
1
-
/*
2
-
* arch/arm/plat-spear/include/plat/padmux.c
3
-
*
4
-
* SPEAr platform specific gpio pads muxing source file
5
-
*
6
-
* Copyright (C) 2009 ST Microelectronics
7
-
* Viresh Kumar<viresh.kumar@st.com>
8
-
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
-
*/
13
-
14
-
#include <linux/err.h>
15
-
#include <linux/io.h>
16
-
#include <linux/slab.h>
17
-
#include <plat/padmux.h>
18
-
19
-
/*
20
-
* struct pmx: pmx definition structure
21
-
*
22
-
* base: base address of configuration registers
23
-
* mode_reg: mode configurations
24
-
* mux_reg: muxing configurations
25
-
* active_mode: pointer to current active mode
26
-
*/
27
-
struct pmx {
28
-
u32 base;
29
-
struct pmx_reg mode_reg;
30
-
struct pmx_reg mux_reg;
31
-
struct pmx_mode *active_mode;
32
-
};
33
-
34
-
static struct pmx *pmx;
35
-
36
-
/**
37
-
* pmx_mode_set - Enables an multiplexing mode
38
-
* @mode - pointer to pmx mode
39
-
*
40
-
* It will set mode of operation in hardware.
41
-
* Returns -ve on Err otherwise 0
42
-
*/
43
-
static int pmx_mode_set(struct pmx_mode *mode)
44
-
{
45
-
u32 val;
46
-
47
-
if (!mode->name)
48
-
return -EFAULT;
49
-
50
-
pmx->active_mode = mode;
51
-
52
-
val = readl(pmx->base + pmx->mode_reg.offset);
53
-
val &= ~pmx->mode_reg.mask;
54
-
val |= mode->mask & pmx->mode_reg.mask;
55
-
writel(val, pmx->base + pmx->mode_reg.offset);
56
-
57
-
return 0;
58
-
}
59
-
60
-
/**
61
-
* pmx_devs_enable - Enables list of devices
62
-
* @devs - pointer to pmx device array
63
-
* @count - number of devices to enable
64
-
*
65
-
* It will enable pads for all required peripherals once and only once.
66
-
* If peripheral is not supported by current mode then request is rejected.
67
-
* Conflicts between peripherals are not handled and peripherals will be
68
-
* enabled in the order they are present in pmx_dev array.
69
-
* In case of conflicts last peripheral enabled will be present.
70
-
* Returns -ve on Err otherwise 0
71
-
*/
72
-
static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
73
-
{
74
-
u32 val, i, mask;
75
-
76
-
if (!count)
77
-
return -EINVAL;
78
-
79
-
val = readl(pmx->base + pmx->mux_reg.offset);
80
-
for (i = 0; i < count; i++) {
81
-
u8 j = 0;
82
-
83
-
if (!devs[i]->name || !devs[i]->modes) {
84
-
printk(KERN_ERR "padmux: dev name or modes is null\n");
85
-
continue;
86
-
}
87
-
/* check if peripheral exists in active mode */
88
-
if (pmx->active_mode) {
89
-
bool found = false;
90
-
for (j = 0; j < devs[i]->mode_count; j++) {
91
-
if (devs[i]->modes[j].ids &
92
-
pmx->active_mode->id) {
93
-
found = true;
94
-
break;
95
-
}
96
-
}
97
-
if (found == false) {
98
-
printk(KERN_ERR "%s device not available in %s"\
99
-
"mode\n", devs[i]->name,
100
-
pmx->active_mode->name);
101
-
continue;
102
-
}
103
-
}
104
-
105
-
/* enable peripheral */
106
-
mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
107
-
if (devs[i]->enb_on_reset)
108
-
val &= ~mask;
109
-
else
110
-
val |= mask;
111
-
112
-
devs[i]->is_active = true;
113
-
}
114
-
writel(val, pmx->base + pmx->mux_reg.offset);
115
-
kfree(pmx);
116
-
117
-
/* this will ensure that multiplexing can't be changed now */
118
-
pmx = (struct pmx *)-1;
119
-
120
-
return 0;
121
-
}
122
-
123
-
/**
124
-
* pmx_register - registers a platform requesting pad mux feature
125
-
* @driver - pointer to driver structure containing driver specific parameters
126
-
*
127
-
* Also this must be called only once. This will allocate memory for pmx
128
-
* structure, will call pmx_mode_set, will call pmx_devs_enable.
129
-
* Returns -ve on Err otherwise 0
130
-
*/
131
-
int pmx_register(struct pmx_driver *driver)
132
-
{
133
-
int ret = 0;
134
-
135
-
if (pmx)
136
-
return -EPERM;
137
-
if (!driver->base || !driver->devs)
138
-
return -EFAULT;
139
-
140
-
pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
141
-
if (!pmx)
142
-
return -ENOMEM;
143
-
144
-
pmx->base = (u32)driver->base;
145
-
pmx->mode_reg.offset = driver->mode_reg.offset;
146
-
pmx->mode_reg.mask = driver->mode_reg.mask;
147
-
pmx->mux_reg.offset = driver->mux_reg.offset;
148
-
pmx->mux_reg.mask = driver->mux_reg.mask;
149
-
150
-
/* choose mode to enable */
151
-
if (driver->mode) {
152
-
ret = pmx_mode_set(driver->mode);
153
-
if (ret)
154
-
goto pmx_fail;
155
-
}
156
-
ret = pmx_devs_enable(driver->devs, driver->devs_count);
157
-
if (ret)
158
-
goto pmx_fail;
159
-
160
-
return 0;
161
-
162
-
pmx_fail:
163
-
return ret;
164
-
}
+80
arch/arm/plat-spear/pl080.c
+80
arch/arm/plat-spear/pl080.c
···
1
+
/*
2
+
* arch/arm/plat-spear/pl080.c
3
+
*
4
+
* DMAC pl080 definitions for SPEAr platform
5
+
*
6
+
* Copyright (C) 2012 ST Microelectronics
7
+
* Viresh Kumar <viresh.kumar@st.com>
8
+
*
9
+
* This file is licensed under the terms of the GNU General Public
10
+
* License version 2. This program is licensed "as is" without any
11
+
* warranty of any kind, whether express or implied.
12
+
*/
13
+
14
+
#include <linux/amba/pl08x.h>
15
+
#include <linux/amba/bus.h>
16
+
#include <linux/bug.h>
17
+
#include <linux/err.h>
18
+
#include <linux/io.h>
19
+
#include <linux/spinlock_types.h>
20
+
#include <mach/spear.h>
21
+
#include <mach/misc_regs.h>
22
+
23
+
static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
24
+
25
+
struct {
26
+
unsigned char busy;
27
+
unsigned char val;
28
+
} signals[16] = {{0, 0}, };
29
+
30
+
int pl080_get_signal(struct pl08x_dma_chan *ch)
31
+
{
32
+
const struct pl08x_channel_data *cd = ch->cd;
33
+
unsigned int signal = cd->min_signal, val;
34
+
unsigned long flags;
35
+
36
+
spin_lock_irqsave(&lock, flags);
37
+
38
+
/* Return if signal is already acquired by somebody else */
39
+
if (signals[signal].busy &&
40
+
(signals[signal].val != cd->muxval)) {
41
+
spin_unlock_irqrestore(&lock, flags);
42
+
return -EBUSY;
43
+
}
44
+
45
+
/* If acquiring for the first time, configure it */
46
+
if (!signals[signal].busy) {
47
+
val = readl(DMA_CHN_CFG);
48
+
49
+
/*
50
+
* Each request line has two bits in DMA_CHN_CFG register. To
51
+
* goto the bits of current request line, do left shift of
52
+
* value by 2 * signal number.
53
+
*/
54
+
val &= ~(0x3 << (signal * 2));
55
+
val |= cd->muxval << (signal * 2);
56
+
writel(val, DMA_CHN_CFG);
57
+
}
58
+
59
+
signals[signal].busy++;
60
+
signals[signal].val = cd->muxval;
61
+
spin_unlock_irqrestore(&lock, flags);
62
+
63
+
return signal;
64
+
}
65
+
66
+
void pl080_put_signal(struct pl08x_dma_chan *ch)
67
+
{
68
+
const struct pl08x_channel_data *cd = ch->cd;
69
+
unsigned long flags;
70
+
71
+
spin_lock_irqsave(&lock, flags);
72
+
73
+
/* if signal is not used */
74
+
if (!signals[cd->min_signal].busy)
75
+
BUG();
76
+
77
+
signals[cd->min_signal].busy--;
78
+
79
+
spin_unlock_irqrestore(&lock, flags);
80
+
}
+1
-1
arch/arm/plat-spear/restart.c
+1
-1
arch/arm/plat-spear/restart.c
+27
-15
arch/arm/plat-spear/time.c
+27
-15
arch/arm/plat-spear/time.c
···
15
15
#include <linux/err.h>
16
16
#include <linux/init.h>
17
17
#include <linux/interrupt.h>
18
+
#include <linux/ioport.h>
18
19
#include <linux/io.h>
19
20
#include <linux/kernel.h>
21
+
#include <linux/of_irq.h>
22
+
#include <linux/of_address.h>
20
23
#include <linux/time.h>
21
24
#include <linux/irq.h>
22
25
#include <asm/mach/time.h>
23
26
#include <mach/generic.h>
24
-
#include <mach/hardware.h>
25
-
#include <mach/irqs.h>
26
27
27
28
/*
28
29
* We would use TIMER0 and TIMER1 as clockevent and clocksource.
···
176
175
.handler = spear_timer_interrupt
177
176
};
178
177
179
-
static void __init spear_clockevent_init(void)
178
+
static void __init spear_clockevent_init(int irq)
180
179
{
181
180
u32 tick_rate;
182
181
···
196
195
197
196
clockevents_register_device(&clkevt);
198
197
199
-
setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
198
+
setup_irq(irq, &spear_timer_irq);
200
199
}
201
200
202
-
void __init spear_setup_timer(void)
203
-
{
204
-
int ret;
201
+
const static struct of_device_id timer_of_match[] __initconst = {
202
+
{ .compatible = "st,spear-timer", },
203
+
{ },
204
+
};
205
205
206
-
if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
207
-
pr_err("%s:cannot get IO addr\n", __func__);
206
+
void __init spear_setup_of_timer(void)
207
+
{
208
+
struct device_node *np;
209
+
int irq, ret;
210
+
211
+
np = of_find_matching_node(NULL, timer_of_match);
212
+
if (!np) {
213
+
pr_err("%s: No timer passed via DT\n", __func__);
208
214
return;
209
215
}
210
216
211
-
gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
217
+
irq = irq_of_parse_and_map(np, 0);
218
+
if (!irq) {
219
+
pr_err("%s: No irq passed for timer via DT\n", __func__);
220
+
return;
221
+
}
222
+
223
+
gpt_base = of_iomap(np, 0);
212
224
if (!gpt_base) {
213
-
pr_err("%s:ioremap failed for gpt\n", __func__);
214
-
goto err_mem;
225
+
pr_err("%s: of iomap failed\n", __func__);
226
+
return;
215
227
}
216
228
217
229
gpt_clk = clk_get_sys("gpt0", NULL);
···
239
225
goto err_prepare_enable_clk;
240
226
}
241
227
242
-
spear_clockevent_init();
228
+
spear_clockevent_init(irq);
243
229
spear_clocksource_init();
244
230
245
231
return;
···
248
234
clk_put(gpt_clk);
249
235
err_iomap:
250
236
iounmap(gpt_base);
251
-
err_mem:
252
-
release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
253
237
}
+8
drivers/i2c/busses/i2c-imx.c
+8
drivers/i2c/busses/i2c-imx.c
···
51
51
#include <linux/of.h>
52
52
#include <linux/of_device.h>
53
53
#include <linux/of_i2c.h>
54
+
#include <linux/pinctrl/consumer.h>
54
55
55
56
#include <mach/irqs.h>
56
57
#include <mach/hardware.h>
···
471
470
struct imx_i2c_struct *i2c_imx;
472
471
struct resource *res;
473
472
struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
473
+
struct pinctrl *pinctrl;
474
474
void __iomem *base;
475
475
resource_size_t res_size;
476
476
int irq, bitrate;
···
521
519
i2c_imx->irq = irq;
522
520
i2c_imx->base = base;
523
521
i2c_imx->res = res;
522
+
523
+
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
524
+
if (IS_ERR(pinctrl)) {
525
+
ret = PTR_ERR(pinctrl);
526
+
goto fail3;
527
+
}
524
528
525
529
/* Get I2C clock */
526
530
i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
+6
drivers/i2c/busses/i2c-mxs.c
+6
drivers/i2c/busses/i2c-mxs.c
···
26
26
#include <linux/platform_device.h>
27
27
#include <linux/jiffies.h>
28
28
#include <linux/io.h>
29
+
#include <linux/pinctrl/consumer.h>
29
30
30
31
#include <mach/common.h>
31
32
···
326
325
struct device *dev = &pdev->dev;
327
326
struct mxs_i2c_dev *i2c;
328
327
struct i2c_adapter *adap;
328
+
struct pinctrl *pinctrl;
329
329
struct resource *res;
330
330
resource_size_t res_size;
331
331
int err, irq;
332
+
333
+
pinctrl = devm_pinctrl_get_select_default(dev);
334
+
if (IS_ERR(pinctrl))
335
+
return PTR_ERR(pinctrl);
332
336
333
337
i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
334
338
if (!i2c)
+8
drivers/mmc/host/mxs-mmc.c
+8
drivers/mmc/host/mxs-mmc.c
···
39
39
#include <linux/regulator/consumer.h>
40
40
#include <linux/module.h>
41
41
#include <linux/fsl/mxs-dma.h>
42
+
#include <linux/pinctrl/consumer.h>
42
43
43
44
#include <mach/mxs.h>
44
45
#include <mach/common.h>
···
683
682
struct mmc_host *mmc;
684
683
struct resource *iores, *dmares, *r;
685
684
struct mxs_mmc_platform_data *pdata;
685
+
struct pinctrl *pinctrl;
686
686
int ret = 0, irq_err, irq_dma;
687
687
dma_cap_mask_t mask;
688
688
···
720
718
host->dma_res = dmares;
721
719
host->irq = irq_err;
722
720
host->sdio_irq_en = 0;
721
+
722
+
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
723
+
if (IS_ERR(pinctrl)) {
724
+
ret = PTR_ERR(pinctrl);
725
+
goto out_iounmap;
726
+
}
723
727
724
728
host->clk = clk_get(&pdev->dev, NULL);
725
729
if (IS_ERR(host->clk)) {
+9
drivers/mmc/host/sdhci-esdhc-imx.c
+9
drivers/mmc/host/sdhci-esdhc-imx.c
···
24
24
#include <linux/of.h>
25
25
#include <linux/of_device.h>
26
26
#include <linux/of_gpio.h>
27
+
#include <linux/pinctrl/consumer.h>
27
28
#include <mach/esdhc.h>
28
29
#include "sdhci-pltfm.h"
29
30
#include "sdhci-esdhc.h"
···
69
68
int flags;
70
69
u32 scratchpad;
71
70
enum imx_esdhc_type devtype;
71
+
struct pinctrl *pinctrl;
72
72
struct esdhc_platform_data boarddata;
73
73
struct clk *clk_ipg;
74
74
struct clk *clk_ahb;
···
486
484
clk_prepare_enable(imx_data->clk_ipg);
487
485
clk_prepare_enable(imx_data->clk_ahb);
488
486
487
+
imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
488
+
if (IS_ERR(imx_data->pinctrl)) {
489
+
err = PTR_ERR(imx_data->pinctrl);
490
+
goto pin_err;
491
+
}
492
+
489
493
host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
490
494
491
495
if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
···
583
575
gpio_free(boarddata->wp_gpio);
584
576
no_card_detect_pin:
585
577
no_board_data:
578
+
pin_err:
586
579
clk_disable_unprepare(imx_data->clk_per);
587
580
clk_disable_unprepare(imx_data->clk_ipg);
588
581
clk_disable_unprepare(imx_data->clk_ahb);
+9
drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+9
drivers/mtd/nand/gpmi-nand/gpmi-nand.c
···
24
24
#include <linux/module.h>
25
25
#include <linux/mtd/gpmi-nand.h>
26
26
#include <linux/mtd/partitions.h>
27
+
#include <linux/pinctrl/consumer.h>
27
28
#include "gpmi-nand.h"
28
29
29
30
/* add our owner bbt descriptor */
···
477
476
static int __devinit acquire_resources(struct gpmi_nand_data *this)
478
477
{
479
478
struct resources *res = &this->resources;
479
+
struct pinctrl *pinctrl;
480
480
int ret;
481
481
482
482
ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME);
···
496
494
if (ret)
497
495
goto exit_dma_channels;
498
496
497
+
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
498
+
if (IS_ERR(pinctrl)) {
499
+
ret = PTR_ERR(pinctrl);
500
+
goto exit_pin;
501
+
}
502
+
499
503
res->clock = clk_get(&this->pdev->dev, NULL);
500
504
if (IS_ERR(res->clock)) {
501
505
pr_err("can not get the clock\n");
···
511
503
return 0;
512
504
513
505
exit_clock:
506
+
exit_pin:
514
507
release_dma_channels(this);
515
508
exit_dma_channels:
516
509
release_bch_irq(this);
+6
drivers/net/can/flexcan.c
+6
drivers/net/can/flexcan.c
···
35
35
#include <linux/module.h>
36
36
#include <linux/of.h>
37
37
#include <linux/platform_device.h>
38
+
#include <linux/pinctrl/consumer.h>
38
39
39
40
#define DRV_NAME "flexcan"
40
41
···
928
927
struct flexcan_priv *priv;
929
928
struct resource *mem;
930
929
struct clk *clk = NULL;
930
+
struct pinctrl *pinctrl;
931
931
void __iomem *base;
932
932
resource_size_t mem_size;
933
933
int err, irq;
934
934
u32 clock_freq = 0;
935
+
936
+
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
937
+
if (IS_ERR(pinctrl))
938
+
return PTR_ERR(pinctrl);
935
939
936
940
if (pdev->dev.of_node) {
937
941
const u32 *clock_freq_p;
+9
drivers/net/ethernet/freescale/fec.c
+9
drivers/net/ethernet/freescale/fec.c
···
48
48
#include <linux/of_device.h>
49
49
#include <linux/of_gpio.h>
50
50
#include <linux/of_net.h>
51
+
#include <linux/pinctrl/consumer.h>
51
52
52
53
#include <asm/cacheflush.h>
53
54
···
1544
1543
struct resource *r;
1545
1544
const struct of_device_id *of_id;
1546
1545
static int dev_id;
1546
+
struct pinctrl *pinctrl;
1547
1547
1548
1548
of_id = of_match_device(fec_dt_ids, &pdev->dev);
1549
1549
if (of_id)
···
1612
1610
}
1613
1611
}
1614
1612
1613
+
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1614
+
if (IS_ERR(pinctrl)) {
1615
+
ret = PTR_ERR(pinctrl);
1616
+
goto failed_pin;
1617
+
}
1618
+
1615
1619
fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1616
1620
if (IS_ERR(fep->clk_ipg)) {
1617
1621
ret = PTR_ERR(fep->clk_ipg);
···
1656
1648
failed_init:
1657
1649
clk_disable_unprepare(fep->clk_ahb);
1658
1650
clk_disable_unprepare(fep->clk_ipg);
1651
+
failed_pin:
1659
1652
failed_clk:
1660
1653
for (i = 0; i < FEC_IRQ_NUM; i++) {
1661
1654
irq = platform_get_irq(pdev, i);
+1
drivers/of/address.c
+1
drivers/of/address.c
+41
drivers/of/base.c
+41
drivers/of/base.c
···
1260
1260
return id;
1261
1261
}
1262
1262
EXPORT_SYMBOL_GPL(of_alias_get_id);
1263
+
1264
+
const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
1265
+
u32 *pu)
1266
+
{
1267
+
const void *curv = cur;
1268
+
1269
+
if (!prop)
1270
+
return NULL;
1271
+
1272
+
if (!cur) {
1273
+
curv = prop->value;
1274
+
goto out_val;
1275
+
}
1276
+
1277
+
curv += sizeof(*cur);
1278
+
if (curv >= prop->value + prop->length)
1279
+
return NULL;
1280
+
1281
+
out_val:
1282
+
*pu = be32_to_cpup(curv);
1283
+
return curv;
1284
+
}
1285
+
EXPORT_SYMBOL_GPL(of_prop_next_u32);
1286
+
1287
+
const char *of_prop_next_string(struct property *prop, const char *cur)
1288
+
{
1289
+
const void *curv = cur;
1290
+
1291
+
if (!prop)
1292
+
return NULL;
1293
+
1294
+
if (!cur)
1295
+
return prop->value;
1296
+
1297
+
curv += strlen(cur) + 1;
1298
+
if (curv >= prop->value + prop->length)
1299
+
return NULL;
1300
+
1301
+
return curv;
1302
+
}
1303
+
EXPORT_SYMBOL_GPL(of_prop_next_string);
+30
-1
drivers/pinctrl/Kconfig
+30
-1
drivers/pinctrl/Kconfig
···
4
4
5
5
config PINCTRL
6
6
bool
7
-
depends on EXPERIMENTAL
8
7
9
8
if PINCTRL
10
9
···
26
27
help
27
28
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
28
29
30
+
config PINCTRL_IMX
31
+
bool
32
+
select PINMUX
33
+
select PINCONF
34
+
35
+
config PINCTRL_IMX6Q
36
+
bool "IMX6Q pinctrl driver"
37
+
depends on OF
38
+
depends on SOC_IMX6Q
39
+
select PINCTRL_IMX
40
+
help
41
+
Say Y here to enable the imx6q pinctrl driver
42
+
29
43
config PINCTRL_PXA3xx
30
44
bool
31
45
select PINMUX
···
48
36
depends on ARCH_MMP
49
37
select PINCTRL_PXA3xx
50
38
select PINCONF
39
+
40
+
config PINCTRL_MXS
41
+
bool
42
+
43
+
config PINCTRL_IMX23
44
+
bool
45
+
select PINMUX
46
+
select PINCONF
47
+
select PINCTRL_MXS
48
+
49
+
config PINCTRL_IMX28
50
+
bool
51
+
select PINMUX
52
+
select PINCONF
53
+
select PINCTRL_MXS
51
54
52
55
config PINCTRL_PXA168
53
56
bool "PXA168 pin controller driver"
···
110
83
The names of the two IP block variants supported are
111
84
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
112
85
ports of 8 GPIO pins each.
86
+
87
+
source "drivers/pinctrl/spear/Kconfig"
113
88
114
89
endmenu
115
90
+10
drivers/pinctrl/Makefile
+10
drivers/pinctrl/Makefile
···
5
5
obj-$(CONFIG_PINCTRL) += core.o
6
6
obj-$(CONFIG_PINMUX) += pinmux.o
7
7
obj-$(CONFIG_PINCONF) += pinconf.o
8
+
ifeq ($(CONFIG_OF),y)
9
+
obj-$(CONFIG_PINCTRL) += devicetree.o
10
+
endif
8
11
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12
+
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
13
+
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
9
14
obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
10
15
obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
16
+
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
17
+
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
18
+
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
11
19
obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
12
20
obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
13
21
obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
···
24
16
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
25
17
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
26
18
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
19
+
20
+
obj-$(CONFIG_PLAT_SPEAR) += spear/
+196
-48
drivers/pinctrl/core.c
+196
-48
drivers/pinctrl/core.c
···
23
23
#include <linux/sysfs.h>
24
24
#include <linux/debugfs.h>
25
25
#include <linux/seq_file.h>
26
+
#include <linux/pinctrl/consumer.h>
26
27
#include <linux/pinctrl/pinctrl.h>
27
28
#include <linux/pinctrl/machine.h>
28
29
#include "core.h"
30
+
#include "devicetree.h"
29
31
#include "pinmux.h"
30
32
#include "pinconf.h"
31
33
···
43
41
unsigned num_maps;
44
42
};
45
43
44
+
static bool pinctrl_dummy_state;
45
+
46
46
/* Mutex taken by all entry points */
47
47
DEFINE_MUTEX(pinctrl_mutex);
48
48
49
49
/* Global list of pin control devices (struct pinctrl_dev) */
50
-
static LIST_HEAD(pinctrldev_list);
50
+
LIST_HEAD(pinctrldev_list);
51
51
52
52
/* List of pin controller handles (struct pinctrl) */
53
53
static LIST_HEAD(pinctrl_list);
···
62
58
for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \
63
59
_i_ < _maps_node_->num_maps; \
64
60
i++, _map_ = &_maps_node_->maps[_i_])
61
+
62
+
/**
63
+
* pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
64
+
*
65
+
* Usually this function is called by platforms without pinctrl driver support
66
+
* but run with some shared drivers using pinctrl APIs.
67
+
* After calling this function, the pinctrl core will return successfully
68
+
* with creating a dummy state for the driver to keep going smoothly.
69
+
*/
70
+
void pinctrl_provide_dummies(void)
71
+
{
72
+
pinctrl_dummy_state = true;
73
+
}
65
74
66
75
const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
67
76
{
···
138
121
}
139
122
140
123
return -EINVAL;
124
+
}
125
+
126
+
/**
127
+
* pin_get_name_from_id() - look up a pin name from a pin id
128
+
* @pctldev: the pin control device to lookup the pin on
129
+
* @name: the name of the pin to look up
130
+
*/
131
+
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
132
+
{
133
+
const struct pin_desc *desc;
134
+
135
+
desc = pin_desc_get(pctldev, pin);
136
+
if (desc == NULL) {
137
+
dev_err(pctldev->dev, "failed to get pin(%d) name\n",
138
+
pin);
139
+
return NULL;
140
+
}
141
+
142
+
return desc->name;
141
143
}
142
144
143
145
/**
···
291
255
*
292
256
* Find the pin controller handling a certain GPIO pin from the pinspace of
293
257
* the GPIO subsystem, return the device and the matching GPIO range. Returns
294
-
* negative if the GPIO range could not be found in any device.
258
+
* -EPROBE_DEFER if the GPIO range could not be found in any device since it
259
+
* may still have not been registered.
295
260
*/
296
261
static int pinctrl_get_device_gpio_range(unsigned gpio,
297
262
struct pinctrl_dev **outdev,
···
312
275
}
313
276
}
314
277
315
-
return -EINVAL;
278
+
return -EPROBE_DEFER;
316
279
}
317
280
318
281
/**
···
355
318
const char *pin_group)
356
319
{
357
320
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
321
+
unsigned ngroups = pctlops->get_groups_count(pctldev);
358
322
unsigned group_selector = 0;
359
323
360
-
while (pctlops->list_groups(pctldev, group_selector) >= 0) {
324
+
while (group_selector < ngroups) {
361
325
const char *gname = pctlops->get_group_name(pctldev,
362
326
group_selector);
363
327
if (!strcmp(gname, pin_group)) {
···
398
360
ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
399
361
if (ret) {
400
362
mutex_unlock(&pinctrl_mutex);
401
-
return -EINVAL;
363
+
return ret;
402
364
}
403
365
404
366
/* Convert to the pin controllers number space */
···
554
516
555
517
setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
556
518
if (setting->pctldev == NULL) {
557
-
dev_err(p->dev, "unknown pinctrl device %s in map entry",
519
+
dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
558
520
map->ctrl_dev_name);
559
521
kfree(setting);
560
-
/* Eventually, this should trigger deferred probe */
561
-
return -ENODEV;
522
+
/*
523
+
* OK let us guess that the driver is not there yet, and
524
+
* let's defer obtaining this pinctrl handle to later...
525
+
*/
526
+
return -EPROBE_DEFER;
562
527
}
563
528
564
529
switch (map->type) {
···
620
579
}
621
580
p->dev = dev;
622
581
INIT_LIST_HEAD(&p->states);
582
+
INIT_LIST_HEAD(&p->dt_maps);
583
+
584
+
ret = pinctrl_dt_to_map(p);
585
+
if (ret < 0) {
586
+
kfree(p);
587
+
return ERR_PTR(ret);
588
+
}
623
589
624
590
devname = dev_name(dev);
625
591
···
710
662
kfree(state);
711
663
}
712
664
665
+
pinctrl_dt_free_maps(p);
666
+
713
667
if (inlist)
714
668
list_del(&p->node);
715
669
kfree(p);
···
735
685
struct pinctrl_state *state;
736
686
737
687
state = find_state(p, name);
738
-
if (!state)
739
-
return ERR_PTR(-ENODEV);
688
+
if (!state) {
689
+
if (pinctrl_dummy_state) {
690
+
/* create dummy state */
691
+
dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
692
+
name);
693
+
state = create_state(p, name);
694
+
if (IS_ERR(state))
695
+
return state;
696
+
} else {
697
+
return ERR_PTR(-ENODEV);
698
+
}
699
+
}
740
700
741
701
return state;
742
702
}
···
847
787
}
848
788
EXPORT_SYMBOL_GPL(pinctrl_select_state);
849
789
790
+
static void devm_pinctrl_release(struct device *dev, void *res)
791
+
{
792
+
pinctrl_put(*(struct pinctrl **)res);
793
+
}
794
+
850
795
/**
851
-
* pinctrl_register_mappings() - register a set of pin controller mappings
852
-
* @maps: the pincontrol mappings table to register. This should probably be
853
-
* marked with __initdata so it can be discarded after boot. This
854
-
* function will perform a shallow copy for the mapping entries.
855
-
* @num_maps: the number of maps in the mapping table
796
+
* struct devm_pinctrl_get() - Resource managed pinctrl_get()
797
+
* @dev: the device to obtain the handle for
798
+
*
799
+
* If there is a need to explicitly destroy the returned struct pinctrl,
800
+
* devm_pinctrl_put() should be used, rather than plain pinctrl_put().
856
801
*/
857
-
int pinctrl_register_mappings(struct pinctrl_map const *maps,
858
-
unsigned num_maps)
802
+
struct pinctrl *devm_pinctrl_get(struct device *dev)
803
+
{
804
+
struct pinctrl **ptr, *p;
805
+
806
+
ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
807
+
if (!ptr)
808
+
return ERR_PTR(-ENOMEM);
809
+
810
+
p = pinctrl_get(dev);
811
+
if (!IS_ERR(p)) {
812
+
*ptr = p;
813
+
devres_add(dev, ptr);
814
+
} else {
815
+
devres_free(ptr);
816
+
}
817
+
818
+
return p;
819
+
}
820
+
EXPORT_SYMBOL_GPL(devm_pinctrl_get);
821
+
822
+
static int devm_pinctrl_match(struct device *dev, void *res, void *data)
823
+
{
824
+
struct pinctrl **p = res;
825
+
826
+
return *p == data;
827
+
}
828
+
829
+
/**
830
+
* devm_pinctrl_put() - Resource managed pinctrl_put()
831
+
* @p: the pinctrl handle to release
832
+
*
833
+
* Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally
834
+
* this function will not need to be called and the resource management
835
+
* code will ensure that the resource is freed.
836
+
*/
837
+
void devm_pinctrl_put(struct pinctrl *p)
838
+
{
839
+
WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
840
+
devm_pinctrl_match, p));
841
+
pinctrl_put(p);
842
+
}
843
+
EXPORT_SYMBOL_GPL(devm_pinctrl_put);
844
+
845
+
int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
846
+
bool dup, bool locked)
859
847
{
860
848
int i, ret;
861
849
struct pinctrl_maps *maps_node;
···
937
829
case PIN_MAP_TYPE_MUX_GROUP:
938
830
ret = pinmux_validate_map(&maps[i], i);
939
831
if (ret < 0)
940
-
return 0;
832
+
return ret;
941
833
break;
942
834
case PIN_MAP_TYPE_CONFIGS_PIN:
943
835
case PIN_MAP_TYPE_CONFIGS_GROUP:
944
836
ret = pinconf_validate_map(&maps[i], i);
945
837
if (ret < 0)
946
-
return 0;
838
+
return ret;
947
839
break;
948
840
default:
949
841
pr_err("failed to register map %s (%d): invalid type given\n",
···
959
851
}
960
852
961
853
maps_node->num_maps = num_maps;
962
-
maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL);
963
-
if (!maps_node->maps) {
964
-
pr_err("failed to duplicate mapping table\n");
965
-
kfree(maps_node);
966
-
return -ENOMEM;
854
+
if (dup) {
855
+
maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
856
+
GFP_KERNEL);
857
+
if (!maps_node->maps) {
858
+
pr_err("failed to duplicate mapping table\n");
859
+
kfree(maps_node);
860
+
return -ENOMEM;
861
+
}
862
+
} else {
863
+
maps_node->maps = maps;
967
864
}
968
865
969
-
mutex_lock(&pinctrl_mutex);
866
+
if (!locked)
867
+
mutex_lock(&pinctrl_mutex);
970
868
list_add_tail(&maps_node->node, &pinctrl_maps);
971
-
mutex_unlock(&pinctrl_mutex);
869
+
if (!locked)
870
+
mutex_unlock(&pinctrl_mutex);
972
871
973
872
return 0;
873
+
}
874
+
875
+
/**
876
+
* pinctrl_register_mappings() - register a set of pin controller mappings
877
+
* @maps: the pincontrol mappings table to register. This should probably be
878
+
* marked with __initdata so it can be discarded after boot. This
879
+
* function will perform a shallow copy for the mapping entries.
880
+
* @num_maps: the number of maps in the mapping table
881
+
*/
882
+
int pinctrl_register_mappings(struct pinctrl_map const *maps,
883
+
unsigned num_maps)
884
+
{
885
+
return pinctrl_register_map(maps, num_maps, true, false);
886
+
}
887
+
888
+
void pinctrl_unregister_map(struct pinctrl_map const *map)
889
+
{
890
+
struct pinctrl_maps *maps_node;
891
+
892
+
list_for_each_entry(maps_node, &pinctrl_maps, node) {
893
+
if (maps_node->maps == map) {
894
+
list_del(&maps_node->node);
895
+
return;
896
+
}
897
+
}
974
898
}
975
899
976
900
#ifdef CONFIG_DEBUG_FS
···
1046
906
{
1047
907
struct pinctrl_dev *pctldev = s->private;
1048
908
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
1049
-
unsigned selector = 0;
909
+
unsigned ngroups, selector = 0;
1050
910
911
+
ngroups = ops->get_groups_count(pctldev);
1051
912
mutex_lock(&pinctrl_mutex);
1052
913
1053
914
seq_puts(s, "registered pin groups:\n");
1054
-
while (ops->list_groups(pctldev, selector) >= 0) {
915
+
while (selector < ngroups) {
1055
916
const unsigned *pins;
1056
917
unsigned num_pins;
1057
918
const char *gname = ops->get_group_name(pctldev, selector);
919
+
const char *pname;
1058
920
int ret;
1059
921
int i;
1060
922
···
1066
924
seq_printf(s, "%s [ERROR GETTING PINS]\n",
1067
925
gname);
1068
926
else {
1069
-
seq_printf(s, "group: %s, pins = [ ", gname);
1070
-
for (i = 0; i < num_pins; i++)
1071
-
seq_printf(s, "%d ", pins[i]);
1072
-
seq_puts(s, "]\n");
927
+
seq_printf(s, "group: %s\n", gname);
928
+
for (i = 0; i < num_pins; i++) {
929
+
pname = pin_get_name(pctldev, pins[i]);
930
+
if (WARN_ON(!pname))
931
+
return -EINVAL;
932
+
seq_printf(s, "pin %d (%s)\n", pins[i], pname);
933
+
}
934
+
seq_puts(s, "\n");
1073
935
}
1074
936
selector++;
1075
937
}
···
1372
1226
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
1373
1227
1374
1228
if (!ops ||
1375
-
!ops->list_groups ||
1229
+
!ops->get_groups_count ||
1376
1230
!ops->get_group_name ||
1377
1231
!ops->get_group_pins)
1232
+
return -EINVAL;
1233
+
1234
+
if (ops->dt_node_to_map && !ops->dt_free_map)
1378
1235
return -EINVAL;
1379
1236
1380
1237
return 0;
···
1417
1268
/* check core ops for sanity */
1418
1269
ret = pinctrl_check_ops(pctldev);
1419
1270
if (ret) {
1420
-
pr_err("%s pinctrl ops lacks necessary functions\n",
1421
-
pctldesc->name);
1271
+
dev_err(dev, "pinctrl ops lacks necessary functions\n");
1422
1272
goto out_err;
1423
1273
}
1424
1274
1425
1275
/* If we're implementing pinmuxing, check the ops for sanity */
1426
1276
if (pctldesc->pmxops) {
1427
1277
ret = pinmux_check_ops(pctldev);
1428
-
if (ret) {
1429
-
pr_err("%s pinmux ops lacks necessary functions\n",
1430
-
pctldesc->name);
1278
+
if (ret)
1431
1279
goto out_err;
1432
-
}
1433
1280
}
1434
1281
1435
1282
/* If we're implementing pinconfig, check the ops for sanity */
1436
1283
if (pctldesc->confops) {
1437
1284
ret = pinconf_check_ops(pctldev);
1438
-
if (ret) {
1439
-
pr_err("%s pin config ops lacks necessary functions\n",
1440
-
pctldesc->name);
1285
+
if (ret)
1441
1286
goto out_err;
1442
-
}
1443
1287
}
1444
1288
1445
1289
/* Register all the pins */
1446
-
pr_debug("try to register %d pins on %s...\n",
1447
-
pctldesc->npins, pctldesc->name);
1290
+
dev_dbg(dev, "try to register %d pins ...\n", pctldesc->npins);
1448
1291
ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
1449
1292
if (ret) {
1450
-
pr_err("error during pin registration\n");
1293
+
dev_err(dev, "error during pin registration\n");
1451
1294
pinctrl_free_pindescs(pctldev, pctldesc->pins,
1452
1295
pctldesc->npins);
1453
1296
goto out_err;
···
1454
1313
struct pinctrl_state *s =
1455
1314
pinctrl_lookup_state_locked(pctldev->p,
1456
1315
PINCTRL_STATE_DEFAULT);
1457
-
if (!IS_ERR(s))
1458
-
pinctrl_select_state_locked(pctldev->p, s);
1316
+
if (IS_ERR(s)) {
1317
+
dev_dbg(dev, "failed to lookup the default state\n");
1318
+
} else {
1319
+
ret = pinctrl_select_state_locked(pctldev->p, s);
1320
+
if (ret) {
1321
+
dev_err(dev,
1322
+
"failed to select default state\n");
1323
+
}
1324
+
}
1459
1325
}
1460
1326
1461
1327
mutex_unlock(&pinctrl_mutex);
+11
-1
drivers/pinctrl/core.h
+11
-1
drivers/pinctrl/core.h
···
52
52
* @dev: the device using this pin control handle
53
53
* @states: a list of states for this device
54
54
* @state: the current state
55
+
* @dt_maps: the mapping table chunks dynamically parsed from device tree for
56
+
* this device, if any
55
57
*/
56
58
struct pinctrl {
57
59
struct list_head node;
58
60
struct device *dev;
59
61
struct list_head states;
60
62
struct pinctrl_state *state;
63
+
struct list_head dt_maps;
61
64
};
62
65
63
66
/**
···
103
100
* struct pinctrl_setting - an individual mux or config setting
104
101
* @node: list node for struct pinctrl_settings's @settings field
105
102
* @type: the type of setting
106
-
* @pctldev: pin control device handling to be programmed
103
+
* @pctldev: pin control device handling to be programmed. Not used for
104
+
* PIN_MAP_TYPE_DUMMY_STATE.
107
105
* @data: Data specific to the setting type
108
106
*/
109
107
struct pinctrl_setting {
···
148
144
149
145
struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
150
146
int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
147
+
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
151
148
int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
152
149
const char *pin_group);
153
150
···
158
153
return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
159
154
}
160
155
156
+
int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
157
+
bool dup, bool locked);
158
+
void pinctrl_unregister_map(struct pinctrl_map const *map);
159
+
161
160
extern struct mutex pinctrl_mutex;
161
+
extern struct list_head pinctrldev_list;
+249
drivers/pinctrl/devicetree.c
+249
drivers/pinctrl/devicetree.c
···
1
+
/*
2
+
* Device tree integration for the pin control subsystem
3
+
*
4
+
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify it
7
+
* under the terms and conditions of the GNU General Public License,
8
+
* version 2, as published by the Free Software Foundation.
9
+
*
10
+
* This program is distributed in the hope it will be useful, but WITHOUT
11
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13
+
* more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
17
+
*/
18
+
19
+
#include <linux/device.h>
20
+
#include <linux/of.h>
21
+
#include <linux/pinctrl/pinctrl.h>
22
+
#include <linux/slab.h>
23
+
24
+
#include "core.h"
25
+
#include "devicetree.h"
26
+
27
+
/**
28
+
* struct pinctrl_dt_map - mapping table chunk parsed from device tree
29
+
* @node: list node for struct pinctrl's @dt_maps field
30
+
* @pctldev: the pin controller that allocated this struct, and will free it
31
+
* @maps: the mapping table entries
32
+
*/
33
+
struct pinctrl_dt_map {
34
+
struct list_head node;
35
+
struct pinctrl_dev *pctldev;
36
+
struct pinctrl_map *map;
37
+
unsigned num_maps;
38
+
};
39
+
40
+
static void dt_free_map(struct pinctrl_dev *pctldev,
41
+
struct pinctrl_map *map, unsigned num_maps)
42
+
{
43
+
if (pctldev) {
44
+
struct pinctrl_ops *ops = pctldev->desc->pctlops;
45
+
ops->dt_free_map(pctldev, map, num_maps);
46
+
} else {
47
+
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
48
+
kfree(map);
49
+
}
50
+
}
51
+
52
+
void pinctrl_dt_free_maps(struct pinctrl *p)
53
+
{
54
+
struct pinctrl_dt_map *dt_map, *n1;
55
+
56
+
list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
57
+
pinctrl_unregister_map(dt_map->map);
58
+
list_del(&dt_map->node);
59
+
dt_free_map(dt_map->pctldev, dt_map->map,
60
+
dt_map->num_maps);
61
+
kfree(dt_map);
62
+
}
63
+
64
+
of_node_put(p->dev->of_node);
65
+
}
66
+
67
+
static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
68
+
struct pinctrl_dev *pctldev,
69
+
struct pinctrl_map *map, unsigned num_maps)
70
+
{
71
+
int i;
72
+
struct pinctrl_dt_map *dt_map;
73
+
74
+
/* Initialize common mapping table entry fields */
75
+
for (i = 0; i < num_maps; i++) {
76
+
map[i].dev_name = dev_name(p->dev);
77
+
map[i].name = statename;
78
+
if (pctldev)
79
+
map[i].ctrl_dev_name = dev_name(pctldev->dev);
80
+
}
81
+
82
+
/* Remember the converted mapping table entries */
83
+
dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
84
+
if (!dt_map) {
85
+
dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n");
86
+
dt_free_map(pctldev, map, num_maps);
87
+
return -ENOMEM;
88
+
}
89
+
90
+
dt_map->pctldev = pctldev;
91
+
dt_map->map = map;
92
+
dt_map->num_maps = num_maps;
93
+
list_add_tail(&dt_map->node, &p->dt_maps);
94
+
95
+
return pinctrl_register_map(map, num_maps, false, true);
96
+
}
97
+
98
+
static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np)
99
+
{
100
+
struct pinctrl_dev *pctldev;
101
+
102
+
list_for_each_entry(pctldev, &pinctrldev_list, node)
103
+
if (pctldev->dev->of_node == np)
104
+
return pctldev;
105
+
106
+
return NULL;
107
+
}
108
+
109
+
static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
110
+
struct device_node *np_config)
111
+
{
112
+
struct device_node *np_pctldev;
113
+
struct pinctrl_dev *pctldev;
114
+
struct pinctrl_ops *ops;
115
+
int ret;
116
+
struct pinctrl_map *map;
117
+
unsigned num_maps;
118
+
119
+
/* Find the pin controller containing np_config */
120
+
np_pctldev = of_node_get(np_config);
121
+
for (;;) {
122
+
np_pctldev = of_get_next_parent(np_pctldev);
123
+
if (!np_pctldev || of_node_is_root(np_pctldev)) {
124
+
dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n",
125
+
np_config->full_name);
126
+
of_node_put(np_pctldev);
127
+
/* OK let's just assume this will appear later then */
128
+
return -EPROBE_DEFER;
129
+
}
130
+
pctldev = find_pinctrl_by_of_node(np_pctldev);
131
+
if (pctldev)
132
+
break;
133
+
}
134
+
of_node_put(np_pctldev);
135
+
136
+
/*
137
+
* Call pinctrl driver to parse device tree node, and
138
+
* generate mapping table entries
139
+
*/
140
+
ops = pctldev->desc->pctlops;
141
+
if (!ops->dt_node_to_map) {
142
+
dev_err(p->dev, "pctldev %s doesn't support DT\n",
143
+
dev_name(pctldev->dev));
144
+
return -ENODEV;
145
+
}
146
+
ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
147
+
if (ret < 0)
148
+
return ret;
149
+
150
+
/* Stash the mapping table chunk away for later use */
151
+
return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
152
+
}
153
+
154
+
static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
155
+
{
156
+
struct pinctrl_map *map;
157
+
158
+
map = kzalloc(sizeof(*map), GFP_KERNEL);
159
+
if (!map) {
160
+
dev_err(p->dev, "failed to alloc struct pinctrl_map\n");
161
+
return -ENOMEM;
162
+
}
163
+
164
+
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
165
+
map->type = PIN_MAP_TYPE_DUMMY_STATE;
166
+
167
+
return dt_remember_or_free_map(p, statename, NULL, map, 1);
168
+
}
169
+
170
+
int pinctrl_dt_to_map(struct pinctrl *p)
171
+
{
172
+
struct device_node *np = p->dev->of_node;
173
+
int state, ret;
174
+
char *propname;
175
+
struct property *prop;
176
+
const char *statename;
177
+
const __be32 *list;
178
+
int size, config;
179
+
phandle phandle;
180
+
struct device_node *np_config;
181
+
182
+
/* CONFIG_OF enabled, p->dev not instantiated from DT */
183
+
if (!np) {
184
+
dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n");
185
+
return 0;
186
+
}
187
+
188
+
/* We may store pointers to property names within the node */
189
+
of_node_get(np);
190
+
191
+
/* For each defined state ID */
192
+
for (state = 0; ; state++) {
193
+
/* Retrieve the pinctrl-* property */
194
+
propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
195
+
prop = of_find_property(np, propname, &size);
196
+
kfree(propname);
197
+
if (!prop)
198
+
break;
199
+
list = prop->value;
200
+
size /= sizeof(*list);
201
+
202
+
/* Determine whether pinctrl-names property names the state */
203
+
ret = of_property_read_string_index(np, "pinctrl-names",
204
+
state, &statename);
205
+
/*
206
+
* If not, statename is just the integer state ID. But rather
207
+
* than dynamically allocate it and have to free it later,
208
+
* just point part way into the property name for the string.
209
+
*/
210
+
if (ret < 0) {
211
+
/* strlen("pinctrl-") == 8 */
212
+
statename = prop->name + 8;
213
+
}
214
+
215
+
/* For every referenced pin configuration node in it */
216
+
for (config = 0; config < size; config++) {
217
+
phandle = be32_to_cpup(list++);
218
+
219
+
/* Look up the pin configuration node */
220
+
np_config = of_find_node_by_phandle(phandle);
221
+
if (!np_config) {
222
+
dev_err(p->dev,
223
+
"prop %s index %i invalid phandle\n",
224
+
prop->name, config);
225
+
ret = -EINVAL;
226
+
goto err;
227
+
}
228
+
229
+
/* Parse the node */
230
+
ret = dt_to_map_one_config(p, statename, np_config);
231
+
of_node_put(np_config);
232
+
if (ret < 0)
233
+
goto err;
234
+
}
235
+
236
+
/* No entries in DT? Generate a dummy state table entry */
237
+
if (!size) {
238
+
ret = dt_remember_dummy_state(p, statename);
239
+
if (ret < 0)
240
+
goto err;
241
+
}
242
+
}
243
+
244
+
return 0;
245
+
246
+
err:
247
+
pinctrl_dt_free_maps(p);
248
+
return ret;
249
+
}
+35
drivers/pinctrl/devicetree.h
+35
drivers/pinctrl/devicetree.h
···
1
+
/*
2
+
* Internal interface to pinctrl device tree integration
3
+
*
4
+
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify it
7
+
* under the terms and conditions of the GNU General Public License,
8
+
* version 2, as published by the Free Software Foundation.
9
+
*
10
+
* This program is distributed in the hope it will be useful, but WITHOUT
11
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13
+
* more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
17
+
*/
18
+
19
+
#ifdef CONFIG_OF
20
+
21
+
void pinctrl_dt_free_maps(struct pinctrl *p);
22
+
int pinctrl_dt_to_map(struct pinctrl *p);
23
+
24
+
#else
25
+
26
+
static inline int pinctrl_dt_to_map(struct pinctrl *p)
27
+
{
28
+
return 0;
29
+
}
30
+
31
+
static inline void pinctrl_dt_free_maps(struct pinctrl *p)
32
+
{
33
+
}
34
+
35
+
#endif
+43
-9
drivers/pinctrl/pinconf.c
+43
-9
drivers/pinctrl/pinconf.c
···
28
28
const struct pinconf_ops *ops = pctldev->desc->confops;
29
29
30
30
/* We must be able to read out pin status */
31
-
if (!ops->pin_config_get && !ops->pin_config_group_get)
31
+
if (!ops->pin_config_get && !ops->pin_config_group_get) {
32
+
dev_err(pctldev->dev,
33
+
"pinconf must be able to read out pin status\n");
32
34
return -EINVAL;
35
+
}
33
36
/* We have to be able to config the pins in SOME way */
34
-
if (!ops->pin_config_set && !ops->pin_config_group_set)
37
+
if (!ops->pin_config_set && !ops->pin_config_group_set) {
38
+
dev_err(pctldev->dev,
39
+
"pinconf has to be able to set a pins config\n");
35
40
return -EINVAL;
41
+
}
36
42
return 0;
37
43
}
38
44
···
385
379
386
380
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
387
381
{
382
+
struct pinctrl_dev *pctldev;
383
+
const struct pinconf_ops *confops;
388
384
int i;
385
+
386
+
pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
387
+
if (pctldev)
388
+
confops = pctldev->desc->confops;
389
+
else
390
+
confops = NULL;
389
391
390
392
switch (map->type) {
391
393
case PIN_MAP_TYPE_CONFIGS_PIN:
···
408
394
409
395
seq_printf(s, "%s\n", map->data.configs.group_or_pin);
410
396
411
-
for (i = 0; i < map->data.configs.num_configs; i++)
412
-
seq_printf(s, "config %08lx\n", map->data.configs.configs[i]);
397
+
for (i = 0; i < map->data.configs.num_configs; i++) {
398
+
seq_printf(s, "config ");
399
+
if (confops && confops->pin_config_config_dbg_show)
400
+
confops->pin_config_config_dbg_show(pctldev, s,
401
+
map->data.configs.configs[i]);
402
+
else
403
+
seq_printf(s, "%08lx", map->data.configs.configs[i]);
404
+
seq_printf(s, "\n");
405
+
}
413
406
}
414
407
415
408
void pinconf_show_setting(struct seq_file *s,
···
424
403
{
425
404
struct pinctrl_dev *pctldev = setting->pctldev;
426
405
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
406
+
const struct pinconf_ops *confops = pctldev->desc->confops;
427
407
struct pin_desc *desc;
428
408
int i;
429
409
···
450
428
* FIXME: We should really get the pin controler to dump the config
451
429
* values, so they can be decoded to something meaningful.
452
430
*/
453
-
for (i = 0; i < setting->data.configs.num_configs; i++)
454
-
seq_printf(s, " %08lx", setting->data.configs.configs[i]);
431
+
for (i = 0; i < setting->data.configs.num_configs; i++) {
432
+
seq_printf(s, " ");
433
+
if (confops && confops->pin_config_config_dbg_show)
434
+
confops->pin_config_config_dbg_show(pctldev, s,
435
+
setting->data.configs.configs[i]);
436
+
else
437
+
seq_printf(s, "%08lx",
438
+
setting->data.configs.configs[i]);
439
+
}
455
440
456
441
seq_printf(s, "\n");
457
442
}
···
477
448
static int pinconf_pins_show(struct seq_file *s, void *what)
478
449
{
479
450
struct pinctrl_dev *pctldev = s->private;
451
+
const struct pinconf_ops *ops = pctldev->desc->confops;
480
452
unsigned i, pin;
481
453
454
+
if (!ops || !ops->pin_config_get)
455
+
return 0;
456
+
482
457
seq_puts(s, "Pin config settings per pin\n");
483
-
seq_puts(s, "Format: pin (name): pinmux setting array\n");
458
+
seq_puts(s, "Format: pin (name): configs\n");
484
459
485
460
mutex_lock(&pinctrl_mutex);
486
461
···
528
495
struct pinctrl_dev *pctldev = s->private;
529
496
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
530
497
const struct pinconf_ops *ops = pctldev->desc->confops;
498
+
unsigned ngroups = pctlops->get_groups_count(pctldev);
531
499
unsigned selector = 0;
532
500
533
501
if (!ops || !ops->pin_config_group_get)
534
502
return 0;
535
503
536
504
seq_puts(s, "Pin config settings per pin group\n");
537
-
seq_puts(s, "Format: group (name): pinmux setting array\n");
505
+
seq_puts(s, "Format: group (name): configs\n");
538
506
539
507
mutex_lock(&pinctrl_mutex);
540
508
541
-
while (pctlops->list_groups(pctldev, selector) >= 0) {
509
+
while (selector < ngroups) {
542
510
const char *gname = pctlops->get_group_name(pctldev, selector);
543
511
544
512
seq_printf(s, "%u (%s):", selector, gname);
+12
-5
drivers/pinctrl/pinconf.h
+12
-5
drivers/pinctrl/pinconf.h
···
19
19
struct pinctrl_setting *setting);
20
20
void pinconf_free_setting(struct pinctrl_setting const *setting);
21
21
int pinconf_apply_setting(struct pinctrl_setting const *setting);
22
-
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
23
-
void pinconf_show_setting(struct seq_file *s,
24
-
struct pinctrl_setting const *setting);
25
-
void pinconf_init_device_debugfs(struct dentry *devroot,
26
-
struct pinctrl_dev *pctldev);
27
22
28
23
/*
29
24
* You will only be interested in these if you're using PINCONF
···
55
60
{
56
61
return 0;
57
62
}
63
+
64
+
#endif
65
+
66
+
#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS)
67
+
68
+
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
69
+
void pinconf_show_setting(struct seq_file *s,
70
+
struct pinctrl_setting const *setting);
71
+
void pinconf_init_device_debugfs(struct dentry *devroot,
72
+
struct pinctrl_dev *pctldev);
73
+
74
+
#else
58
75
59
76
static inline void pinconf_show_map(struct seq_file *s,
60
77
struct pinctrl_map const *map)
+2
-2
drivers/pinctrl/pinctrl-coh901.c
+2
-2
drivers/pinctrl/pinctrl-coh901.c
···
174
174
175
175
176
176
/* Initial configuration */
177
-
static const struct __initdata u300_gpio_confdata
177
+
static const struct __initconst u300_gpio_confdata
178
178
bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
179
179
/* Port 0, pins 0-7 */
180
180
{
···
255
255
}
256
256
};
257
257
258
-
static const struct __initdata u300_gpio_confdata
258
+
static const struct __initconst u300_gpio_confdata
259
259
bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
260
260
/* Port 0, pins 0-7 */
261
261
{
+627
drivers/pinctrl/pinctrl-imx.c
+627
drivers/pinctrl/pinctrl-imx.c
···
1
+
/*
2
+
* Core driver for the imx pin controller
3
+
*
4
+
* Copyright (C) 2012 Freescale Semiconductor, Inc.
5
+
* Copyright (C) 2012 Linaro Ltd.
6
+
*
7
+
* Author: Dong Aisheng <dong.aisheng@linaro.org>
8
+
*
9
+
* This program is free software; you can redistribute it and/or modify
10
+
* it under the terms of the GNU General Public License as published by
11
+
* the Free Software Foundation; either version 2 of the License, or
12
+
* (at your option) any later version.
13
+
*/
14
+
15
+
#include <linux/err.h>
16
+
#include <linux/init.h>
17
+
#include <linux/io.h>
18
+
#include <linux/module.h>
19
+
#include <linux/of.h>
20
+
#include <linux/of_device.h>
21
+
#include <linux/pinctrl/machine.h>
22
+
#include <linux/pinctrl/pinconf.h>
23
+
#include <linux/pinctrl/pinctrl.h>
24
+
#include <linux/pinctrl/pinmux.h>
25
+
#include <linux/slab.h>
26
+
27
+
#include "core.h"
28
+
#include "pinctrl-imx.h"
29
+
30
+
#define IMX_PMX_DUMP(info, p, m, c, n) \
31
+
{ \
32
+
int i, j; \
33
+
printk("Format: Pin Mux Config\n"); \
34
+
for (i = 0; i < n; i++) { \
35
+
j = p[i]; \
36
+
printk("%s %d 0x%lx\n", \
37
+
info->pins[j].name, \
38
+
m[i], c[i]); \
39
+
} \
40
+
}
41
+
42
+
/* The bits in CONFIG cell defined in binding doc*/
43
+
#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
44
+
#define IMX_PAD_SION 0x40000000 /* set SION */
45
+
46
+
/**
47
+
* @dev: a pointer back to containing device
48
+
* @base: the offset to the controller in virtual memory
49
+
*/
50
+
struct imx_pinctrl {
51
+
struct device *dev;
52
+
struct pinctrl_dev *pctl;
53
+
void __iomem *base;
54
+
const struct imx_pinctrl_soc_info *info;
55
+
};
56
+
57
+
static const struct imx_pin_reg *imx_find_pin_reg(
58
+
const struct imx_pinctrl_soc_info *info,
59
+
unsigned pin, bool is_mux, unsigned mux)
60
+
{
61
+
const struct imx_pin_reg *pin_reg = NULL;
62
+
int i;
63
+
64
+
for (i = 0; i < info->npin_regs; i++) {
65
+
pin_reg = &info->pin_regs[i];
66
+
if (pin_reg->pid != pin)
67
+
continue;
68
+
if (!is_mux)
69
+
break;
70
+
else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
71
+
break;
72
+
}
73
+
74
+
if (!pin_reg) {
75
+
dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
76
+
info->pins[pin].name);
77
+
return NULL;
78
+
}
79
+
80
+
return pin_reg;
81
+
}
82
+
83
+
static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
84
+
const struct imx_pinctrl_soc_info *info,
85
+
const char *name)
86
+
{
87
+
const struct imx_pin_group *grp = NULL;
88
+
int i;
89
+
90
+
for (i = 0; i < info->ngroups; i++) {
91
+
if (!strcmp(info->groups[i].name, name)) {
92
+
grp = &info->groups[i];
93
+
break;
94
+
}
95
+
}
96
+
97
+
return grp;
98
+
}
99
+
100
+
static int imx_get_groups_count(struct pinctrl_dev *pctldev)
101
+
{
102
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
103
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
104
+
105
+
return info->ngroups;
106
+
}
107
+
108
+
static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
109
+
unsigned selector)
110
+
{
111
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
112
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
113
+
114
+
return info->groups[selector].name;
115
+
}
116
+
117
+
static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
118
+
const unsigned **pins,
119
+
unsigned *npins)
120
+
{
121
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
122
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
123
+
124
+
if (selector >= info->ngroups)
125
+
return -EINVAL;
126
+
127
+
*pins = info->groups[selector].pins;
128
+
*npins = info->groups[selector].npins;
129
+
130
+
return 0;
131
+
}
132
+
133
+
static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
134
+
unsigned offset)
135
+
{
136
+
seq_printf(s, "%s", dev_name(pctldev->dev));
137
+
}
138
+
139
+
static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
140
+
struct device_node *np,
141
+
struct pinctrl_map **map, unsigned *num_maps)
142
+
{
143
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
144
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
145
+
const struct imx_pin_group *grp;
146
+
struct pinctrl_map *new_map;
147
+
struct device_node *parent;
148
+
int map_num = 1;
149
+
int i;
150
+
151
+
/*
152
+
* first find the group of this node and check if we need create
153
+
* config maps for pins
154
+
*/
155
+
grp = imx_pinctrl_find_group_by_name(info, np->name);
156
+
if (!grp) {
157
+
dev_err(info->dev, "unable to find group for node %s\n",
158
+
np->name);
159
+
return -EINVAL;
160
+
}
161
+
162
+
for (i = 0; i < grp->npins; i++) {
163
+
if (!(grp->configs[i] & IMX_NO_PAD_CTL))
164
+
map_num++;
165
+
}
166
+
167
+
new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
168
+
if (!new_map)
169
+
return -ENOMEM;
170
+
171
+
*map = new_map;
172
+
*num_maps = map_num;
173
+
174
+
/* create mux map */
175
+
parent = of_get_parent(np);
176
+
if (!parent)
177
+
return -EINVAL;
178
+
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
179
+
new_map[0].data.mux.function = parent->name;
180
+
new_map[0].data.mux.group = np->name;
181
+
of_node_put(parent);
182
+
183
+
/* create config map */
184
+
new_map++;
185
+
for (i = 0; i < grp->npins; i++) {
186
+
if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
187
+
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
188
+
new_map[i].data.configs.group_or_pin =
189
+
pin_get_name(pctldev, grp->pins[i]);
190
+
new_map[i].data.configs.configs = &grp->configs[i];
191
+
new_map[i].data.configs.num_configs = 1;
192
+
}
193
+
}
194
+
195
+
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
196
+
new_map->data.mux.function, new_map->data.mux.group, map_num);
197
+
198
+
return 0;
199
+
}
200
+
201
+
static void imx_dt_free_map(struct pinctrl_dev *pctldev,
202
+
struct pinctrl_map *map, unsigned num_maps)
203
+
{
204
+
int i;
205
+
206
+
for (i = 0; i < num_maps; i++)
207
+
kfree(map);
208
+
}
209
+
210
+
static struct pinctrl_ops imx_pctrl_ops = {
211
+
.get_groups_count = imx_get_groups_count,
212
+
.get_group_name = imx_get_group_name,
213
+
.get_group_pins = imx_get_group_pins,
214
+
.pin_dbg_show = imx_pin_dbg_show,
215
+
.dt_node_to_map = imx_dt_node_to_map,
216
+
.dt_free_map = imx_dt_free_map,
217
+
218
+
};
219
+
220
+
static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
221
+
unsigned group)
222
+
{
223
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
224
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
225
+
const struct imx_pin_reg *pin_reg;
226
+
const unsigned *pins, *mux;
227
+
unsigned int npins, pin_id;
228
+
int i;
229
+
230
+
/*
231
+
* Configure the mux mode for each pin in the group for a specific
232
+
* function.
233
+
*/
234
+
pins = info->groups[group].pins;
235
+
npins = info->groups[group].npins;
236
+
mux = info->groups[group].mux_mode;
237
+
238
+
WARN_ON(!pins || !npins || !mux);
239
+
240
+
dev_dbg(ipctl->dev, "enable function %s group %s\n",
241
+
info->functions[selector].name, info->groups[group].name);
242
+
243
+
for (i = 0; i < npins; i++) {
244
+
pin_id = pins[i];
245
+
246
+
pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
247
+
if (!pin_reg)
248
+
return -EINVAL;
249
+
250
+
if (!pin_reg->mux_reg) {
251
+
dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
252
+
info->pins[pin_id].name);
253
+
return -EINVAL;
254
+
}
255
+
256
+
writel(mux[i], ipctl->base + pin_reg->mux_reg);
257
+
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
258
+
pin_reg->mux_reg, mux[i]);
259
+
260
+
/* some pins also need select input setting, set it if found */
261
+
if (pin_reg->input_reg) {
262
+
writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
263
+
dev_dbg(ipctl->dev,
264
+
"==>select_input: offset 0x%x val 0x%x\n",
265
+
pin_reg->input_reg, pin_reg->input_val);
266
+
}
267
+
}
268
+
269
+
return 0;
270
+
}
271
+
272
+
static void imx_pmx_disable(struct pinctrl_dev *pctldev, unsigned func_selector,
273
+
unsigned group_selector)
274
+
{
275
+
/* nothing to do here */
276
+
}
277
+
278
+
static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
279
+
{
280
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
281
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
282
+
283
+
return info->nfunctions;
284
+
}
285
+
286
+
static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
287
+
unsigned selector)
288
+
{
289
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
290
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
291
+
292
+
return info->functions[selector].name;
293
+
}
294
+
295
+
static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
296
+
const char * const **groups,
297
+
unsigned * const num_groups)
298
+
{
299
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
300
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
301
+
302
+
*groups = info->functions[selector].groups;
303
+
*num_groups = info->functions[selector].num_groups;
304
+
305
+
return 0;
306
+
}
307
+
308
+
static struct pinmux_ops imx_pmx_ops = {
309
+
.get_functions_count = imx_pmx_get_funcs_count,
310
+
.get_function_name = imx_pmx_get_func_name,
311
+
.get_function_groups = imx_pmx_get_groups,
312
+
.enable = imx_pmx_enable,
313
+
.disable = imx_pmx_disable,
314
+
};
315
+
316
+
static int imx_pinconf_get(struct pinctrl_dev *pctldev,
317
+
unsigned pin_id, unsigned long *config)
318
+
{
319
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
320
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
321
+
const struct imx_pin_reg *pin_reg;
322
+
323
+
pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
324
+
if (!pin_reg)
325
+
return -EINVAL;
326
+
327
+
if (!pin_reg->conf_reg) {
328
+
dev_err(info->dev, "Pin(%s) does not support config function\n",
329
+
info->pins[pin_id].name);
330
+
return -EINVAL;
331
+
}
332
+
333
+
*config = readl(ipctl->base + pin_reg->conf_reg);
334
+
335
+
return 0;
336
+
}
337
+
338
+
static int imx_pinconf_set(struct pinctrl_dev *pctldev,
339
+
unsigned pin_id, unsigned long config)
340
+
{
341
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
342
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
343
+
const struct imx_pin_reg *pin_reg;
344
+
345
+
pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
346
+
if (!pin_reg)
347
+
return -EINVAL;
348
+
349
+
if (!pin_reg->conf_reg) {
350
+
dev_err(info->dev, "Pin(%s) does not support config function\n",
351
+
info->pins[pin_id].name);
352
+
return -EINVAL;
353
+
}
354
+
355
+
dev_dbg(ipctl->dev, "pinconf set pin %s\n",
356
+
info->pins[pin_id].name);
357
+
358
+
writel(config, ipctl->base + pin_reg->conf_reg);
359
+
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
360
+
pin_reg->conf_reg, config);
361
+
362
+
return 0;
363
+
}
364
+
365
+
static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
366
+
struct seq_file *s, unsigned pin_id)
367
+
{
368
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
369
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
370
+
const struct imx_pin_reg *pin_reg;
371
+
unsigned long config;
372
+
373
+
pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
374
+
if (!pin_reg || !pin_reg->conf_reg) {
375
+
seq_printf(s, "N/A");
376
+
return;
377
+
}
378
+
379
+
config = readl(ipctl->base + pin_reg->conf_reg);
380
+
seq_printf(s, "0x%lx", config);
381
+
}
382
+
383
+
static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
384
+
struct seq_file *s, unsigned group)
385
+
{
386
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
387
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
388
+
struct imx_pin_group *grp;
389
+
unsigned long config;
390
+
const char *name;
391
+
int i, ret;
392
+
393
+
if (group > info->ngroups)
394
+
return;
395
+
396
+
seq_printf(s, "\n");
397
+
grp = &info->groups[group];
398
+
for (i = 0; i < grp->npins; i++) {
399
+
name = pin_get_name(pctldev, grp->pins[i]);
400
+
ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
401
+
if (ret)
402
+
return;
403
+
seq_printf(s, "%s: 0x%lx", name, config);
404
+
}
405
+
}
406
+
407
+
struct pinconf_ops imx_pinconf_ops = {
408
+
.pin_config_get = imx_pinconf_get,
409
+
.pin_config_set = imx_pinconf_set,
410
+
.pin_config_dbg_show = imx_pinconf_dbg_show,
411
+
.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
412
+
};
413
+
414
+
static struct pinctrl_desc imx_pinctrl_desc = {
415
+
.pctlops = &imx_pctrl_ops,
416
+
.pmxops = &imx_pmx_ops,
417
+
.confops = &imx_pinconf_ops,
418
+
.owner = THIS_MODULE,
419
+
};
420
+
421
+
/* decode pin id and mux from pin function id got from device tree*/
422
+
static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
423
+
unsigned int pin_func_id, unsigned int *pin_id,
424
+
unsigned int *mux)
425
+
{
426
+
if (pin_func_id > info->npin_regs)
427
+
return -EINVAL;
428
+
429
+
*pin_id = info->pin_regs[pin_func_id].pid;
430
+
*mux = info->pin_regs[pin_func_id].mux_mode;
431
+
432
+
return 0;
433
+
}
434
+
435
+
static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
436
+
struct imx_pin_group *grp,
437
+
struct imx_pinctrl_soc_info *info,
438
+
u32 index)
439
+
{
440
+
unsigned int pin_func_id;
441
+
int ret, size;
442
+
const const __be32 *list;
443
+
int i, j;
444
+
u32 config;
445
+
446
+
dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
447
+
448
+
/* Initialise group */
449
+
grp->name = np->name;
450
+
451
+
/*
452
+
* the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
453
+
* do sanity check and calculate pins number
454
+
*/
455
+
list = of_get_property(np, "fsl,pins", &size);
456
+
/* we do not check return since it's safe node passed down */
457
+
size /= sizeof(*list);
458
+
if (!size || size % 2) {
459
+
dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
460
+
return -EINVAL;
461
+
}
462
+
463
+
grp->npins = size / 2;
464
+
grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
465
+
GFP_KERNEL);
466
+
grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
467
+
GFP_KERNEL);
468
+
grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
469
+
GFP_KERNEL);
470
+
for (i = 0, j = 0; i < size; i += 2, j++) {
471
+
pin_func_id = be32_to_cpu(*list++);
472
+
ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
473
+
&grp->pins[j], &grp->mux_mode[j]);
474
+
if (ret) {
475
+
dev_err(info->dev, "get invalid pin function id\n");
476
+
return -EINVAL;
477
+
}
478
+
/* SION bit is in mux register */
479
+
config = be32_to_cpu(*list++);
480
+
if (config & IMX_PAD_SION)
481
+
grp->mux_mode[j] |= IOMUXC_CONFIG_SION;
482
+
grp->configs[j] = config & ~IMX_PAD_SION;
483
+
}
484
+
485
+
#ifdef DEBUG
486
+
IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
487
+
#endif
488
+
return 0;
489
+
}
490
+
491
+
static int __devinit imx_pinctrl_parse_functions(struct device_node *np,
492
+
struct imx_pinctrl_soc_info *info, u32 index)
493
+
{
494
+
struct device_node *child;
495
+
struct imx_pmx_func *func;
496
+
struct imx_pin_group *grp;
497
+
int ret;
498
+
static u32 grp_index;
499
+
u32 i = 0;
500
+
501
+
dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
502
+
503
+
func = &info->functions[index];
504
+
505
+
/* Initialise function */
506
+
func->name = np->name;
507
+
func->num_groups = of_get_child_count(np);
508
+
if (func->num_groups <= 0) {
509
+
dev_err(info->dev, "no groups defined\n");
510
+
return -EINVAL;
511
+
}
512
+
func->groups = devm_kzalloc(info->dev,
513
+
func->num_groups * sizeof(char *), GFP_KERNEL);
514
+
515
+
for_each_child_of_node(np, child) {
516
+
func->groups[i] = child->name;
517
+
grp = &info->groups[grp_index++];
518
+
ret = imx_pinctrl_parse_groups(child, grp, info, i++);
519
+
if (ret)
520
+
return ret;
521
+
}
522
+
523
+
return 0;
524
+
}
525
+
526
+
static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev,
527
+
struct imx_pinctrl_soc_info *info)
528
+
{
529
+
struct device_node *np = pdev->dev.of_node;
530
+
struct device_node *child;
531
+
int ret;
532
+
u32 nfuncs = 0;
533
+
u32 i = 0;
534
+
535
+
if (!np)
536
+
return -ENODEV;
537
+
538
+
nfuncs = of_get_child_count(np);
539
+
if (nfuncs <= 0) {
540
+
dev_err(&pdev->dev, "no functions defined\n");
541
+
return -EINVAL;
542
+
}
543
+
544
+
info->nfunctions = nfuncs;
545
+
info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
546
+
GFP_KERNEL);
547
+
if (!info->functions)
548
+
return -ENOMEM;
549
+
550
+
info->ngroups = 0;
551
+
for_each_child_of_node(np, child)
552
+
info->ngroups += of_get_child_count(child);
553
+
info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
554
+
GFP_KERNEL);
555
+
if (!info->groups)
556
+
return -ENOMEM;
557
+
558
+
for_each_child_of_node(np, child) {
559
+
ret = imx_pinctrl_parse_functions(child, info, i++);
560
+
if (ret) {
561
+
dev_err(&pdev->dev, "failed to parse function\n");
562
+
return ret;
563
+
}
564
+
}
565
+
566
+
return 0;
567
+
}
568
+
569
+
int __devinit imx_pinctrl_probe(struct platform_device *pdev,
570
+
struct imx_pinctrl_soc_info *info)
571
+
{
572
+
struct imx_pinctrl *ipctl;
573
+
struct resource *res;
574
+
int ret;
575
+
576
+
if (!info || !info->pins || !info->npins
577
+
|| !info->pin_regs || !info->npin_regs) {
578
+
dev_err(&pdev->dev, "wrong pinctrl info\n");
579
+
return -EINVAL;
580
+
}
581
+
info->dev = &pdev->dev;
582
+
583
+
/* Create state holders etc for this driver */
584
+
ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
585
+
if (!ipctl)
586
+
return -ENOMEM;
587
+
588
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
589
+
if (!res)
590
+
return -ENOENT;
591
+
592
+
ipctl->base = devm_request_and_ioremap(&pdev->dev, res);
593
+
if (!ipctl->base)
594
+
return -EBUSY;
595
+
596
+
imx_pinctrl_desc.name = dev_name(&pdev->dev);
597
+
imx_pinctrl_desc.pins = info->pins;
598
+
imx_pinctrl_desc.npins = info->npins;
599
+
600
+
ret = imx_pinctrl_probe_dt(pdev, info);
601
+
if (ret) {
602
+
dev_err(&pdev->dev, "fail to probe dt properties\n");
603
+
return ret;
604
+
}
605
+
606
+
ipctl->info = info;
607
+
ipctl->dev = info->dev;
608
+
platform_set_drvdata(pdev, ipctl);
609
+
ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
610
+
if (!ipctl->pctl) {
611
+
dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
612
+
return -EINVAL;
613
+
}
614
+
615
+
dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
616
+
617
+
return 0;
618
+
}
619
+
620
+
int __devexit imx_pinctrl_remove(struct platform_device *pdev)
621
+
{
622
+
struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
623
+
624
+
pinctrl_unregister(ipctl->pctl);
625
+
626
+
return 0;
627
+
}
+106
drivers/pinctrl/pinctrl-imx.h
+106
drivers/pinctrl/pinctrl-imx.h
···
1
+
/*
2
+
* IMX pinmux core definitions
3
+
*
4
+
* Copyright (C) 2012 Freescale Semiconductor, Inc.
5
+
* Copyright (C) 2012 Linaro Ltd.
6
+
*
7
+
* Author: Dong Aisheng <dong.aisheng@linaro.org>
8
+
*
9
+
* This program is free software; you can redistribute it and/or modify
10
+
* it under the terms of the GNU General Public License as published by
11
+
* the Free Software Foundation; either version 2 of the License, or
12
+
* (at your option) any later version.
13
+
*/
14
+
15
+
#ifndef __DRIVERS_PINCTRL_IMX_H
16
+
#define __DRIVERS_PINCTRL_IMX_H
17
+
18
+
struct platform_device;
19
+
20
+
/**
21
+
* struct imx_pin_group - describes an IMX pin group
22
+
* @name: the name of this specific pin group
23
+
* @pins: an array of discrete physical pins used in this group, taken
24
+
* from the driver-local pin enumeration space
25
+
* @npins: the number of pins in this group array, i.e. the number of
26
+
* elements in .pins so we can iterate over that array
27
+
* @mux_mode: the mux mode for each pin in this group. The size of this
28
+
* array is the same as pins.
29
+
* @configs: the config for each pin in this group. The size of this
30
+
* array is the same as pins.
31
+
*/
32
+
struct imx_pin_group {
33
+
const char *name;
34
+
unsigned int *pins;
35
+
unsigned npins;
36
+
unsigned int *mux_mode;
37
+
unsigned long *configs;
38
+
};
39
+
40
+
/**
41
+
* struct imx_pmx_func - describes IMX pinmux functions
42
+
* @name: the name of this specific function
43
+
* @groups: corresponding pin groups
44
+
* @num_groups: the number of groups
45
+
*/
46
+
struct imx_pmx_func {
47
+
const char *name;
48
+
const char **groups;
49
+
unsigned num_groups;
50
+
};
51
+
52
+
/**
53
+
* struct imx_pin_reg - describe a pin reg map
54
+
* The last 3 members are used for select input setting
55
+
* @pid: pin id
56
+
* @mux_reg: mux register offset
57
+
* @conf_reg: config register offset
58
+
* @mux_mode: mux mode
59
+
* @input_reg: select input register offset for this mux if any
60
+
* 0 if no select input setting needed.
61
+
* @input_val: the value set to select input register
62
+
*/
63
+
struct imx_pin_reg {
64
+
u16 pid;
65
+
u16 mux_reg;
66
+
u16 conf_reg;
67
+
u8 mux_mode;
68
+
u16 input_reg;
69
+
u8 input_val;
70
+
};
71
+
72
+
struct imx_pinctrl_soc_info {
73
+
struct device *dev;
74
+
const struct pinctrl_pin_desc *pins;
75
+
unsigned int npins;
76
+
const struct imx_pin_reg *pin_regs;
77
+
unsigned int npin_regs;
78
+
struct imx_pin_group *groups;
79
+
unsigned int ngroups;
80
+
struct imx_pmx_func *functions;
81
+
unsigned int nfunctions;
82
+
};
83
+
84
+
#define NO_MUX 0x0
85
+
#define NO_PAD 0x0
86
+
87
+
#define IMX_PIN_REG(id, conf, mux, mode, input, val) \
88
+
{ \
89
+
.pid = id, \
90
+
.conf_reg = conf, \
91
+
.mux_reg = mux, \
92
+
.mux_mode = mode, \
93
+
.input_reg = input, \
94
+
.input_val = val, \
95
+
}
96
+
97
+
#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
98
+
99
+
#define PAD_CTL_MASK(len) ((1 << len) - 1)
100
+
#define IMX_MUX_MASK 0x7
101
+
#define IOMUXC_CONFIG_SION (0x1 << 4)
102
+
103
+
int imx_pinctrl_probe(struct platform_device *pdev,
104
+
struct imx_pinctrl_soc_info *info);
105
+
int imx_pinctrl_remove(struct platform_device *pdev);
106
+
#endif /* __DRIVERS_PINCTRL_IMX_H */
+305
drivers/pinctrl/pinctrl-imx23.c
+305
drivers/pinctrl/pinctrl-imx23.c
···
1
+
/*
2
+
* Copyright 2012 Freescale Semiconductor, Inc.
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
#include <linux/init.h>
13
+
#include <linux/module.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/pinctrl/pinctrl.h>
16
+
#include "pinctrl-mxs.h"
17
+
18
+
enum imx23_pin_enum {
19
+
GPMI_D00 = PINID(0, 0),
20
+
GPMI_D01 = PINID(0, 1),
21
+
GPMI_D02 = PINID(0, 2),
22
+
GPMI_D03 = PINID(0, 3),
23
+
GPMI_D04 = PINID(0, 4),
24
+
GPMI_D05 = PINID(0, 5),
25
+
GPMI_D06 = PINID(0, 6),
26
+
GPMI_D07 = PINID(0, 7),
27
+
GPMI_D08 = PINID(0, 8),
28
+
GPMI_D09 = PINID(0, 9),
29
+
GPMI_D10 = PINID(0, 10),
30
+
GPMI_D11 = PINID(0, 11),
31
+
GPMI_D12 = PINID(0, 12),
32
+
GPMI_D13 = PINID(0, 13),
33
+
GPMI_D14 = PINID(0, 14),
34
+
GPMI_D15 = PINID(0, 15),
35
+
GPMI_CLE = PINID(0, 16),
36
+
GPMI_ALE = PINID(0, 17),
37
+
GPMI_CE2N = PINID(0, 18),
38
+
GPMI_RDY0 = PINID(0, 19),
39
+
GPMI_RDY1 = PINID(0, 20),
40
+
GPMI_RDY2 = PINID(0, 21),
41
+
GPMI_RDY3 = PINID(0, 22),
42
+
GPMI_WPN = PINID(0, 23),
43
+
GPMI_WRN = PINID(0, 24),
44
+
GPMI_RDN = PINID(0, 25),
45
+
AUART1_CTS = PINID(0, 26),
46
+
AUART1_RTS = PINID(0, 27),
47
+
AUART1_RX = PINID(0, 28),
48
+
AUART1_TX = PINID(0, 29),
49
+
I2C_SCL = PINID(0, 30),
50
+
I2C_SDA = PINID(0, 31),
51
+
LCD_D00 = PINID(1, 0),
52
+
LCD_D01 = PINID(1, 1),
53
+
LCD_D02 = PINID(1, 2),
54
+
LCD_D03 = PINID(1, 3),
55
+
LCD_D04 = PINID(1, 4),
56
+
LCD_D05 = PINID(1, 5),
57
+
LCD_D06 = PINID(1, 6),
58
+
LCD_D07 = PINID(1, 7),
59
+
LCD_D08 = PINID(1, 8),
60
+
LCD_D09 = PINID(1, 9),
61
+
LCD_D10 = PINID(1, 10),
62
+
LCD_D11 = PINID(1, 11),
63
+
LCD_D12 = PINID(1, 12),
64
+
LCD_D13 = PINID(1, 13),
65
+
LCD_D14 = PINID(1, 14),
66
+
LCD_D15 = PINID(1, 15),
67
+
LCD_D16 = PINID(1, 16),
68
+
LCD_D17 = PINID(1, 17),
69
+
LCD_RESET = PINID(1, 18),
70
+
LCD_RS = PINID(1, 19),
71
+
LCD_WR = PINID(1, 20),
72
+
LCD_CS = PINID(1, 21),
73
+
LCD_DOTCK = PINID(1, 22),
74
+
LCD_ENABLE = PINID(1, 23),
75
+
LCD_HSYNC = PINID(1, 24),
76
+
LCD_VSYNC = PINID(1, 25),
77
+
PWM0 = PINID(1, 26),
78
+
PWM1 = PINID(1, 27),
79
+
PWM2 = PINID(1, 28),
80
+
PWM3 = PINID(1, 29),
81
+
PWM4 = PINID(1, 30),
82
+
SSP1_CMD = PINID(2, 0),
83
+
SSP1_DETECT = PINID(2, 1),
84
+
SSP1_DATA0 = PINID(2, 2),
85
+
SSP1_DATA1 = PINID(2, 3),
86
+
SSP1_DATA2 = PINID(2, 4),
87
+
SSP1_DATA3 = PINID(2, 5),
88
+
SSP1_SCK = PINID(2, 6),
89
+
ROTARYA = PINID(2, 7),
90
+
ROTARYB = PINID(2, 8),
91
+
EMI_A00 = PINID(2, 9),
92
+
EMI_A01 = PINID(2, 10),
93
+
EMI_A02 = PINID(2, 11),
94
+
EMI_A03 = PINID(2, 12),
95
+
EMI_A04 = PINID(2, 13),
96
+
EMI_A05 = PINID(2, 14),
97
+
EMI_A06 = PINID(2, 15),
98
+
EMI_A07 = PINID(2, 16),
99
+
EMI_A08 = PINID(2, 17),
100
+
EMI_A09 = PINID(2, 18),
101
+
EMI_A10 = PINID(2, 19),
102
+
EMI_A11 = PINID(2, 20),
103
+
EMI_A12 = PINID(2, 21),
104
+
EMI_BA0 = PINID(2, 22),
105
+
EMI_BA1 = PINID(2, 23),
106
+
EMI_CASN = PINID(2, 24),
107
+
EMI_CE0N = PINID(2, 25),
108
+
EMI_CE1N = PINID(2, 26),
109
+
GPMI_CE1N = PINID(2, 27),
110
+
GPMI_CE0N = PINID(2, 28),
111
+
EMI_CKE = PINID(2, 29),
112
+
EMI_RASN = PINID(2, 30),
113
+
EMI_WEN = PINID(2, 31),
114
+
EMI_D00 = PINID(3, 0),
115
+
EMI_D01 = PINID(3, 1),
116
+
EMI_D02 = PINID(3, 2),
117
+
EMI_D03 = PINID(3, 3),
118
+
EMI_D04 = PINID(3, 4),
119
+
EMI_D05 = PINID(3, 5),
120
+
EMI_D06 = PINID(3, 6),
121
+
EMI_D07 = PINID(3, 7),
122
+
EMI_D08 = PINID(3, 8),
123
+
EMI_D09 = PINID(3, 9),
124
+
EMI_D10 = PINID(3, 10),
125
+
EMI_D11 = PINID(3, 11),
126
+
EMI_D12 = PINID(3, 12),
127
+
EMI_D13 = PINID(3, 13),
128
+
EMI_D14 = PINID(3, 14),
129
+
EMI_D15 = PINID(3, 15),
130
+
EMI_DQM0 = PINID(3, 16),
131
+
EMI_DQM1 = PINID(3, 17),
132
+
EMI_DQS0 = PINID(3, 18),
133
+
EMI_DQS1 = PINID(3, 19),
134
+
EMI_CLK = PINID(3, 20),
135
+
EMI_CLKN = PINID(3, 21),
136
+
};
137
+
138
+
static const struct pinctrl_pin_desc imx23_pins[] = {
139
+
MXS_PINCTRL_PIN(GPMI_D00),
140
+
MXS_PINCTRL_PIN(GPMI_D01),
141
+
MXS_PINCTRL_PIN(GPMI_D02),
142
+
MXS_PINCTRL_PIN(GPMI_D03),
143
+
MXS_PINCTRL_PIN(GPMI_D04),
144
+
MXS_PINCTRL_PIN(GPMI_D05),
145
+
MXS_PINCTRL_PIN(GPMI_D06),
146
+
MXS_PINCTRL_PIN(GPMI_D07),
147
+
MXS_PINCTRL_PIN(GPMI_D08),
148
+
MXS_PINCTRL_PIN(GPMI_D09),
149
+
MXS_PINCTRL_PIN(GPMI_D10),
150
+
MXS_PINCTRL_PIN(GPMI_D11),
151
+
MXS_PINCTRL_PIN(GPMI_D12),
152
+
MXS_PINCTRL_PIN(GPMI_D13),
153
+
MXS_PINCTRL_PIN(GPMI_D14),
154
+
MXS_PINCTRL_PIN(GPMI_D15),
155
+
MXS_PINCTRL_PIN(GPMI_CLE),
156
+
MXS_PINCTRL_PIN(GPMI_ALE),
157
+
MXS_PINCTRL_PIN(GPMI_CE2N),
158
+
MXS_PINCTRL_PIN(GPMI_RDY0),
159
+
MXS_PINCTRL_PIN(GPMI_RDY1),
160
+
MXS_PINCTRL_PIN(GPMI_RDY2),
161
+
MXS_PINCTRL_PIN(GPMI_RDY3),
162
+
MXS_PINCTRL_PIN(GPMI_WPN),
163
+
MXS_PINCTRL_PIN(GPMI_WRN),
164
+
MXS_PINCTRL_PIN(GPMI_RDN),
165
+
MXS_PINCTRL_PIN(AUART1_CTS),
166
+
MXS_PINCTRL_PIN(AUART1_RTS),
167
+
MXS_PINCTRL_PIN(AUART1_RX),
168
+
MXS_PINCTRL_PIN(AUART1_TX),
169
+
MXS_PINCTRL_PIN(I2C_SCL),
170
+
MXS_PINCTRL_PIN(I2C_SDA),
171
+
MXS_PINCTRL_PIN(LCD_D00),
172
+
MXS_PINCTRL_PIN(LCD_D01),
173
+
MXS_PINCTRL_PIN(LCD_D02),
174
+
MXS_PINCTRL_PIN(LCD_D03),
175
+
MXS_PINCTRL_PIN(LCD_D04),
176
+
MXS_PINCTRL_PIN(LCD_D05),
177
+
MXS_PINCTRL_PIN(LCD_D06),
178
+
MXS_PINCTRL_PIN(LCD_D07),
179
+
MXS_PINCTRL_PIN(LCD_D08),
180
+
MXS_PINCTRL_PIN(LCD_D09),
181
+
MXS_PINCTRL_PIN(LCD_D10),
182
+
MXS_PINCTRL_PIN(LCD_D11),
183
+
MXS_PINCTRL_PIN(LCD_D12),
184
+
MXS_PINCTRL_PIN(LCD_D13),
185
+
MXS_PINCTRL_PIN(LCD_D14),
186
+
MXS_PINCTRL_PIN(LCD_D15),
187
+
MXS_PINCTRL_PIN(LCD_D16),
188
+
MXS_PINCTRL_PIN(LCD_D17),
189
+
MXS_PINCTRL_PIN(LCD_RESET),
190
+
MXS_PINCTRL_PIN(LCD_RS),
191
+
MXS_PINCTRL_PIN(LCD_WR),
192
+
MXS_PINCTRL_PIN(LCD_CS),
193
+
MXS_PINCTRL_PIN(LCD_DOTCK),
194
+
MXS_PINCTRL_PIN(LCD_ENABLE),
195
+
MXS_PINCTRL_PIN(LCD_HSYNC),
196
+
MXS_PINCTRL_PIN(LCD_VSYNC),
197
+
MXS_PINCTRL_PIN(PWM0),
198
+
MXS_PINCTRL_PIN(PWM1),
199
+
MXS_PINCTRL_PIN(PWM2),
200
+
MXS_PINCTRL_PIN(PWM3),
201
+
MXS_PINCTRL_PIN(PWM4),
202
+
MXS_PINCTRL_PIN(SSP1_CMD),
203
+
MXS_PINCTRL_PIN(SSP1_DETECT),
204
+
MXS_PINCTRL_PIN(SSP1_DATA0),
205
+
MXS_PINCTRL_PIN(SSP1_DATA1),
206
+
MXS_PINCTRL_PIN(SSP1_DATA2),
207
+
MXS_PINCTRL_PIN(SSP1_DATA3),
208
+
MXS_PINCTRL_PIN(SSP1_SCK),
209
+
MXS_PINCTRL_PIN(ROTARYA),
210
+
MXS_PINCTRL_PIN(ROTARYB),
211
+
MXS_PINCTRL_PIN(EMI_A00),
212
+
MXS_PINCTRL_PIN(EMI_A01),
213
+
MXS_PINCTRL_PIN(EMI_A02),
214
+
MXS_PINCTRL_PIN(EMI_A03),
215
+
MXS_PINCTRL_PIN(EMI_A04),
216
+
MXS_PINCTRL_PIN(EMI_A05),
217
+
MXS_PINCTRL_PIN(EMI_A06),
218
+
MXS_PINCTRL_PIN(EMI_A07),
219
+
MXS_PINCTRL_PIN(EMI_A08),
220
+
MXS_PINCTRL_PIN(EMI_A09),
221
+
MXS_PINCTRL_PIN(EMI_A10),
222
+
MXS_PINCTRL_PIN(EMI_A11),
223
+
MXS_PINCTRL_PIN(EMI_A12),
224
+
MXS_PINCTRL_PIN(EMI_BA0),
225
+
MXS_PINCTRL_PIN(EMI_BA1),
226
+
MXS_PINCTRL_PIN(EMI_CASN),
227
+
MXS_PINCTRL_PIN(EMI_CE0N),
228
+
MXS_PINCTRL_PIN(EMI_CE1N),
229
+
MXS_PINCTRL_PIN(GPMI_CE1N),
230
+
MXS_PINCTRL_PIN(GPMI_CE0N),
231
+
MXS_PINCTRL_PIN(EMI_CKE),
232
+
MXS_PINCTRL_PIN(EMI_RASN),
233
+
MXS_PINCTRL_PIN(EMI_WEN),
234
+
MXS_PINCTRL_PIN(EMI_D00),
235
+
MXS_PINCTRL_PIN(EMI_D01),
236
+
MXS_PINCTRL_PIN(EMI_D02),
237
+
MXS_PINCTRL_PIN(EMI_D03),
238
+
MXS_PINCTRL_PIN(EMI_D04),
239
+
MXS_PINCTRL_PIN(EMI_D05),
240
+
MXS_PINCTRL_PIN(EMI_D06),
241
+
MXS_PINCTRL_PIN(EMI_D07),
242
+
MXS_PINCTRL_PIN(EMI_D08),
243
+
MXS_PINCTRL_PIN(EMI_D09),
244
+
MXS_PINCTRL_PIN(EMI_D10),
245
+
MXS_PINCTRL_PIN(EMI_D11),
246
+
MXS_PINCTRL_PIN(EMI_D12),
247
+
MXS_PINCTRL_PIN(EMI_D13),
248
+
MXS_PINCTRL_PIN(EMI_D14),
249
+
MXS_PINCTRL_PIN(EMI_D15),
250
+
MXS_PINCTRL_PIN(EMI_DQM0),
251
+
MXS_PINCTRL_PIN(EMI_DQM1),
252
+
MXS_PINCTRL_PIN(EMI_DQS0),
253
+
MXS_PINCTRL_PIN(EMI_DQS1),
254
+
MXS_PINCTRL_PIN(EMI_CLK),
255
+
MXS_PINCTRL_PIN(EMI_CLKN),
256
+
};
257
+
258
+
static struct mxs_regs imx23_regs = {
259
+
.muxsel = 0x100,
260
+
.drive = 0x200,
261
+
.pull = 0x400,
262
+
};
263
+
264
+
static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
265
+
.regs = &imx23_regs,
266
+
.pins = imx23_pins,
267
+
.npins = ARRAY_SIZE(imx23_pins),
268
+
};
269
+
270
+
static int __devinit imx23_pinctrl_probe(struct platform_device *pdev)
271
+
{
272
+
return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
273
+
}
274
+
275
+
static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = {
276
+
{ .compatible = "fsl,imx23-pinctrl", },
277
+
{ /* sentinel */ }
278
+
};
279
+
MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
280
+
281
+
static struct platform_driver imx23_pinctrl_driver = {
282
+
.driver = {
283
+
.name = "imx23-pinctrl",
284
+
.owner = THIS_MODULE,
285
+
.of_match_table = imx23_pinctrl_of_match,
286
+
},
287
+
.probe = imx23_pinctrl_probe,
288
+
.remove = __devexit_p(mxs_pinctrl_remove),
289
+
};
290
+
291
+
static int __init imx23_pinctrl_init(void)
292
+
{
293
+
return platform_driver_register(&imx23_pinctrl_driver);
294
+
}
295
+
arch_initcall(imx23_pinctrl_init);
296
+
297
+
static void __exit imx23_pinctrl_exit(void)
298
+
{
299
+
platform_driver_unregister(&imx23_pinctrl_driver);
300
+
}
301
+
module_exit(imx23_pinctrl_exit);
302
+
303
+
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
304
+
MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
305
+
MODULE_LICENSE("GPL v2");
+421
drivers/pinctrl/pinctrl-imx28.c
+421
drivers/pinctrl/pinctrl-imx28.c
···
1
+
/*
2
+
* Copyright 2012 Freescale Semiconductor, Inc.
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
#include <linux/init.h>
13
+
#include <linux/module.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/pinctrl/pinctrl.h>
16
+
#include "pinctrl-mxs.h"
17
+
18
+
enum imx28_pin_enum {
19
+
GPMI_D00 = PINID(0, 0),
20
+
GPMI_D01 = PINID(0, 1),
21
+
GPMI_D02 = PINID(0, 2),
22
+
GPMI_D03 = PINID(0, 3),
23
+
GPMI_D04 = PINID(0, 4),
24
+
GPMI_D05 = PINID(0, 5),
25
+
GPMI_D06 = PINID(0, 6),
26
+
GPMI_D07 = PINID(0, 7),
27
+
GPMI_CE0N = PINID(0, 16),
28
+
GPMI_CE1N = PINID(0, 17),
29
+
GPMI_CE2N = PINID(0, 18),
30
+
GPMI_CE3N = PINID(0, 19),
31
+
GPMI_RDY0 = PINID(0, 20),
32
+
GPMI_RDY1 = PINID(0, 21),
33
+
GPMI_RDY2 = PINID(0, 22),
34
+
GPMI_RDY3 = PINID(0, 23),
35
+
GPMI_RDN = PINID(0, 24),
36
+
GPMI_WRN = PINID(0, 25),
37
+
GPMI_ALE = PINID(0, 26),
38
+
GPMI_CLE = PINID(0, 27),
39
+
GPMI_RESETN = PINID(0, 28),
40
+
LCD_D00 = PINID(1, 0),
41
+
LCD_D01 = PINID(1, 1),
42
+
LCD_D02 = PINID(1, 2),
43
+
LCD_D03 = PINID(1, 3),
44
+
LCD_D04 = PINID(1, 4),
45
+
LCD_D05 = PINID(1, 5),
46
+
LCD_D06 = PINID(1, 6),
47
+
LCD_D07 = PINID(1, 7),
48
+
LCD_D08 = PINID(1, 8),
49
+
LCD_D09 = PINID(1, 9),
50
+
LCD_D10 = PINID(1, 10),
51
+
LCD_D11 = PINID(1, 11),
52
+
LCD_D12 = PINID(1, 12),
53
+
LCD_D13 = PINID(1, 13),
54
+
LCD_D14 = PINID(1, 14),
55
+
LCD_D15 = PINID(1, 15),
56
+
LCD_D16 = PINID(1, 16),
57
+
LCD_D17 = PINID(1, 17),
58
+
LCD_D18 = PINID(1, 18),
59
+
LCD_D19 = PINID(1, 19),
60
+
LCD_D20 = PINID(1, 20),
61
+
LCD_D21 = PINID(1, 21),
62
+
LCD_D22 = PINID(1, 22),
63
+
LCD_D23 = PINID(1, 23),
64
+
LCD_RD_E = PINID(1, 24),
65
+
LCD_WR_RWN = PINID(1, 25),
66
+
LCD_RS = PINID(1, 26),
67
+
LCD_CS = PINID(1, 27),
68
+
LCD_VSYNC = PINID(1, 28),
69
+
LCD_HSYNC = PINID(1, 29),
70
+
LCD_DOTCLK = PINID(1, 30),
71
+
LCD_ENABLE = PINID(1, 31),
72
+
SSP0_DATA0 = PINID(2, 0),
73
+
SSP0_DATA1 = PINID(2, 1),
74
+
SSP0_DATA2 = PINID(2, 2),
75
+
SSP0_DATA3 = PINID(2, 3),
76
+
SSP0_DATA4 = PINID(2, 4),
77
+
SSP0_DATA5 = PINID(2, 5),
78
+
SSP0_DATA6 = PINID(2, 6),
79
+
SSP0_DATA7 = PINID(2, 7),
80
+
SSP0_CMD = PINID(2, 8),
81
+
SSP0_DETECT = PINID(2, 9),
82
+
SSP0_SCK = PINID(2, 10),
83
+
SSP1_SCK = PINID(2, 12),
84
+
SSP1_CMD = PINID(2, 13),
85
+
SSP1_DATA0 = PINID(2, 14),
86
+
SSP1_DATA3 = PINID(2, 15),
87
+
SSP2_SCK = PINID(2, 16),
88
+
SSP2_MOSI = PINID(2, 17),
89
+
SSP2_MISO = PINID(2, 18),
90
+
SSP2_SS0 = PINID(2, 19),
91
+
SSP2_SS1 = PINID(2, 20),
92
+
SSP2_SS2 = PINID(2, 21),
93
+
SSP3_SCK = PINID(2, 24),
94
+
SSP3_MOSI = PINID(2, 25),
95
+
SSP3_MISO = PINID(2, 26),
96
+
SSP3_SS0 = PINID(2, 27),
97
+
AUART0_RX = PINID(3, 0),
98
+
AUART0_TX = PINID(3, 1),
99
+
AUART0_CTS = PINID(3, 2),
100
+
AUART0_RTS = PINID(3, 3),
101
+
AUART1_RX = PINID(3, 4),
102
+
AUART1_TX = PINID(3, 5),
103
+
AUART1_CTS = PINID(3, 6),
104
+
AUART1_RTS = PINID(3, 7),
105
+
AUART2_RX = PINID(3, 8),
106
+
AUART2_TX = PINID(3, 9),
107
+
AUART2_CTS = PINID(3, 10),
108
+
AUART2_RTS = PINID(3, 11),
109
+
AUART3_RX = PINID(3, 12),
110
+
AUART3_TX = PINID(3, 13),
111
+
AUART3_CTS = PINID(3, 14),
112
+
AUART3_RTS = PINID(3, 15),
113
+
PWM0 = PINID(3, 16),
114
+
PWM1 = PINID(3, 17),
115
+
PWM2 = PINID(3, 18),
116
+
SAIF0_MCLK = PINID(3, 20),
117
+
SAIF0_LRCLK = PINID(3, 21),
118
+
SAIF0_BITCLK = PINID(3, 22),
119
+
SAIF0_SDATA0 = PINID(3, 23),
120
+
I2C0_SCL = PINID(3, 24),
121
+
I2C0_SDA = PINID(3, 25),
122
+
SAIF1_SDATA0 = PINID(3, 26),
123
+
SPDIF = PINID(3, 27),
124
+
PWM3 = PINID(3, 28),
125
+
PWM4 = PINID(3, 29),
126
+
LCD_RESET = PINID(3, 30),
127
+
ENET0_MDC = PINID(4, 0),
128
+
ENET0_MDIO = PINID(4, 1),
129
+
ENET0_RX_EN = PINID(4, 2),
130
+
ENET0_RXD0 = PINID(4, 3),
131
+
ENET0_RXD1 = PINID(4, 4),
132
+
ENET0_TX_CLK = PINID(4, 5),
133
+
ENET0_TX_EN = PINID(4, 6),
134
+
ENET0_TXD0 = PINID(4, 7),
135
+
ENET0_TXD1 = PINID(4, 8),
136
+
ENET0_RXD2 = PINID(4, 9),
137
+
ENET0_RXD3 = PINID(4, 10),
138
+
ENET0_TXD2 = PINID(4, 11),
139
+
ENET0_TXD3 = PINID(4, 12),
140
+
ENET0_RX_CLK = PINID(4, 13),
141
+
ENET0_COL = PINID(4, 14),
142
+
ENET0_CRS = PINID(4, 15),
143
+
ENET_CLK = PINID(4, 16),
144
+
JTAG_RTCK = PINID(4, 20),
145
+
EMI_D00 = PINID(5, 0),
146
+
EMI_D01 = PINID(5, 1),
147
+
EMI_D02 = PINID(5, 2),
148
+
EMI_D03 = PINID(5, 3),
149
+
EMI_D04 = PINID(5, 4),
150
+
EMI_D05 = PINID(5, 5),
151
+
EMI_D06 = PINID(5, 6),
152
+
EMI_D07 = PINID(5, 7),
153
+
EMI_D08 = PINID(5, 8),
154
+
EMI_D09 = PINID(5, 9),
155
+
EMI_D10 = PINID(5, 10),
156
+
EMI_D11 = PINID(5, 11),
157
+
EMI_D12 = PINID(5, 12),
158
+
EMI_D13 = PINID(5, 13),
159
+
EMI_D14 = PINID(5, 14),
160
+
EMI_D15 = PINID(5, 15),
161
+
EMI_ODT0 = PINID(5, 16),
162
+
EMI_DQM0 = PINID(5, 17),
163
+
EMI_ODT1 = PINID(5, 18),
164
+
EMI_DQM1 = PINID(5, 19),
165
+
EMI_DDR_OPEN_FB = PINID(5, 20),
166
+
EMI_CLK = PINID(5, 21),
167
+
EMI_DQS0 = PINID(5, 22),
168
+
EMI_DQS1 = PINID(5, 23),
169
+
EMI_DDR_OPEN = PINID(5, 26),
170
+
EMI_A00 = PINID(6, 0),
171
+
EMI_A01 = PINID(6, 1),
172
+
EMI_A02 = PINID(6, 2),
173
+
EMI_A03 = PINID(6, 3),
174
+
EMI_A04 = PINID(6, 4),
175
+
EMI_A05 = PINID(6, 5),
176
+
EMI_A06 = PINID(6, 6),
177
+
EMI_A07 = PINID(6, 7),
178
+
EMI_A08 = PINID(6, 8),
179
+
EMI_A09 = PINID(6, 9),
180
+
EMI_A10 = PINID(6, 10),
181
+
EMI_A11 = PINID(6, 11),
182
+
EMI_A12 = PINID(6, 12),
183
+
EMI_A13 = PINID(6, 13),
184
+
EMI_A14 = PINID(6, 14),
185
+
EMI_BA0 = PINID(6, 16),
186
+
EMI_BA1 = PINID(6, 17),
187
+
EMI_BA2 = PINID(6, 18),
188
+
EMI_CASN = PINID(6, 19),
189
+
EMI_RASN = PINID(6, 20),
190
+
EMI_WEN = PINID(6, 21),
191
+
EMI_CE0N = PINID(6, 22),
192
+
EMI_CE1N = PINID(6, 23),
193
+
EMI_CKE = PINID(6, 24),
194
+
};
195
+
196
+
static const struct pinctrl_pin_desc imx28_pins[] = {
197
+
MXS_PINCTRL_PIN(GPMI_D00),
198
+
MXS_PINCTRL_PIN(GPMI_D01),
199
+
MXS_PINCTRL_PIN(GPMI_D02),
200
+
MXS_PINCTRL_PIN(GPMI_D03),
201
+
MXS_PINCTRL_PIN(GPMI_D04),
202
+
MXS_PINCTRL_PIN(GPMI_D05),
203
+
MXS_PINCTRL_PIN(GPMI_D06),
204
+
MXS_PINCTRL_PIN(GPMI_D07),
205
+
MXS_PINCTRL_PIN(GPMI_CE0N),
206
+
MXS_PINCTRL_PIN(GPMI_CE1N),
207
+
MXS_PINCTRL_PIN(GPMI_CE2N),
208
+
MXS_PINCTRL_PIN(GPMI_CE3N),
209
+
MXS_PINCTRL_PIN(GPMI_RDY0),
210
+
MXS_PINCTRL_PIN(GPMI_RDY1),
211
+
MXS_PINCTRL_PIN(GPMI_RDY2),
212
+
MXS_PINCTRL_PIN(GPMI_RDY3),
213
+
MXS_PINCTRL_PIN(GPMI_RDN),
214
+
MXS_PINCTRL_PIN(GPMI_WRN),
215
+
MXS_PINCTRL_PIN(GPMI_ALE),
216
+
MXS_PINCTRL_PIN(GPMI_CLE),
217
+
MXS_PINCTRL_PIN(GPMI_RESETN),
218
+
MXS_PINCTRL_PIN(LCD_D00),
219
+
MXS_PINCTRL_PIN(LCD_D01),
220
+
MXS_PINCTRL_PIN(LCD_D02),
221
+
MXS_PINCTRL_PIN(LCD_D03),
222
+
MXS_PINCTRL_PIN(LCD_D04),
223
+
MXS_PINCTRL_PIN(LCD_D05),
224
+
MXS_PINCTRL_PIN(LCD_D06),
225
+
MXS_PINCTRL_PIN(LCD_D07),
226
+
MXS_PINCTRL_PIN(LCD_D08),
227
+
MXS_PINCTRL_PIN(LCD_D09),
228
+
MXS_PINCTRL_PIN(LCD_D10),
229
+
MXS_PINCTRL_PIN(LCD_D11),
230
+
MXS_PINCTRL_PIN(LCD_D12),
231
+
MXS_PINCTRL_PIN(LCD_D13),
232
+
MXS_PINCTRL_PIN(LCD_D14),
233
+
MXS_PINCTRL_PIN(LCD_D15),
234
+
MXS_PINCTRL_PIN(LCD_D16),
235
+
MXS_PINCTRL_PIN(LCD_D17),
236
+
MXS_PINCTRL_PIN(LCD_D18),
237
+
MXS_PINCTRL_PIN(LCD_D19),
238
+
MXS_PINCTRL_PIN(LCD_D20),
239
+
MXS_PINCTRL_PIN(LCD_D21),
240
+
MXS_PINCTRL_PIN(LCD_D22),
241
+
MXS_PINCTRL_PIN(LCD_D23),
242
+
MXS_PINCTRL_PIN(LCD_RD_E),
243
+
MXS_PINCTRL_PIN(LCD_WR_RWN),
244
+
MXS_PINCTRL_PIN(LCD_RS),
245
+
MXS_PINCTRL_PIN(LCD_CS),
246
+
MXS_PINCTRL_PIN(LCD_VSYNC),
247
+
MXS_PINCTRL_PIN(LCD_HSYNC),
248
+
MXS_PINCTRL_PIN(LCD_DOTCLK),
249
+
MXS_PINCTRL_PIN(LCD_ENABLE),
250
+
MXS_PINCTRL_PIN(SSP0_DATA0),
251
+
MXS_PINCTRL_PIN(SSP0_DATA1),
252
+
MXS_PINCTRL_PIN(SSP0_DATA2),
253
+
MXS_PINCTRL_PIN(SSP0_DATA3),
254
+
MXS_PINCTRL_PIN(SSP0_DATA4),
255
+
MXS_PINCTRL_PIN(SSP0_DATA5),
256
+
MXS_PINCTRL_PIN(SSP0_DATA6),
257
+
MXS_PINCTRL_PIN(SSP0_DATA7),
258
+
MXS_PINCTRL_PIN(SSP0_CMD),
259
+
MXS_PINCTRL_PIN(SSP0_DETECT),
260
+
MXS_PINCTRL_PIN(SSP0_SCK),
261
+
MXS_PINCTRL_PIN(SSP1_SCK),
262
+
MXS_PINCTRL_PIN(SSP1_CMD),
263
+
MXS_PINCTRL_PIN(SSP1_DATA0),
264
+
MXS_PINCTRL_PIN(SSP1_DATA3),
265
+
MXS_PINCTRL_PIN(SSP2_SCK),
266
+
MXS_PINCTRL_PIN(SSP2_MOSI),
267
+
MXS_PINCTRL_PIN(SSP2_MISO),
268
+
MXS_PINCTRL_PIN(SSP2_SS0),
269
+
MXS_PINCTRL_PIN(SSP2_SS1),
270
+
MXS_PINCTRL_PIN(SSP2_SS2),
271
+
MXS_PINCTRL_PIN(SSP3_SCK),
272
+
MXS_PINCTRL_PIN(SSP3_MOSI),
273
+
MXS_PINCTRL_PIN(SSP3_MISO),
274
+
MXS_PINCTRL_PIN(SSP3_SS0),
275
+
MXS_PINCTRL_PIN(AUART0_RX),
276
+
MXS_PINCTRL_PIN(AUART0_TX),
277
+
MXS_PINCTRL_PIN(AUART0_CTS),
278
+
MXS_PINCTRL_PIN(AUART0_RTS),
279
+
MXS_PINCTRL_PIN(AUART1_RX),
280
+
MXS_PINCTRL_PIN(AUART1_TX),
281
+
MXS_PINCTRL_PIN(AUART1_CTS),
282
+
MXS_PINCTRL_PIN(AUART1_RTS),
283
+
MXS_PINCTRL_PIN(AUART2_RX),
284
+
MXS_PINCTRL_PIN(AUART2_TX),
285
+
MXS_PINCTRL_PIN(AUART2_CTS),
286
+
MXS_PINCTRL_PIN(AUART2_RTS),
287
+
MXS_PINCTRL_PIN(AUART3_RX),
288
+
MXS_PINCTRL_PIN(AUART3_TX),
289
+
MXS_PINCTRL_PIN(AUART3_CTS),
290
+
MXS_PINCTRL_PIN(AUART3_RTS),
291
+
MXS_PINCTRL_PIN(PWM0),
292
+
MXS_PINCTRL_PIN(PWM1),
293
+
MXS_PINCTRL_PIN(PWM2),
294
+
MXS_PINCTRL_PIN(SAIF0_MCLK),
295
+
MXS_PINCTRL_PIN(SAIF0_LRCLK),
296
+
MXS_PINCTRL_PIN(SAIF0_BITCLK),
297
+
MXS_PINCTRL_PIN(SAIF0_SDATA0),
298
+
MXS_PINCTRL_PIN(I2C0_SCL),
299
+
MXS_PINCTRL_PIN(I2C0_SDA),
300
+
MXS_PINCTRL_PIN(SAIF1_SDATA0),
301
+
MXS_PINCTRL_PIN(SPDIF),
302
+
MXS_PINCTRL_PIN(PWM3),
303
+
MXS_PINCTRL_PIN(PWM4),
304
+
MXS_PINCTRL_PIN(LCD_RESET),
305
+
MXS_PINCTRL_PIN(ENET0_MDC),
306
+
MXS_PINCTRL_PIN(ENET0_MDIO),
307
+
MXS_PINCTRL_PIN(ENET0_RX_EN),
308
+
MXS_PINCTRL_PIN(ENET0_RXD0),
309
+
MXS_PINCTRL_PIN(ENET0_RXD1),
310
+
MXS_PINCTRL_PIN(ENET0_TX_CLK),
311
+
MXS_PINCTRL_PIN(ENET0_TX_EN),
312
+
MXS_PINCTRL_PIN(ENET0_TXD0),
313
+
MXS_PINCTRL_PIN(ENET0_TXD1),
314
+
MXS_PINCTRL_PIN(ENET0_RXD2),
315
+
MXS_PINCTRL_PIN(ENET0_RXD3),
316
+
MXS_PINCTRL_PIN(ENET0_TXD2),
317
+
MXS_PINCTRL_PIN(ENET0_TXD3),
318
+
MXS_PINCTRL_PIN(ENET0_RX_CLK),
319
+
MXS_PINCTRL_PIN(ENET0_COL),
320
+
MXS_PINCTRL_PIN(ENET0_CRS),
321
+
MXS_PINCTRL_PIN(ENET_CLK),
322
+
MXS_PINCTRL_PIN(JTAG_RTCK),
323
+
MXS_PINCTRL_PIN(EMI_D00),
324
+
MXS_PINCTRL_PIN(EMI_D01),
325
+
MXS_PINCTRL_PIN(EMI_D02),
326
+
MXS_PINCTRL_PIN(EMI_D03),
327
+
MXS_PINCTRL_PIN(EMI_D04),
328
+
MXS_PINCTRL_PIN(EMI_D05),
329
+
MXS_PINCTRL_PIN(EMI_D06),
330
+
MXS_PINCTRL_PIN(EMI_D07),
331
+
MXS_PINCTRL_PIN(EMI_D08),
332
+
MXS_PINCTRL_PIN(EMI_D09),
333
+
MXS_PINCTRL_PIN(EMI_D10),
334
+
MXS_PINCTRL_PIN(EMI_D11),
335
+
MXS_PINCTRL_PIN(EMI_D12),
336
+
MXS_PINCTRL_PIN(EMI_D13),
337
+
MXS_PINCTRL_PIN(EMI_D14),
338
+
MXS_PINCTRL_PIN(EMI_D15),
339
+
MXS_PINCTRL_PIN(EMI_ODT0),
340
+
MXS_PINCTRL_PIN(EMI_DQM0),
341
+
MXS_PINCTRL_PIN(EMI_ODT1),
342
+
MXS_PINCTRL_PIN(EMI_DQM1),
343
+
MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
344
+
MXS_PINCTRL_PIN(EMI_CLK),
345
+
MXS_PINCTRL_PIN(EMI_DQS0),
346
+
MXS_PINCTRL_PIN(EMI_DQS1),
347
+
MXS_PINCTRL_PIN(EMI_DDR_OPEN),
348
+
MXS_PINCTRL_PIN(EMI_A00),
349
+
MXS_PINCTRL_PIN(EMI_A01),
350
+
MXS_PINCTRL_PIN(EMI_A02),
351
+
MXS_PINCTRL_PIN(EMI_A03),
352
+
MXS_PINCTRL_PIN(EMI_A04),
353
+
MXS_PINCTRL_PIN(EMI_A05),
354
+
MXS_PINCTRL_PIN(EMI_A06),
355
+
MXS_PINCTRL_PIN(EMI_A07),
356
+
MXS_PINCTRL_PIN(EMI_A08),
357
+
MXS_PINCTRL_PIN(EMI_A09),
358
+
MXS_PINCTRL_PIN(EMI_A10),
359
+
MXS_PINCTRL_PIN(EMI_A11),
360
+
MXS_PINCTRL_PIN(EMI_A12),
361
+
MXS_PINCTRL_PIN(EMI_A13),
362
+
MXS_PINCTRL_PIN(EMI_A14),
363
+
MXS_PINCTRL_PIN(EMI_BA0),
364
+
MXS_PINCTRL_PIN(EMI_BA1),
365
+
MXS_PINCTRL_PIN(EMI_BA2),
366
+
MXS_PINCTRL_PIN(EMI_CASN),
367
+
MXS_PINCTRL_PIN(EMI_RASN),
368
+
MXS_PINCTRL_PIN(EMI_WEN),
369
+
MXS_PINCTRL_PIN(EMI_CE0N),
370
+
MXS_PINCTRL_PIN(EMI_CE1N),
371
+
MXS_PINCTRL_PIN(EMI_CKE),
372
+
};
373
+
374
+
static struct mxs_regs imx28_regs = {
375
+
.muxsel = 0x100,
376
+
.drive = 0x300,
377
+
.pull = 0x600,
378
+
};
379
+
380
+
static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
381
+
.regs = &imx28_regs,
382
+
.pins = imx28_pins,
383
+
.npins = ARRAY_SIZE(imx28_pins),
384
+
};
385
+
386
+
static int __devinit imx28_pinctrl_probe(struct platform_device *pdev)
387
+
{
388
+
return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
389
+
}
390
+
391
+
static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = {
392
+
{ .compatible = "fsl,imx28-pinctrl", },
393
+
{ /* sentinel */ }
394
+
};
395
+
MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
396
+
397
+
static struct platform_driver imx28_pinctrl_driver = {
398
+
.driver = {
399
+
.name = "imx28-pinctrl",
400
+
.owner = THIS_MODULE,
401
+
.of_match_table = imx28_pinctrl_of_match,
402
+
},
403
+
.probe = imx28_pinctrl_probe,
404
+
.remove = __devexit_p(mxs_pinctrl_remove),
405
+
};
406
+
407
+
static int __init imx28_pinctrl_init(void)
408
+
{
409
+
return platform_driver_register(&imx28_pinctrl_driver);
410
+
}
411
+
arch_initcall(imx28_pinctrl_init);
412
+
413
+
static void __exit imx28_pinctrl_exit(void)
414
+
{
415
+
platform_driver_unregister(&imx28_pinctrl_driver);
416
+
}
417
+
module_exit(imx28_pinctrl_exit);
418
+
419
+
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
420
+
MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
421
+
MODULE_LICENSE("GPL v2");
+2331
drivers/pinctrl/pinctrl-imx6q.c
+2331
drivers/pinctrl/pinctrl-imx6q.c
···
1
+
/*
2
+
* imx6q pinctrl driver based on imx pinmux core
3
+
*
4
+
* Copyright (C) 2012 Freescale Semiconductor, Inc.
5
+
* Copyright (C) 2012 Linaro, Inc.
6
+
*
7
+
* Author: Dong Aisheng <dong.aisheng@linaro.org>
8
+
*
9
+
* This program is free software; you can redistribute it and/or modify
10
+
* it under the terms of the GNU General Public License as published by
11
+
* the Free Software Foundation; either version 2 of the License, or
12
+
* (at your option) any later version.
13
+
*/
14
+
15
+
#include <linux/err.h>
16
+
#include <linux/init.h>
17
+
#include <linux/io.h>
18
+
#include <linux/module.h>
19
+
#include <linux/of.h>
20
+
#include <linux/of_device.h>
21
+
#include <linux/pinctrl/pinctrl.h>
22
+
23
+
#include "pinctrl-imx.h"
24
+
25
+
enum imx6q_pads {
26
+
MX6Q_PAD_SD2_DAT1 = 0,
27
+
MX6Q_PAD_SD2_DAT2 = 1,
28
+
MX6Q_PAD_SD2_DAT0 = 2,
29
+
MX6Q_PAD_RGMII_TXC = 3,
30
+
MX6Q_PAD_RGMII_TD0 = 4,
31
+
MX6Q_PAD_RGMII_TD1 = 5,
32
+
MX6Q_PAD_RGMII_TD2 = 6,
33
+
MX6Q_PAD_RGMII_TD3 = 7,
34
+
MX6Q_PAD_RGMII_RX_CTL = 8,
35
+
MX6Q_PAD_RGMII_RD0 = 9,
36
+
MX6Q_PAD_RGMII_TX_CTL = 10,
37
+
MX6Q_PAD_RGMII_RD1 = 11,
38
+
MX6Q_PAD_RGMII_RD2 = 12,
39
+
MX6Q_PAD_RGMII_RD3 = 13,
40
+
MX6Q_PAD_RGMII_RXC = 14,
41
+
MX6Q_PAD_EIM_A25 = 15,
42
+
MX6Q_PAD_EIM_EB2 = 16,
43
+
MX6Q_PAD_EIM_D16 = 17,
44
+
MX6Q_PAD_EIM_D17 = 18,
45
+
MX6Q_PAD_EIM_D18 = 19,
46
+
MX6Q_PAD_EIM_D19 = 20,
47
+
MX6Q_PAD_EIM_D20 = 21,
48
+
MX6Q_PAD_EIM_D21 = 22,
49
+
MX6Q_PAD_EIM_D22 = 23,
50
+
MX6Q_PAD_EIM_D23 = 24,
51
+
MX6Q_PAD_EIM_EB3 = 25,
52
+
MX6Q_PAD_EIM_D24 = 26,
53
+
MX6Q_PAD_EIM_D25 = 27,
54
+
MX6Q_PAD_EIM_D26 = 28,
55
+
MX6Q_PAD_EIM_D27 = 29,
56
+
MX6Q_PAD_EIM_D28 = 30,
57
+
MX6Q_PAD_EIM_D29 = 31,
58
+
MX6Q_PAD_EIM_D30 = 32,
59
+
MX6Q_PAD_EIM_D31 = 33,
60
+
MX6Q_PAD_EIM_A24 = 34,
61
+
MX6Q_PAD_EIM_A23 = 35,
62
+
MX6Q_PAD_EIM_A22 = 36,
63
+
MX6Q_PAD_EIM_A21 = 37,
64
+
MX6Q_PAD_EIM_A20 = 38,
65
+
MX6Q_PAD_EIM_A19 = 39,
66
+
MX6Q_PAD_EIM_A18 = 40,
67
+
MX6Q_PAD_EIM_A17 = 41,
68
+
MX6Q_PAD_EIM_A16 = 42,
69
+
MX6Q_PAD_EIM_CS0 = 43,
70
+
MX6Q_PAD_EIM_CS1 = 44,
71
+
MX6Q_PAD_EIM_OE = 45,
72
+
MX6Q_PAD_EIM_RW = 46,
73
+
MX6Q_PAD_EIM_LBA = 47,
74
+
MX6Q_PAD_EIM_EB0 = 48,
75
+
MX6Q_PAD_EIM_EB1 = 49,
76
+
MX6Q_PAD_EIM_DA0 = 50,
77
+
MX6Q_PAD_EIM_DA1 = 51,
78
+
MX6Q_PAD_EIM_DA2 = 52,
79
+
MX6Q_PAD_EIM_DA3 = 53,
80
+
MX6Q_PAD_EIM_DA4 = 54,
81
+
MX6Q_PAD_EIM_DA5 = 55,
82
+
MX6Q_PAD_EIM_DA6 = 56,
83
+
MX6Q_PAD_EIM_DA7 = 57,
84
+
MX6Q_PAD_EIM_DA8 = 58,
85
+
MX6Q_PAD_EIM_DA9 = 59,
86
+
MX6Q_PAD_EIM_DA10 = 60,
87
+
MX6Q_PAD_EIM_DA11 = 61,
88
+
MX6Q_PAD_EIM_DA12 = 62,
89
+
MX6Q_PAD_EIM_DA13 = 63,
90
+
MX6Q_PAD_EIM_DA14 = 64,
91
+
MX6Q_PAD_EIM_DA15 = 65,
92
+
MX6Q_PAD_EIM_WAIT = 66,
93
+
MX6Q_PAD_EIM_BCLK = 67,
94
+
MX6Q_PAD_DI0_DISP_CLK = 68,
95
+
MX6Q_PAD_DI0_PIN15 = 69,
96
+
MX6Q_PAD_DI0_PIN2 = 70,
97
+
MX6Q_PAD_DI0_PIN3 = 71,
98
+
MX6Q_PAD_DI0_PIN4 = 72,
99
+
MX6Q_PAD_DISP0_DAT0 = 73,
100
+
MX6Q_PAD_DISP0_DAT1 = 74,
101
+
MX6Q_PAD_DISP0_DAT2 = 75,
102
+
MX6Q_PAD_DISP0_DAT3 = 76,
103
+
MX6Q_PAD_DISP0_DAT4 = 77,
104
+
MX6Q_PAD_DISP0_DAT5 = 78,
105
+
MX6Q_PAD_DISP0_DAT6 = 79,
106
+
MX6Q_PAD_DISP0_DAT7 = 80,
107
+
MX6Q_PAD_DISP0_DAT8 = 81,
108
+
MX6Q_PAD_DISP0_DAT9 = 82,
109
+
MX6Q_PAD_DISP0_DAT10 = 83,
110
+
MX6Q_PAD_DISP0_DAT11 = 84,
111
+
MX6Q_PAD_DISP0_DAT12 = 85,
112
+
MX6Q_PAD_DISP0_DAT13 = 86,
113
+
MX6Q_PAD_DISP0_DAT14 = 87,
114
+
MX6Q_PAD_DISP0_DAT15 = 88,
115
+
MX6Q_PAD_DISP0_DAT16 = 89,
116
+
MX6Q_PAD_DISP0_DAT17 = 90,
117
+
MX6Q_PAD_DISP0_DAT18 = 91,
118
+
MX6Q_PAD_DISP0_DAT19 = 92,
119
+
MX6Q_PAD_DISP0_DAT20 = 93,
120
+
MX6Q_PAD_DISP0_DAT21 = 94,
121
+
MX6Q_PAD_DISP0_DAT22 = 95,
122
+
MX6Q_PAD_DISP0_DAT23 = 96,
123
+
MX6Q_PAD_ENET_MDIO = 97,
124
+
MX6Q_PAD_ENET_REF_CLK = 98,
125
+
MX6Q_PAD_ENET_RX_ER = 99,
126
+
MX6Q_PAD_ENET_CRS_DV = 100,
127
+
MX6Q_PAD_ENET_RXD1 = 101,
128
+
MX6Q_PAD_ENET_RXD0 = 102,
129
+
MX6Q_PAD_ENET_TX_EN = 103,
130
+
MX6Q_PAD_ENET_TXD1 = 104,
131
+
MX6Q_PAD_ENET_TXD0 = 105,
132
+
MX6Q_PAD_ENET_MDC = 106,
133
+
MX6Q_PAD_DRAM_D40 = 107,
134
+
MX6Q_PAD_DRAM_D41 = 108,
135
+
MX6Q_PAD_DRAM_D42 = 109,
136
+
MX6Q_PAD_DRAM_D43 = 110,
137
+
MX6Q_PAD_DRAM_D44 = 111,
138
+
MX6Q_PAD_DRAM_D45 = 112,
139
+
MX6Q_PAD_DRAM_D46 = 113,
140
+
MX6Q_PAD_DRAM_D47 = 114,
141
+
MX6Q_PAD_DRAM_SDQS5 = 115,
142
+
MX6Q_PAD_DRAM_DQM5 = 116,
143
+
MX6Q_PAD_DRAM_D32 = 117,
144
+
MX6Q_PAD_DRAM_D33 = 118,
145
+
MX6Q_PAD_DRAM_D34 = 119,
146
+
MX6Q_PAD_DRAM_D35 = 120,
147
+
MX6Q_PAD_DRAM_D36 = 121,
148
+
MX6Q_PAD_DRAM_D37 = 122,
149
+
MX6Q_PAD_DRAM_D38 = 123,
150
+
MX6Q_PAD_DRAM_D39 = 124,
151
+
MX6Q_PAD_DRAM_DQM4 = 125,
152
+
MX6Q_PAD_DRAM_SDQS4 = 126,
153
+
MX6Q_PAD_DRAM_D24 = 127,
154
+
MX6Q_PAD_DRAM_D25 = 128,
155
+
MX6Q_PAD_DRAM_D26 = 129,
156
+
MX6Q_PAD_DRAM_D27 = 130,
157
+
MX6Q_PAD_DRAM_D28 = 131,
158
+
MX6Q_PAD_DRAM_D29 = 132,
159
+
MX6Q_PAD_DRAM_SDQS3 = 133,
160
+
MX6Q_PAD_DRAM_D30 = 134,
161
+
MX6Q_PAD_DRAM_D31 = 135,
162
+
MX6Q_PAD_DRAM_DQM3 = 136,
163
+
MX6Q_PAD_DRAM_D16 = 137,
164
+
MX6Q_PAD_DRAM_D17 = 138,
165
+
MX6Q_PAD_DRAM_D18 = 139,
166
+
MX6Q_PAD_DRAM_D19 = 140,
167
+
MX6Q_PAD_DRAM_D20 = 141,
168
+
MX6Q_PAD_DRAM_D21 = 142,
169
+
MX6Q_PAD_DRAM_D22 = 143,
170
+
MX6Q_PAD_DRAM_SDQS2 = 144,
171
+
MX6Q_PAD_DRAM_D23 = 145,
172
+
MX6Q_PAD_DRAM_DQM2 = 146,
173
+
MX6Q_PAD_DRAM_A0 = 147,
174
+
MX6Q_PAD_DRAM_A1 = 148,
175
+
MX6Q_PAD_DRAM_A2 = 149,
176
+
MX6Q_PAD_DRAM_A3 = 150,
177
+
MX6Q_PAD_DRAM_A4 = 151,
178
+
MX6Q_PAD_DRAM_A5 = 152,
179
+
MX6Q_PAD_DRAM_A6 = 153,
180
+
MX6Q_PAD_DRAM_A7 = 154,
181
+
MX6Q_PAD_DRAM_A8 = 155,
182
+
MX6Q_PAD_DRAM_A9 = 156,
183
+
MX6Q_PAD_DRAM_A10 = 157,
184
+
MX6Q_PAD_DRAM_A11 = 158,
185
+
MX6Q_PAD_DRAM_A12 = 159,
186
+
MX6Q_PAD_DRAM_A13 = 160,
187
+
MX6Q_PAD_DRAM_A14 = 161,
188
+
MX6Q_PAD_DRAM_A15 = 162,
189
+
MX6Q_PAD_DRAM_CAS = 163,
190
+
MX6Q_PAD_DRAM_CS0 = 164,
191
+
MX6Q_PAD_DRAM_CS1 = 165,
192
+
MX6Q_PAD_DRAM_RAS = 166,
193
+
MX6Q_PAD_DRAM_RESET = 167,
194
+
MX6Q_PAD_DRAM_SDBA0 = 168,
195
+
MX6Q_PAD_DRAM_SDBA1 = 169,
196
+
MX6Q_PAD_DRAM_SDCLK_0 = 170,
197
+
MX6Q_PAD_DRAM_SDBA2 = 171,
198
+
MX6Q_PAD_DRAM_SDCKE0 = 172,
199
+
MX6Q_PAD_DRAM_SDCLK_1 = 173,
200
+
MX6Q_PAD_DRAM_SDCKE1 = 174,
201
+
MX6Q_PAD_DRAM_SDODT0 = 175,
202
+
MX6Q_PAD_DRAM_SDODT1 = 176,
203
+
MX6Q_PAD_DRAM_SDWE = 177,
204
+
MX6Q_PAD_DRAM_D0 = 178,
205
+
MX6Q_PAD_DRAM_D1 = 179,
206
+
MX6Q_PAD_DRAM_D2 = 180,
207
+
MX6Q_PAD_DRAM_D3 = 181,
208
+
MX6Q_PAD_DRAM_D4 = 182,
209
+
MX6Q_PAD_DRAM_D5 = 183,
210
+
MX6Q_PAD_DRAM_SDQS0 = 184,
211
+
MX6Q_PAD_DRAM_D6 = 185,
212
+
MX6Q_PAD_DRAM_D7 = 186,
213
+
MX6Q_PAD_DRAM_DQM0 = 187,
214
+
MX6Q_PAD_DRAM_D8 = 188,
215
+
MX6Q_PAD_DRAM_D9 = 189,
216
+
MX6Q_PAD_DRAM_D10 = 190,
217
+
MX6Q_PAD_DRAM_D11 = 191,
218
+
MX6Q_PAD_DRAM_D12 = 192,
219
+
MX6Q_PAD_DRAM_D13 = 193,
220
+
MX6Q_PAD_DRAM_D14 = 194,
221
+
MX6Q_PAD_DRAM_SDQS1 = 195,
222
+
MX6Q_PAD_DRAM_D15 = 196,
223
+
MX6Q_PAD_DRAM_DQM1 = 197,
224
+
MX6Q_PAD_DRAM_D48 = 198,
225
+
MX6Q_PAD_DRAM_D49 = 199,
226
+
MX6Q_PAD_DRAM_D50 = 200,
227
+
MX6Q_PAD_DRAM_D51 = 201,
228
+
MX6Q_PAD_DRAM_D52 = 202,
229
+
MX6Q_PAD_DRAM_D53 = 203,
230
+
MX6Q_PAD_DRAM_D54 = 204,
231
+
MX6Q_PAD_DRAM_D55 = 205,
232
+
MX6Q_PAD_DRAM_SDQS6 = 206,
233
+
MX6Q_PAD_DRAM_DQM6 = 207,
234
+
MX6Q_PAD_DRAM_D56 = 208,
235
+
MX6Q_PAD_DRAM_SDQS7 = 209,
236
+
MX6Q_PAD_DRAM_D57 = 210,
237
+
MX6Q_PAD_DRAM_D58 = 211,
238
+
MX6Q_PAD_DRAM_D59 = 212,
239
+
MX6Q_PAD_DRAM_D60 = 213,
240
+
MX6Q_PAD_DRAM_DQM7 = 214,
241
+
MX6Q_PAD_DRAM_D61 = 215,
242
+
MX6Q_PAD_DRAM_D62 = 216,
243
+
MX6Q_PAD_DRAM_D63 = 217,
244
+
MX6Q_PAD_KEY_COL0 = 218,
245
+
MX6Q_PAD_KEY_ROW0 = 219,
246
+
MX6Q_PAD_KEY_COL1 = 220,
247
+
MX6Q_PAD_KEY_ROW1 = 221,
248
+
MX6Q_PAD_KEY_COL2 = 222,
249
+
MX6Q_PAD_KEY_ROW2 = 223,
250
+
MX6Q_PAD_KEY_COL3 = 224,
251
+
MX6Q_PAD_KEY_ROW3 = 225,
252
+
MX6Q_PAD_KEY_COL4 = 226,
253
+
MX6Q_PAD_KEY_ROW4 = 227,
254
+
MX6Q_PAD_GPIO_0 = 228,
255
+
MX6Q_PAD_GPIO_1 = 229,
256
+
MX6Q_PAD_GPIO_9 = 230,
257
+
MX6Q_PAD_GPIO_3 = 231,
258
+
MX6Q_PAD_GPIO_6 = 232,
259
+
MX6Q_PAD_GPIO_2 = 233,
260
+
MX6Q_PAD_GPIO_4 = 234,
261
+
MX6Q_PAD_GPIO_5 = 235,
262
+
MX6Q_PAD_GPIO_7 = 236,
263
+
MX6Q_PAD_GPIO_8 = 237,
264
+
MX6Q_PAD_GPIO_16 = 238,
265
+
MX6Q_PAD_GPIO_17 = 239,
266
+
MX6Q_PAD_GPIO_18 = 240,
267
+
MX6Q_PAD_GPIO_19 = 241,
268
+
MX6Q_PAD_CSI0_PIXCLK = 242,
269
+
MX6Q_PAD_CSI0_MCLK = 243,
270
+
MX6Q_PAD_CSI0_DATA_EN = 244,
271
+
MX6Q_PAD_CSI0_VSYNC = 245,
272
+
MX6Q_PAD_CSI0_DAT4 = 246,
273
+
MX6Q_PAD_CSI0_DAT5 = 247,
274
+
MX6Q_PAD_CSI0_DAT6 = 248,
275
+
MX6Q_PAD_CSI0_DAT7 = 249,
276
+
MX6Q_PAD_CSI0_DAT8 = 250,
277
+
MX6Q_PAD_CSI0_DAT9 = 251,
278
+
MX6Q_PAD_CSI0_DAT10 = 252,
279
+
MX6Q_PAD_CSI0_DAT11 = 253,
280
+
MX6Q_PAD_CSI0_DAT12 = 254,
281
+
MX6Q_PAD_CSI0_DAT13 = 255,
282
+
MX6Q_PAD_CSI0_DAT14 = 256,
283
+
MX6Q_PAD_CSI0_DAT15 = 257,
284
+
MX6Q_PAD_CSI0_DAT16 = 258,
285
+
MX6Q_PAD_CSI0_DAT17 = 259,
286
+
MX6Q_PAD_CSI0_DAT18 = 260,
287
+
MX6Q_PAD_CSI0_DAT19 = 261,
288
+
MX6Q_PAD_JTAG_TMS = 262,
289
+
MX6Q_PAD_JTAG_MOD = 263,
290
+
MX6Q_PAD_JTAG_TRSTB = 264,
291
+
MX6Q_PAD_JTAG_TDI = 265,
292
+
MX6Q_PAD_JTAG_TCK = 266,
293
+
MX6Q_PAD_JTAG_TDO = 267,
294
+
MX6Q_PAD_LVDS1_TX3_P = 268,
295
+
MX6Q_PAD_LVDS1_TX2_P = 269,
296
+
MX6Q_PAD_LVDS1_CLK_P = 270,
297
+
MX6Q_PAD_LVDS1_TX1_P = 271,
298
+
MX6Q_PAD_LVDS1_TX0_P = 272,
299
+
MX6Q_PAD_LVDS0_TX3_P = 273,
300
+
MX6Q_PAD_LVDS0_CLK_P = 274,
301
+
MX6Q_PAD_LVDS0_TX2_P = 275,
302
+
MX6Q_PAD_LVDS0_TX1_P = 276,
303
+
MX6Q_PAD_LVDS0_TX0_P = 277,
304
+
MX6Q_PAD_TAMPER = 278,
305
+
MX6Q_PAD_PMIC_ON_REQ = 279,
306
+
MX6Q_PAD_PMIC_STBY_REQ = 280,
307
+
MX6Q_PAD_POR_B = 281,
308
+
MX6Q_PAD_BOOT_MODE1 = 282,
309
+
MX6Q_PAD_RESET_IN_B = 283,
310
+
MX6Q_PAD_BOOT_MODE0 = 284,
311
+
MX6Q_PAD_TEST_MODE = 285,
312
+
MX6Q_PAD_SD3_DAT7 = 286,
313
+
MX6Q_PAD_SD3_DAT6 = 287,
314
+
MX6Q_PAD_SD3_DAT5 = 288,
315
+
MX6Q_PAD_SD3_DAT4 = 289,
316
+
MX6Q_PAD_SD3_CMD = 290,
317
+
MX6Q_PAD_SD3_CLK = 291,
318
+
MX6Q_PAD_SD3_DAT0 = 292,
319
+
MX6Q_PAD_SD3_DAT1 = 293,
320
+
MX6Q_PAD_SD3_DAT2 = 294,
321
+
MX6Q_PAD_SD3_DAT3 = 295,
322
+
MX6Q_PAD_SD3_RST = 296,
323
+
MX6Q_PAD_NANDF_CLE = 297,
324
+
MX6Q_PAD_NANDF_ALE = 298,
325
+
MX6Q_PAD_NANDF_WP_B = 299,
326
+
MX6Q_PAD_NANDF_RB0 = 300,
327
+
MX6Q_PAD_NANDF_CS0 = 301,
328
+
MX6Q_PAD_NANDF_CS1 = 302,
329
+
MX6Q_PAD_NANDF_CS2 = 303,
330
+
MX6Q_PAD_NANDF_CS3 = 304,
331
+
MX6Q_PAD_SD4_CMD = 305,
332
+
MX6Q_PAD_SD4_CLK = 306,
333
+
MX6Q_PAD_NANDF_D0 = 307,
334
+
MX6Q_PAD_NANDF_D1 = 308,
335
+
MX6Q_PAD_NANDF_D2 = 309,
336
+
MX6Q_PAD_NANDF_D3 = 310,
337
+
MX6Q_PAD_NANDF_D4 = 311,
338
+
MX6Q_PAD_NANDF_D5 = 312,
339
+
MX6Q_PAD_NANDF_D6 = 313,
340
+
MX6Q_PAD_NANDF_D7 = 314,
341
+
MX6Q_PAD_SD4_DAT0 = 315,
342
+
MX6Q_PAD_SD4_DAT1 = 316,
343
+
MX6Q_PAD_SD4_DAT2 = 317,
344
+
MX6Q_PAD_SD4_DAT3 = 318,
345
+
MX6Q_PAD_SD4_DAT4 = 319,
346
+
MX6Q_PAD_SD4_DAT5 = 320,
347
+
MX6Q_PAD_SD4_DAT6 = 321,
348
+
MX6Q_PAD_SD4_DAT7 = 322,
349
+
MX6Q_PAD_SD1_DAT1 = 323,
350
+
MX6Q_PAD_SD1_DAT0 = 324,
351
+
MX6Q_PAD_SD1_DAT3 = 325,
352
+
MX6Q_PAD_SD1_CMD = 326,
353
+
MX6Q_PAD_SD1_DAT2 = 327,
354
+
MX6Q_PAD_SD1_CLK = 328,
355
+
MX6Q_PAD_SD2_CLK = 329,
356
+
MX6Q_PAD_SD2_CMD = 330,
357
+
MX6Q_PAD_SD2_DAT3 = 331,
358
+
};
359
+
360
+
/* imx6q register maps */
361
+
static struct imx_pin_reg imx6q_pin_regs[] = {
362
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
363
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */
364
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */
365
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
366
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */
367
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */
368
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */
369
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */
370
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
371
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */
372
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */
373
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
374
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */
375
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
376
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */
377
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */
378
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
379
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */
380
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
381
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */
382
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */
383
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */
384
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */
385
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */
386
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
387
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */
388
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */
389
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */
390
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */
391
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */
392
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
393
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */
394
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */
395
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */
396
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
397
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */
398
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */
399
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */
400
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */
401
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
402
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */
403
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */
404
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */
405
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */
406
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
407
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */
408
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */
409
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */
410
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
411
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */
412
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */
413
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */
414
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
415
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */
416
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */
417
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */
418
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
419
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */
420
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */
421
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */
422
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */
423
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
424
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */
425
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */
426
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */
427
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */
428
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
429
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */
430
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */
431
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */
432
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
433
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */
434
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */
435
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */
436
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
437
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */
438
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */
439
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */
440
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */
441
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */
442
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */
443
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */
444
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */
445
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */
446
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */
447
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */
448
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */
449
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
450
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */
451
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */
452
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */
453
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */
454
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */
455
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */
456
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
457
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */
458
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */
459
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */
460
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */
461
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */
462
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */
463
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
464
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */
465
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */
466
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */
467
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */
468
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */
469
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */
470
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */
471
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
472
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */
473
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */
474
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */
475
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */
476
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */
477
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */
478
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */
479
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */
480
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */
481
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */
482
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */
483
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
484
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */
485
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */
486
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */
487
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */
488
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */
489
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */
490
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */
491
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */
492
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */
493
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */
494
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */
495
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */
496
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */
497
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */
498
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */
499
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */
500
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */
501
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */
502
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */
503
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */
504
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */
505
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */
506
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
507
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */
508
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */
509
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */
510
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */
511
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */
512
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */
513
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */
514
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
515
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */
516
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */
517
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */
518
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */
519
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */
520
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */
521
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */
522
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */
523
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */
524
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */
525
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */
526
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */
527
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */
528
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */
529
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */
530
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */
531
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
532
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */
533
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */
534
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */
535
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */
536
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */
537
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */
538
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
539
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */
540
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */
541
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */
542
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */
543
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */
544
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */
545
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */
546
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */
547
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */
548
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */
549
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */
550
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */
551
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */
552
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */
553
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */
554
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */
555
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */
556
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */
557
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */
558
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */
559
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */
560
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */
561
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */
562
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */
563
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */
564
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */
565
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */
566
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */
567
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */
568
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */
569
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */
570
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */
571
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */
572
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */
573
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */
574
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */
575
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */
576
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */
577
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */
578
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */
579
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */
580
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */
581
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */
582
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */
583
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */
584
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */
585
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */
586
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */
587
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */
588
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */
589
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */
590
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */
591
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */
592
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */
593
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */
594
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */
595
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */
596
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */
597
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */
598
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */
599
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */
600
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */
601
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */
602
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */
603
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */
604
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */
605
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */
606
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */
607
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */
608
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */
609
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */
610
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */
611
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */
612
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */
613
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */
614
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */
615
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */
616
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */
617
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */
618
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */
619
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */
620
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */
621
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */
622
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */
623
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */
624
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */
625
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */
626
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */
627
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */
628
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */
629
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */
630
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */
631
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */
632
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */
633
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */
634
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */
635
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */
636
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */
637
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */
638
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */
639
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */
640
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */
641
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */
642
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */
643
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */
644
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */
645
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */
646
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */
647
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */
648
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */
649
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */
650
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */
651
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */
652
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */
653
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */
654
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */
655
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */
656
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */
657
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */
658
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */
659
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */
660
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */
661
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */
662
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */
663
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */
664
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */
665
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */
666
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */
667
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */
668
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */
669
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */
670
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */
671
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */
672
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */
673
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */
674
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */
675
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */
676
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */
677
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */
678
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */
679
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */
680
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */
681
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */
682
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */
683
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */
684
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */
685
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */
686
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */
687
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */
688
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */
689
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */
690
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */
691
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */
692
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */
693
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */
694
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */
695
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */
696
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */
697
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */
698
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */
699
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */
700
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */
701
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */
702
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */
703
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */
704
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */
705
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */
706
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */
707
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */
708
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */
709
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */
710
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */
711
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */
712
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */
713
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */
714
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */
715
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */
716
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */
717
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */
718
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */
719
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */
720
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */
721
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */
722
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */
723
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */
724
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */
725
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */
726
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */
727
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */
728
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */
729
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */
730
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */
731
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */
732
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */
733
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */
734
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */
735
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */
736
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */
737
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */
738
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */
739
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */
740
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */
741
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */
742
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */
743
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */
744
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */
745
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */
746
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */
747
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */
748
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */
749
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */
750
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */
751
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */
752
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */
753
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */
754
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */
755
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */
756
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */
757
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */
758
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */
759
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */
760
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */
761
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */
762
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */
763
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */
764
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */
765
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */
766
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */
767
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */
768
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */
769
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */
770
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */
771
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */
772
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */
773
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */
774
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */
775
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */
776
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */
777
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */
778
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */
779
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */
780
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */
781
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */
782
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */
783
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */
784
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */
785
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */
786
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */
787
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */
788
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */
789
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */
790
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */
791
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */
792
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */
793
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */
794
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */
795
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */
796
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */
797
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */
798
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */
799
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */
800
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */
801
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */
802
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */
803
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */
804
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
805
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */
806
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */
807
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */
808
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */
809
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */
810
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */
811
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */
812
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
813
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */
814
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */
815
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */
816
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */
817
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */
818
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */
819
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */
820
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */
821
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */
822
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */
823
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */
824
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */
825
+
IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */
826
+
IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */
827
+
IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */
828
+
IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */
829
+
IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */
830
+
IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */
831
+
IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */
832
+
IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */
833
+
IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */
834
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */
835
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */
836
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */
837
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */
838
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */
839
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */
840
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */
841
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */
842
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
843
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */
844
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */
845
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */
846
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */
847
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */
848
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */
849
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
850
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */
851
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */
852
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */
853
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */
854
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */
855
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */
856
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */
857
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
858
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */
859
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */
860
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */
861
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */
862
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */
863
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */
864
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */
865
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
866
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */
867
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
868
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */
869
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */
870
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */
871
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */
872
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */
873
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */
874
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */
875
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */
876
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */
877
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */
878
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */
879
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */
880
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */
881
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */
882
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */
883
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */
884
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */
885
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */
886
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */
887
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */
888
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */
889
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */
890
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
891
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */
892
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */
893
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */
894
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */
895
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */
896
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */
897
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */
898
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */
899
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */
900
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */
901
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */
902
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */
903
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */
904
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */
905
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */
906
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
907
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */
908
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */
909
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */
910
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */
911
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */
912
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */
913
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */
914
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */
915
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */
916
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */
917
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */
918
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */
919
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */
920
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */
921
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */
922
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */
923
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */
924
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */
925
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */
926
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */
927
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */
928
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */
929
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */
930
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */
931
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */
932
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */
933
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */
934
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */
935
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */
936
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
937
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */
938
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */
939
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */
940
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */
941
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */
942
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */
943
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */
944
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
945
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */
946
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */
947
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */
948
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */
949
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */
950
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */
951
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */
952
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */
953
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */
954
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */
955
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */
956
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */
957
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */
958
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */
959
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */
960
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */
961
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */
962
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */
963
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */
964
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */
965
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */
966
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */
967
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */
968
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */
969
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */
970
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */
971
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */
972
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */
973
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
974
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */
975
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */
976
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */
977
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */
978
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */
979
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */
980
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
981
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */
982
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */
983
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */
984
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */
985
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */
986
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */
987
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */
988
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */
989
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */
990
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */
991
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */
992
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */
993
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */
994
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */
995
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
996
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
997
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */
998
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */
999
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */
1000
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */
1001
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */
1002
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */
1003
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
1004
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
1005
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */
1006
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */
1007
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */
1008
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */
1009
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */
1010
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */
1011
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
1012
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
1013
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */
1014
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */
1015
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */
1016
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */
1017
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */
1018
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */
1019
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
1020
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
1021
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */
1022
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */
1023
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */
1024
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */
1025
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */
1026
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */
1027
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
1028
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */
1029
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */
1030
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */
1031
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */
1032
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */
1033
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */
1034
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */
1035
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
1036
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */
1037
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */
1038
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */
1039
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */
1040
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */
1041
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */
1042
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */
1043
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
1044
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */
1045
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */
1046
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */
1047
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */
1048
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */
1049
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */
1050
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */
1051
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
1052
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */
1053
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */
1054
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */
1055
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */
1056
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */
1057
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
1058
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */
1059
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */
1060
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */
1061
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */
1062
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */
1063
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */
1064
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
1065
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */
1066
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */
1067
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */
1068
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */
1069
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */
1070
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */
1071
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */
1072
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */
1073
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */
1074
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */
1075
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */
1076
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */
1077
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */
1078
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */
1079
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */
1080
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */
1081
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */
1082
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */
1083
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */
1084
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */
1085
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */
1086
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */
1087
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */
1088
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */
1089
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */
1090
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */
1091
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */
1092
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */
1093
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */
1094
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */
1095
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */
1096
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */
1097
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */
1098
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */
1099
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */
1100
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */
1101
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */
1102
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */
1103
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */
1104
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */
1105
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */
1106
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */
1107
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */
1108
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */
1109
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */
1110
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */
1111
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */
1112
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */
1113
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */
1114
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */
1115
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */
1116
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */
1117
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */
1118
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */
1119
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */
1120
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */
1121
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */
1122
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */
1123
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */
1124
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */
1125
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */
1126
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */
1127
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */
1128
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */
1129
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */
1130
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */
1131
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */
1132
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */
1133
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */
1134
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */
1135
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */
1136
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */
1137
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */
1138
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */
1139
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */
1140
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */
1141
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */
1142
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */
1143
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */
1144
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */
1145
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */
1146
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */
1147
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */
1148
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */
1149
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */
1150
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */
1151
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */
1152
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */
1153
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */
1154
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */
1155
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */
1156
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */
1157
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */
1158
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */
1159
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */
1160
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */
1161
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */
1162
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */
1163
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */
1164
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */
1165
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */
1166
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */
1167
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */
1168
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */
1169
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */
1170
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */
1171
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */
1172
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */
1173
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */
1174
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */
1175
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */
1176
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */
1177
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */
1178
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */
1179
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */
1180
+
IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */
1181
+
IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */
1182
+
IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */
1183
+
IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */
1184
+
IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */
1185
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */
1186
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */
1187
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */
1188
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */
1189
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */
1190
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */
1191
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */
1192
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */
1193
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */
1194
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */
1195
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */
1196
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */
1197
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */
1198
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */
1199
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */
1200
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */
1201
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */
1202
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */
1203
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */
1204
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */
1205
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */
1206
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */
1207
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */
1208
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */
1209
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */
1210
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */
1211
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */
1212
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */
1213
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */
1214
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */
1215
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */
1216
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */
1217
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */
1218
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */
1219
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */
1220
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */
1221
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */
1222
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */
1223
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */
1224
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */
1225
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */
1226
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */
1227
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */
1228
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */
1229
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */
1230
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */
1231
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */
1232
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */
1233
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */
1234
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */
1235
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */
1236
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */
1237
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
1238
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */
1239
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */
1240
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */
1241
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */
1242
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */
1243
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */
1244
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */
1245
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
1246
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */
1247
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
1248
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */
1249
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */
1250
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */
1251
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */
1252
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
1253
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
1254
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */
1255
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */
1256
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */
1257
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */
1258
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */
1259
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */
1260
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */
1261
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
1262
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */
1263
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */
1264
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */
1265
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */
1266
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */
1267
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */
1268
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */
1269
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */
1270
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */
1271
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */
1272
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */
1273
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */
1274
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */
1275
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */
1276
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */
1277
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */
1278
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */
1279
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */
1280
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */
1281
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */
1282
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */
1283
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */
1284
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */
1285
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */
1286
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */
1287
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */
1288
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */
1289
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */
1290
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */
1291
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */
1292
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */
1293
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */
1294
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */
1295
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */
1296
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */
1297
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */
1298
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */
1299
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */
1300
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */
1301
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */
1302
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */
1303
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */
1304
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */
1305
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */
1306
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */
1307
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */
1308
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */
1309
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
1310
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */
1311
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */
1312
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */
1313
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */
1314
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */
1315
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */
1316
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */
1317
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */
1318
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */
1319
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */
1320
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */
1321
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */
1322
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */
1323
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */
1324
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */
1325
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */
1326
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */
1327
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */
1328
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */
1329
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */
1330
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */
1331
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */
1332
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */
1333
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */
1334
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */
1335
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */
1336
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */
1337
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */
1338
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */
1339
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */
1340
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */
1341
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */
1342
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */
1343
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */
1344
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */
1345
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */
1346
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */
1347
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */
1348
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */
1349
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */
1350
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */
1351
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */
1352
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */
1353
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */
1354
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */
1355
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */
1356
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */
1357
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
1358
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */
1359
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */
1360
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */
1361
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */
1362
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */
1363
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */
1364
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */
1365
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
1366
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
1367
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */
1368
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */
1369
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */
1370
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */
1371
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */
1372
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */
1373
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
1374
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
1375
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */
1376
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */
1377
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */
1378
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */
1379
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */
1380
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */
1381
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */
1382
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */
1383
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */
1384
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */
1385
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */
1386
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */
1387
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */
1388
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */
1389
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */
1390
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */
1391
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */
1392
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */
1393
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */
1394
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */
1395
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */
1396
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */
1397
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */
1398
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */
1399
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */
1400
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */
1401
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */
1402
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */
1403
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */
1404
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */
1405
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */
1406
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */
1407
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */
1408
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */
1409
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */
1410
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */
1411
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */
1412
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */
1413
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */
1414
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */
1415
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */
1416
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */
1417
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */
1418
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */
1419
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */
1420
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */
1421
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */
1422
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */
1423
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */
1424
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */
1425
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */
1426
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
1427
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */
1428
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */
1429
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */
1430
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */
1431
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */
1432
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */
1433
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
1434
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */
1435
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */
1436
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */
1437
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */
1438
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */
1439
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */
1440
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
1441
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */
1442
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */
1443
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */
1444
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */
1445
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */
1446
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */
1447
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
1448
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */
1449
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */
1450
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */
1451
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */
1452
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */
1453
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */
1454
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */
1455
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
1456
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */
1457
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */
1458
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */
1459
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */
1460
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */
1461
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */
1462
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */
1463
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
1464
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */
1465
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */
1466
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */
1467
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */
1468
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */
1469
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */
1470
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */
1471
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
1472
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */
1473
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */
1474
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */
1475
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */
1476
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */
1477
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */
1478
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */
1479
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
1480
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */
1481
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */
1482
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */
1483
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */
1484
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */
1485
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */
1486
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */
1487
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */
1488
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */
1489
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */
1490
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */
1491
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */
1492
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */
1493
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */
1494
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */
1495
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */
1496
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */
1497
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */
1498
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */
1499
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */
1500
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
1501
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */
1502
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
1503
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
1504
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */
1505
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */
1506
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */
1507
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */
1508
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
1509
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */
1510
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
1511
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
1512
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */
1513
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */
1514
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */
1515
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */
1516
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */
1517
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */
1518
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */
1519
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
1520
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */
1521
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */
1522
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */
1523
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */
1524
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */
1525
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */
1526
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */
1527
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
1528
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */
1529
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */
1530
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */
1531
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */
1532
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */
1533
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */
1534
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */
1535
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
1536
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */
1537
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */
1538
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */
1539
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */
1540
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */
1541
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */
1542
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */
1543
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
1544
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */
1545
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */
1546
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */
1547
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */
1548
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */
1549
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */
1550
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */
1551
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
1552
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */
1553
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */
1554
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */
1555
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */
1556
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */
1557
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */
1558
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */
1559
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
1560
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */
1561
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */
1562
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */
1563
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */
1564
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */
1565
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */
1566
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */
1567
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
1568
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */
1569
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */
1570
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */
1571
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */
1572
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */
1573
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */
1574
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */
1575
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
1576
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */
1577
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */
1578
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */
1579
+
IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */
1580
+
IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */
1581
+
IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */
1582
+
IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */
1583
+
IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */
1584
+
IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */
1585
+
IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
1586
+
IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
1587
+
IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
1588
+
IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
1589
+
IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
1590
+
IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
1591
+
IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
1592
+
IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
1593
+
IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
1594
+
IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
1595
+
IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */
1596
+
IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */
1597
+
IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */
1598
+
IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */
1599
+
IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */
1600
+
IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */
1601
+
IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */
1602
+
IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */
1603
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
1604
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
1605
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */
1606
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */
1607
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */
1608
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */
1609
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */
1610
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */
1611
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
1612
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
1613
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */
1614
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */
1615
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */
1616
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */
1617
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */
1618
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */
1619
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
1620
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
1621
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */
1622
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */
1623
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */
1624
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1625
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */
1626
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */
1627
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
1628
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */
1629
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */
1630
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */
1631
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */
1632
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
1633
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */
1634
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */
1635
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1636
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */
1637
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */
1638
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */
1639
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */
1640
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */
1641
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */
1642
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */
1643
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1644
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */
1645
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */
1646
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */
1647
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */
1648
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */
1649
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */
1650
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */
1651
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1652
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
1653
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */
1654
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */
1655
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */
1656
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */
1657
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */
1658
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */
1659
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1660
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
1661
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */
1662
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */
1663
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */
1664
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */
1665
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */
1666
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */
1667
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1668
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */
1669
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */
1670
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */
1671
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */
1672
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */
1673
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */
1674
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
1675
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
1676
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */
1677
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */
1678
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */
1679
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */
1680
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */
1681
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */
1682
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */
1683
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */
1684
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */
1685
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */
1686
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */
1687
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */
1688
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */
1689
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */
1690
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
1691
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */
1692
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */
1693
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */
1694
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */
1695
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */
1696
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */
1697
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */
1698
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
1699
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */
1700
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */
1701
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */
1702
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */
1703
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */
1704
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */
1705
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */
1706
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
1707
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */
1708
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */
1709
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */
1710
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */
1711
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */
1712
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */
1713
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */
1714
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
1715
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */
1716
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */
1717
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */
1718
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */
1719
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */
1720
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */
1721
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */
1722
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
1723
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */
1724
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */
1725
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1726
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */
1727
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
1728
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */
1729
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */
1730
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */
1731
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
1732
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */
1733
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
1734
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */
1735
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */
1736
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */
1737
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */
1738
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
1739
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */
1740
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
1741
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */
1742
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */
1743
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */
1744
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */
1745
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */
1746
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */
1747
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */
1748
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1749
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
1750
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */
1751
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */
1752
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */
1753
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */
1754
+
IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1755
+
IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
1756
+
IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */
1757
+
IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */
1758
+
IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */
1759
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
1760
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
1761
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */
1762
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */
1763
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */
1764
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1765
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */
1766
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */
1767
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
1768
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
1769
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */
1770
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */
1771
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */
1772
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1773
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */
1774
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */
1775
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
1776
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
1777
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */
1778
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */
1779
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */
1780
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1781
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */
1782
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */
1783
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
1784
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
1785
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */
1786
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */
1787
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */
1788
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
1789
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */
1790
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */
1791
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
1792
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
1793
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */
1794
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */
1795
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */
1796
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */
1797
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */
1798
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */
1799
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
1800
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
1801
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */
1802
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */
1803
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */
1804
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */
1805
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */
1806
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */
1807
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
1808
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
1809
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */
1810
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */
1811
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */
1812
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1813
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */
1814
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */
1815
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
1816
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
1817
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */
1818
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */
1819
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */
1820
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
1821
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */
1822
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */
1823
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */
1824
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1825
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
1826
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */
1827
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */
1828
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */
1829
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */
1830
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */
1831
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */
1832
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1833
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
1834
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */
1835
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */
1836
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */
1837
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */
1838
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */
1839
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */
1840
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1841
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
1842
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */
1843
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */
1844
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */
1845
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */
1846
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */
1847
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */
1848
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1849
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */
1850
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */
1851
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */
1852
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */
1853
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */
1854
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */
1855
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1856
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
1857
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */
1858
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */
1859
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */
1860
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */
1861
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */
1862
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */
1863
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1864
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
1865
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */
1866
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */
1867
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */
1868
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */
1869
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */
1870
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */
1871
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1872
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
1873
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */
1874
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */
1875
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */
1876
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */
1877
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */
1878
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */
1879
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
1880
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
1881
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */
1882
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */
1883
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */
1884
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */
1885
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */
1886
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
1887
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */
1888
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
1889
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */
1890
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */
1891
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */
1892
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */
1893
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */
1894
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
1895
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */
1896
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */
1897
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */
1898
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */
1899
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */
1900
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */
1901
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */
1902
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
1903
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */
1904
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */
1905
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
1906
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */
1907
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */
1908
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */
1909
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */
1910
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
1911
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */
1912
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
1913
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */
1914
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */
1915
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */
1916
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
1917
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */
1918
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */
1919
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
1920
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */
1921
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */
1922
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */
1923
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */
1924
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
1925
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */
1926
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */
1927
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */
1928
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */
1929
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */
1930
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */
1931
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
1932
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */
1933
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */
1934
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
1935
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */
1936
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */
1937
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */
1938
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */
1939
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
1940
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */
1941
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */
1942
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
1943
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */
1944
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */
1945
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
1946
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */
1947
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */
1948
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
1949
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */
1950
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
1951
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
1952
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
1953
+
};
1954
+
1955
+
/* Pad names for the pinmux subsystem */
1956
+
static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
1957
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
1958
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
1959
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
1960
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
1961
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
1962
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
1963
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
1964
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
1965
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
1966
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
1967
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
1968
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
1969
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
1970
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
1971
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
1972
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
1973
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
1974
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
1975
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
1976
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
1977
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
1978
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
1979
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
1980
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
1981
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
1982
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
1983
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
1984
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
1985
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
1986
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
1987
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
1988
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
1989
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
1990
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
1991
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
1992
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
1993
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
1994
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
1995
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
1996
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
1997
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
1998
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
1999
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
2000
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
2001
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
2002
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
2003
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
2004
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
2005
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
2006
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
2007
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
2008
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
2009
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
2010
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
2011
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
2012
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
2013
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
2014
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
2015
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
2016
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
2017
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
2018
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
2019
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
2020
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
2021
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
2022
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
2023
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
2024
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
2025
+
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
2026
+
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
2027
+
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
2028
+
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
2029
+
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
2030
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
2031
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
2032
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
2033
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
2034
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
2035
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
2036
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
2037
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
2038
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
2039
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
2040
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
2041
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
2042
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
2043
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
2044
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
2045
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
2046
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
2047
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
2048
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
2049
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
2050
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
2051
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
2052
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
2053
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
2054
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
2055
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
2056
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
2057
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
2058
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
2059
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
2060
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
2061
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
2062
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
2063
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
2064
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40),
2065
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41),
2066
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42),
2067
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43),
2068
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44),
2069
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45),
2070
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46),
2071
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47),
2072
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5),
2073
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5),
2074
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32),
2075
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33),
2076
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34),
2077
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35),
2078
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36),
2079
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37),
2080
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38),
2081
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39),
2082
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4),
2083
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4),
2084
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24),
2085
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25),
2086
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26),
2087
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27),
2088
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28),
2089
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29),
2090
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3),
2091
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30),
2092
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31),
2093
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3),
2094
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16),
2095
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17),
2096
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18),
2097
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19),
2098
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20),
2099
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21),
2100
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22),
2101
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2),
2102
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23),
2103
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2),
2104
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0),
2105
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1),
2106
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2),
2107
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3),
2108
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4),
2109
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5),
2110
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6),
2111
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7),
2112
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8),
2113
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9),
2114
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10),
2115
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11),
2116
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12),
2117
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13),
2118
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14),
2119
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15),
2120
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS),
2121
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0),
2122
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1),
2123
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS),
2124
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET),
2125
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0),
2126
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1),
2127
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0),
2128
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2),
2129
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0),
2130
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1),
2131
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1),
2132
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0),
2133
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1),
2134
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE),
2135
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0),
2136
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1),
2137
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2),
2138
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3),
2139
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4),
2140
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5),
2141
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0),
2142
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6),
2143
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7),
2144
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0),
2145
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8),
2146
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9),
2147
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10),
2148
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11),
2149
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12),
2150
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13),
2151
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14),
2152
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1),
2153
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15),
2154
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1),
2155
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48),
2156
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49),
2157
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50),
2158
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51),
2159
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52),
2160
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53),
2161
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54),
2162
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55),
2163
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6),
2164
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6),
2165
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56),
2166
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7),
2167
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57),
2168
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58),
2169
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59),
2170
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60),
2171
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7),
2172
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61),
2173
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62),
2174
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63),
2175
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
2176
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
2177
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
2178
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
2179
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
2180
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
2181
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
2182
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
2183
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
2184
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
2185
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
2186
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
2187
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
2188
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
2189
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
2190
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
2191
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
2192
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
2193
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
2194
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
2195
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
2196
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
2197
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
2198
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
2199
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
2200
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
2201
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
2202
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
2203
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
2204
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
2205
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
2206
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
2207
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
2208
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
2209
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
2210
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
2211
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
2212
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
2213
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
2214
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
2215
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
2216
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
2217
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
2218
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
2219
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS),
2220
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD),
2221
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB),
2222
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI),
2223
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK),
2224
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO),
2225
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P),
2226
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P),
2227
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P),
2228
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P),
2229
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P),
2230
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P),
2231
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P),
2232
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P),
2233
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P),
2234
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P),
2235
+
IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER),
2236
+
IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ),
2237
+
IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ),
2238
+
IMX_PINCTRL_PIN(MX6Q_PAD_POR_B),
2239
+
IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1),
2240
+
IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B),
2241
+
IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0),
2242
+
IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE),
2243
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
2244
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
2245
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
2246
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
2247
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
2248
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
2249
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
2250
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
2251
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
2252
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
2253
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
2254
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
2255
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
2256
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
2257
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
2258
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
2259
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
2260
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
2261
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
2262
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
2263
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
2264
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
2265
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
2266
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
2267
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
2268
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
2269
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
2270
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
2271
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
2272
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
2273
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
2274
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
2275
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
2276
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
2277
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
2278
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
2279
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
2280
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
2281
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
2282
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
2283
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
2284
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
2285
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
2286
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
2287
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
2288
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
2289
+
};
2290
+
2291
+
static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
2292
+
.pins = imx6q_pinctrl_pads,
2293
+
.npins = ARRAY_SIZE(imx6q_pinctrl_pads),
2294
+
.pin_regs = imx6q_pin_regs,
2295
+
.npin_regs = ARRAY_SIZE(imx6q_pin_regs),
2296
+
};
2297
+
2298
+
static struct of_device_id imx6q_pinctrl_of_match[] __devinitdata = {
2299
+
{ .compatible = "fsl,imx6q-iomuxc", },
2300
+
{ /* sentinel */ }
2301
+
};
2302
+
2303
+
static int __devinit imx6q_pinctrl_probe(struct platform_device *pdev)
2304
+
{
2305
+
return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
2306
+
}
2307
+
2308
+
static struct platform_driver imx6q_pinctrl_driver = {
2309
+
.driver = {
2310
+
.name = "imx6q-pinctrl",
2311
+
.owner = THIS_MODULE,
2312
+
.of_match_table = of_match_ptr(imx6q_pinctrl_of_match),
2313
+
},
2314
+
.probe = imx6q_pinctrl_probe,
2315
+
.remove = __devexit_p(imx_pinctrl_remove),
2316
+
};
2317
+
2318
+
static int __init imx6q_pinctrl_init(void)
2319
+
{
2320
+
return platform_driver_register(&imx6q_pinctrl_driver);
2321
+
}
2322
+
arch_initcall(imx6q_pinctrl_init);
2323
+
2324
+
static void __exit imx6q_pinctrl_exit(void)
2325
+
{
2326
+
platform_driver_unregister(&imx6q_pinctrl_driver);
2327
+
}
2328
+
module_exit(imx6q_pinctrl_exit);
2329
+
MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
2330
+
MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
2331
+
MODULE_LICENSE("GPL v2");
+508
drivers/pinctrl/pinctrl-mxs.c
+508
drivers/pinctrl/pinctrl-mxs.c
···
1
+
/*
2
+
* Copyright 2012 Freescale Semiconductor, Inc.
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
#include <linux/err.h>
13
+
#include <linux/init.h>
14
+
#include <linux/io.h>
15
+
#include <linux/module.h>
16
+
#include <linux/of.h>
17
+
#include <linux/of_address.h>
18
+
#include <linux/pinctrl/machine.h>
19
+
#include <linux/pinctrl/pinconf.h>
20
+
#include <linux/pinctrl/pinctrl.h>
21
+
#include <linux/pinctrl/pinmux.h>
22
+
#include <linux/platform_device.h>
23
+
#include <linux/slab.h>
24
+
#include "core.h"
25
+
#include "pinctrl-mxs.h"
26
+
27
+
#define SUFFIX_LEN 4
28
+
29
+
struct mxs_pinctrl_data {
30
+
struct device *dev;
31
+
struct pinctrl_dev *pctl;
32
+
void __iomem *base;
33
+
struct mxs_pinctrl_soc_data *soc;
34
+
};
35
+
36
+
static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
37
+
{
38
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
39
+
40
+
return d->soc->ngroups;
41
+
}
42
+
43
+
static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
44
+
unsigned group)
45
+
{
46
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
47
+
48
+
return d->soc->groups[group].name;
49
+
}
50
+
51
+
static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
52
+
const unsigned **pins, unsigned *num_pins)
53
+
{
54
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
55
+
56
+
*pins = d->soc->groups[group].pins;
57
+
*num_pins = d->soc->groups[group].npins;
58
+
59
+
return 0;
60
+
}
61
+
62
+
static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
63
+
unsigned offset)
64
+
{
65
+
seq_printf(s, " %s", dev_name(pctldev->dev));
66
+
}
67
+
68
+
static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
69
+
struct device_node *np,
70
+
struct pinctrl_map **map, unsigned *num_maps)
71
+
{
72
+
struct pinctrl_map *new_map;
73
+
char *group;
74
+
unsigned new_num;
75
+
unsigned long config = 0;
76
+
unsigned long *pconfig;
77
+
int length = strlen(np->name) + SUFFIX_LEN;
78
+
u32 val;
79
+
int ret;
80
+
81
+
ret = of_property_read_u32(np, "fsl,drive-strength", &val);
82
+
if (!ret)
83
+
config = val | MA_PRESENT;
84
+
ret = of_property_read_u32(np, "fsl,voltage", &val);
85
+
if (!ret)
86
+
config |= val << VOL_SHIFT | VOL_PRESENT;
87
+
ret = of_property_read_u32(np, "fsl,pull-up", &val);
88
+
if (!ret)
89
+
config |= val << PULL_SHIFT | PULL_PRESENT;
90
+
91
+
new_num = config ? 2 : 1;
92
+
new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
93
+
if (!new_map)
94
+
return -ENOMEM;
95
+
96
+
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
97
+
new_map[0].data.mux.function = np->name;
98
+
99
+
/* Compose group name */
100
+
group = kzalloc(length, GFP_KERNEL);
101
+
if (!group)
102
+
return -ENOMEM;
103
+
of_property_read_u32(np, "reg", &val);
104
+
snprintf(group, length, "%s.%d", np->name, val);
105
+
new_map[0].data.mux.group = group;
106
+
107
+
if (config) {
108
+
pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
109
+
if (!pconfig) {
110
+
ret = -ENOMEM;
111
+
goto free;
112
+
}
113
+
114
+
new_map[1].type = PIN_MAP_TYPE_CONFIGS_GROUP;
115
+
new_map[1].data.configs.group_or_pin = group;
116
+
new_map[1].data.configs.configs = pconfig;
117
+
new_map[1].data.configs.num_configs = 1;
118
+
}
119
+
120
+
*map = new_map;
121
+
*num_maps = new_num;
122
+
123
+
return 0;
124
+
125
+
free:
126
+
kfree(new_map);
127
+
return ret;
128
+
}
129
+
130
+
static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
131
+
struct pinctrl_map *map, unsigned num_maps)
132
+
{
133
+
int i;
134
+
135
+
for (i = 0; i < num_maps; i++) {
136
+
if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
137
+
kfree(map[i].data.mux.group);
138
+
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
139
+
kfree(map[i].data.configs.configs);
140
+
}
141
+
142
+
kfree(map);
143
+
}
144
+
145
+
static struct pinctrl_ops mxs_pinctrl_ops = {
146
+
.get_groups_count = mxs_get_groups_count,
147
+
.get_group_name = mxs_get_group_name,
148
+
.get_group_pins = mxs_get_group_pins,
149
+
.pin_dbg_show = mxs_pin_dbg_show,
150
+
.dt_node_to_map = mxs_dt_node_to_map,
151
+
.dt_free_map = mxs_dt_free_map,
152
+
};
153
+
154
+
static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
155
+
{
156
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
157
+
158
+
return d->soc->nfunctions;
159
+
}
160
+
161
+
static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
162
+
unsigned function)
163
+
{
164
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
165
+
166
+
return d->soc->functions[function].name;
167
+
}
168
+
169
+
static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
170
+
unsigned group,
171
+
const char * const **groups,
172
+
unsigned * const num_groups)
173
+
{
174
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
175
+
176
+
*groups = d->soc->functions[group].groups;
177
+
*num_groups = d->soc->functions[group].ngroups;
178
+
179
+
return 0;
180
+
}
181
+
182
+
static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
183
+
unsigned group)
184
+
{
185
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
186
+
struct mxs_group *g = &d->soc->groups[group];
187
+
void __iomem *reg;
188
+
u8 bank, shift;
189
+
u16 pin;
190
+
int i;
191
+
192
+
for (i = 0; i < g->npins; i++) {
193
+
bank = PINID_TO_BANK(g->pins[i]);
194
+
pin = PINID_TO_PIN(g->pins[i]);
195
+
reg = d->base + d->soc->regs->muxsel;
196
+
reg += bank * 0x20 + pin / 16 * 0x10;
197
+
shift = pin % 16 * 2;
198
+
199
+
writel(0x3 << shift, reg + CLR);
200
+
writel(g->muxsel[i] << shift, reg + SET);
201
+
}
202
+
203
+
return 0;
204
+
}
205
+
206
+
static void mxs_pinctrl_disable(struct pinctrl_dev *pctldev,
207
+
unsigned function, unsigned group)
208
+
{
209
+
/* Nothing to do here */
210
+
}
211
+
212
+
static struct pinmux_ops mxs_pinmux_ops = {
213
+
.get_functions_count = mxs_pinctrl_get_funcs_count,
214
+
.get_function_name = mxs_pinctrl_get_func_name,
215
+
.get_function_groups = mxs_pinctrl_get_func_groups,
216
+
.enable = mxs_pinctrl_enable,
217
+
.disable = mxs_pinctrl_disable,
218
+
};
219
+
220
+
static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
221
+
unsigned pin, unsigned long *config)
222
+
{
223
+
return -ENOTSUPP;
224
+
}
225
+
226
+
static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
227
+
unsigned pin, unsigned long config)
228
+
{
229
+
return -ENOTSUPP;
230
+
}
231
+
232
+
static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
233
+
unsigned group, unsigned long *config)
234
+
{
235
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
236
+
237
+
*config = d->soc->groups[group].config;
238
+
239
+
return 0;
240
+
}
241
+
242
+
static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
243
+
unsigned group, unsigned long config)
244
+
{
245
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
246
+
struct mxs_group *g = &d->soc->groups[group];
247
+
void __iomem *reg;
248
+
u8 ma, vol, pull, bank, shift;
249
+
u16 pin;
250
+
int i;
251
+
252
+
ma = CONFIG_TO_MA(config);
253
+
vol = CONFIG_TO_VOL(config);
254
+
pull = CONFIG_TO_PULL(config);
255
+
256
+
for (i = 0; i < g->npins; i++) {
257
+
bank = PINID_TO_BANK(g->pins[i]);
258
+
pin = PINID_TO_PIN(g->pins[i]);
259
+
260
+
/* drive */
261
+
reg = d->base + d->soc->regs->drive;
262
+
reg += bank * 0x40 + pin / 8 * 0x10;
263
+
264
+
/* mA */
265
+
if (config & MA_PRESENT) {
266
+
shift = pin % 8 * 4;
267
+
writel(0x3 << shift, reg + CLR);
268
+
writel(ma << shift, reg + SET);
269
+
}
270
+
271
+
/* vol */
272
+
if (config & VOL_PRESENT) {
273
+
shift = pin % 8 * 4 + 2;
274
+
if (vol)
275
+
writel(1 << shift, reg + SET);
276
+
else
277
+
writel(1 << shift, reg + CLR);
278
+
}
279
+
280
+
/* pull */
281
+
if (config & PULL_PRESENT) {
282
+
reg = d->base + d->soc->regs->pull;
283
+
reg += bank * 0x10;
284
+
shift = pin;
285
+
if (pull)
286
+
writel(1 << shift, reg + SET);
287
+
else
288
+
writel(1 << shift, reg + CLR);
289
+
}
290
+
}
291
+
292
+
/* cache the config value for mxs_pinconf_group_get() */
293
+
g->config = config;
294
+
295
+
return 0;
296
+
}
297
+
298
+
static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
299
+
struct seq_file *s, unsigned pin)
300
+
{
301
+
/* Not support */
302
+
}
303
+
304
+
static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
305
+
struct seq_file *s, unsigned group)
306
+
{
307
+
unsigned long config;
308
+
309
+
if (!mxs_pinconf_group_get(pctldev, group, &config))
310
+
seq_printf(s, "0x%lx", config);
311
+
}
312
+
313
+
struct pinconf_ops mxs_pinconf_ops = {
314
+
.pin_config_get = mxs_pinconf_get,
315
+
.pin_config_set = mxs_pinconf_set,
316
+
.pin_config_group_get = mxs_pinconf_group_get,
317
+
.pin_config_group_set = mxs_pinconf_group_set,
318
+
.pin_config_dbg_show = mxs_pinconf_dbg_show,
319
+
.pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
320
+
};
321
+
322
+
static struct pinctrl_desc mxs_pinctrl_desc = {
323
+
.pctlops = &mxs_pinctrl_ops,
324
+
.pmxops = &mxs_pinmux_ops,
325
+
.confops = &mxs_pinconf_ops,
326
+
.owner = THIS_MODULE,
327
+
};
328
+
329
+
static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev,
330
+
struct device_node *np, int idx,
331
+
const char **out_name)
332
+
{
333
+
struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
334
+
struct mxs_group *g = &d->soc->groups[idx];
335
+
struct property *prop;
336
+
const char *propname = "fsl,pinmux-ids";
337
+
char *group;
338
+
int length = strlen(np->name) + SUFFIX_LEN;
339
+
int i;
340
+
u32 val;
341
+
342
+
group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
343
+
if (!group)
344
+
return -ENOMEM;
345
+
of_property_read_u32(np, "reg", &val);
346
+
snprintf(group, length, "%s.%d", np->name, val);
347
+
g->name = group;
348
+
349
+
prop = of_find_property(np, propname, &length);
350
+
if (!prop)
351
+
return -EINVAL;
352
+
g->npins = length / sizeof(u32);
353
+
354
+
g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
355
+
GFP_KERNEL);
356
+
if (!g->pins)
357
+
return -ENOMEM;
358
+
359
+
g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
360
+
GFP_KERNEL);
361
+
if (!g->muxsel)
362
+
return -ENOMEM;
363
+
364
+
of_property_read_u32_array(np, propname, g->pins, g->npins);
365
+
for (i = 0; i < g->npins; i++) {
366
+
g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
367
+
g->pins[i] = MUXID_TO_PINID(g->pins[i]);
368
+
}
369
+
370
+
*out_name = g->name;
371
+
372
+
return 0;
373
+
}
374
+
375
+
static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev,
376
+
struct mxs_pinctrl_data *d)
377
+
{
378
+
struct mxs_pinctrl_soc_data *soc = d->soc;
379
+
struct device_node *np = pdev->dev.of_node;
380
+
struct device_node *child;
381
+
struct mxs_function *f;
382
+
const char *fn, *fnull = "";
383
+
int i = 0, idxf = 0, idxg = 0;
384
+
int ret;
385
+
u32 val;
386
+
387
+
child = of_get_next_child(np, NULL);
388
+
if (!child) {
389
+
dev_err(&pdev->dev, "no group is defined\n");
390
+
return -ENOENT;
391
+
}
392
+
393
+
/* Count total functions and groups */
394
+
fn = fnull;
395
+
for_each_child_of_node(np, child) {
396
+
/* Skip pure pinconf node */
397
+
if (of_property_read_u32(child, "reg", &val))
398
+
continue;
399
+
if (strcmp(fn, child->name)) {
400
+
fn = child->name;
401
+
soc->nfunctions++;
402
+
}
403
+
soc->ngroups++;
404
+
}
405
+
406
+
soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
407
+
sizeof(*soc->functions), GFP_KERNEL);
408
+
if (!soc->functions)
409
+
return -ENOMEM;
410
+
411
+
soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
412
+
sizeof(*soc->groups), GFP_KERNEL);
413
+
if (!soc->groups)
414
+
return -ENOMEM;
415
+
416
+
/* Count groups for each function */
417
+
fn = fnull;
418
+
f = &soc->functions[idxf];
419
+
for_each_child_of_node(np, child) {
420
+
if (of_property_read_u32(child, "reg", &val))
421
+
continue;
422
+
if (strcmp(fn, child->name)) {
423
+
f = &soc->functions[idxf++];
424
+
f->name = fn = child->name;
425
+
}
426
+
f->ngroups++;
427
+
};
428
+
429
+
/* Get groups for each function */
430
+
idxf = 0;
431
+
fn = fnull;
432
+
for_each_child_of_node(np, child) {
433
+
if (of_property_read_u32(child, "reg", &val))
434
+
continue;
435
+
if (strcmp(fn, child->name)) {
436
+
f = &soc->functions[idxf++];
437
+
f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
438
+
sizeof(*f->groups),
439
+
GFP_KERNEL);
440
+
if (!f->groups)
441
+
return -ENOMEM;
442
+
fn = child->name;
443
+
i = 0;
444
+
}
445
+
ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
446
+
&f->groups[i++]);
447
+
if (ret)
448
+
return ret;
449
+
}
450
+
451
+
return 0;
452
+
}
453
+
454
+
int __devinit mxs_pinctrl_probe(struct platform_device *pdev,
455
+
struct mxs_pinctrl_soc_data *soc)
456
+
{
457
+
struct device_node *np = pdev->dev.of_node;
458
+
struct mxs_pinctrl_data *d;
459
+
int ret;
460
+
461
+
d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
462
+
if (!d)
463
+
return -ENOMEM;
464
+
465
+
d->dev = &pdev->dev;
466
+
d->soc = soc;
467
+
468
+
d->base = of_iomap(np, 0);
469
+
if (!d->base)
470
+
return -EADDRNOTAVAIL;
471
+
472
+
mxs_pinctrl_desc.pins = d->soc->pins;
473
+
mxs_pinctrl_desc.npins = d->soc->npins;
474
+
mxs_pinctrl_desc.name = dev_name(&pdev->dev);
475
+
476
+
platform_set_drvdata(pdev, d);
477
+
478
+
ret = mxs_pinctrl_probe_dt(pdev, d);
479
+
if (ret) {
480
+
dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
481
+
goto err;
482
+
}
483
+
484
+
d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
485
+
if (!d->pctl) {
486
+
dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
487
+
ret = -EINVAL;
488
+
goto err;
489
+
}
490
+
491
+
return 0;
492
+
493
+
err:
494
+
iounmap(d->base);
495
+
return ret;
496
+
}
497
+
EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
498
+
499
+
int __devexit mxs_pinctrl_remove(struct platform_device *pdev)
500
+
{
501
+
struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
502
+
503
+
pinctrl_unregister(d->pctl);
504
+
iounmap(d->base);
505
+
506
+
return 0;
507
+
}
508
+
EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
+91
drivers/pinctrl/pinctrl-mxs.h
+91
drivers/pinctrl/pinctrl-mxs.h
···
1
+
/*
2
+
* Copyright 2012 Freescale Semiconductor, Inc.
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
#ifndef __PINCTRL_MXS_H
13
+
#define __PINCTRL_MXS_H
14
+
15
+
#include <linux/platform_device.h>
16
+
#include <linux/pinctrl/pinctrl.h>
17
+
18
+
#define SET 0x4
19
+
#define CLR 0x8
20
+
#define TOG 0xc
21
+
22
+
#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
23
+
#define PINID(bank, pin) ((bank) * 32 + (pin))
24
+
25
+
/*
26
+
* pinmux-id bit field definitions
27
+
*
28
+
* bank: 15..12 (4)
29
+
* pin: 11..4 (8)
30
+
* muxsel: 3..0 (4)
31
+
*/
32
+
#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
33
+
#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
34
+
35
+
#define PINID_TO_BANK(p) ((p) >> 5)
36
+
#define PINID_TO_PIN(p) ((p) % 32)
37
+
38
+
/*
39
+
* pin config bit field definitions
40
+
*
41
+
* pull-up: 6..5 (2)
42
+
* voltage: 4..3 (2)
43
+
* mA: 2..0 (3)
44
+
*
45
+
* MSB of each field is presence bit for the config.
46
+
*/
47
+
#define PULL_PRESENT (1 << 6)
48
+
#define PULL_SHIFT 5
49
+
#define VOL_PRESENT (1 << 4)
50
+
#define VOL_SHIFT 3
51
+
#define MA_PRESENT (1 << 2)
52
+
#define MA_SHIFT 0
53
+
#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
54
+
#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
55
+
#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
56
+
57
+
struct mxs_function {
58
+
const char *name;
59
+
const char **groups;
60
+
unsigned ngroups;
61
+
};
62
+
63
+
struct mxs_group {
64
+
const char *name;
65
+
unsigned int *pins;
66
+
unsigned npins;
67
+
u8 *muxsel;
68
+
u8 config;
69
+
};
70
+
71
+
struct mxs_regs {
72
+
u16 muxsel;
73
+
u16 drive;
74
+
u16 pull;
75
+
};
76
+
77
+
struct mxs_pinctrl_soc_data {
78
+
const struct mxs_regs *regs;
79
+
const struct pinctrl_pin_desc *pins;
80
+
unsigned npins;
81
+
struct mxs_function *functions;
82
+
unsigned nfunctions;
83
+
struct mxs_group *groups;
84
+
unsigned ngroups;
85
+
};
86
+
87
+
int mxs_pinctrl_probe(struct platform_device *pdev,
88
+
struct mxs_pinctrl_soc_data *soc);
89
+
int mxs_pinctrl_remove(struct platform_device *pdev);
90
+
91
+
#endif /* __PINCTRL_MXS_H */
+10
-14
drivers/pinctrl/pinctrl-pxa3xx.c
+10
-14
drivers/pinctrl/pinctrl-pxa3xx.c
···
25
25
.pin_base = 0,
26
26
};
27
27
28
-
static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector)
28
+
static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev)
29
29
{
30
30
struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
31
-
if (selector >= info->num_grps)
32
-
return -EINVAL;
33
-
return 0;
31
+
32
+
return info->num_grps;
34
33
}
35
34
36
35
static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev,
37
36
unsigned selector)
38
37
{
39
38
struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
40
-
if (selector >= info->num_grps)
41
-
return NULL;
39
+
42
40
return info->grps[selector].name;
43
41
}
44
42
···
46
48
unsigned *num_pins)
47
49
{
48
50
struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
49
-
if (selector >= info->num_grps)
50
-
return -EINVAL;
51
+
51
52
*pins = info->grps[selector].pins;
52
53
*num_pins = info->grps[selector].npins;
53
54
return 0;
54
55
}
55
56
56
57
static struct pinctrl_ops pxa3xx_pctrl_ops = {
57
-
.list_groups = pxa3xx_list_groups,
58
+
.get_groups_count = pxa3xx_get_groups_count,
58
59
.get_group_name = pxa3xx_get_group_name,
59
60
.get_group_pins = pxa3xx_get_group_pins,
60
61
};
61
62
62
-
static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func)
63
+
static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev)
63
64
{
64
65
struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
65
-
if (func >= info->num_funcs)
66
-
return -EINVAL;
67
-
return 0;
66
+
67
+
return info->num_funcs;
68
68
}
69
69
70
70
static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev,
···
166
170
}
167
171
168
172
static struct pinmux_ops pxa3xx_pmx_ops = {
169
-
.list_functions = pxa3xx_pmx_list_func,
173
+
.get_functions_count = pxa3xx_pmx_get_funcs_count,
170
174
.get_function_name = pxa3xx_pmx_get_func_name,
171
175
.get_function_groups = pxa3xx_pmx_get_groups,
172
176
.enable = pxa3xx_pmx_enable,
+6
-14
drivers/pinctrl/pinctrl-sirf.c
+6
-14
drivers/pinctrl/pinctrl-sirf.c
···
853
853
SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
854
854
};
855
855
856
-
static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
856
+
static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
857
857
{
858
-
if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
859
-
return -EINVAL;
860
-
return 0;
858
+
return ARRAY_SIZE(sirfsoc_pin_groups);
861
859
}
862
860
863
861
static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
864
862
unsigned selector)
865
863
{
866
-
if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
867
-
return NULL;
868
864
return sirfsoc_pin_groups[selector].name;
869
865
}
870
866
···
868
872
const unsigned **pins,
869
873
unsigned *num_pins)
870
874
{
871
-
if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
872
-
return -EINVAL;
873
875
*pins = sirfsoc_pin_groups[selector].pins;
874
876
*num_pins = sirfsoc_pin_groups[selector].num_pins;
875
877
return 0;
···
880
886
}
881
887
882
888
static struct pinctrl_ops sirfsoc_pctrl_ops = {
883
-
.list_groups = sirfsoc_list_groups,
889
+
.get_groups_count = sirfsoc_get_groups_count,
884
890
.get_group_name = sirfsoc_get_group_name,
885
891
.get_group_pins = sirfsoc_get_group_pins,
886
892
.pin_dbg_show = sirfsoc_pin_dbg_show,
···
1027
1033
sirfsoc_pinmux_endisable(spmx, selector, false);
1028
1034
}
1029
1035
1030
-
static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector)
1036
+
static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1031
1037
{
1032
-
if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions))
1033
-
return -EINVAL;
1034
-
return 0;
1038
+
return ARRAY_SIZE(sirfsoc_pmx_functions);
1035
1039
}
1036
1040
1037
1041
static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
···
1066
1074
}
1067
1075
1068
1076
static struct pinmux_ops sirfsoc_pinmux_ops = {
1069
-
.list_functions = sirfsoc_pinmux_list_funcs,
1070
1077
.enable = sirfsoc_pinmux_enable,
1071
1078
.disable = sirfsoc_pinmux_disable,
1079
+
.get_functions_count = sirfsoc_pinmux_get_funcs_count,
1072
1080
.get_function_name = sirfsoc_pinmux_get_func_name,
1073
1081
.get_function_groups = sirfsoc_pinmux_get_groups,
1074
1082
.gpio_request_enable = sirfsoc_pinmux_request_gpio,
+211
-34
drivers/pinctrl/pinctrl-tegra.c
+211
-34
drivers/pinctrl/pinctrl-tegra.c
···
23
23
#include <linux/io.h>
24
24
#include <linux/module.h>
25
25
#include <linux/of_device.h>
26
+
#include <linux/pinctrl/machine.h>
26
27
#include <linux/pinctrl/pinctrl.h>
27
28
#include <linux/pinctrl/pinmux.h>
28
29
#include <linux/pinctrl/pinconf.h>
30
+
#include <linux/slab.h>
29
31
30
32
#include <mach/pinconf-tegra.h>
31
33
···
55
53
writel(val, pmx->regs[bank] + reg);
56
54
}
57
55
58
-
static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev,
59
-
unsigned group)
56
+
static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
60
57
{
61
58
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
62
59
63
-
if (group >= pmx->soc->ngroups)
64
-
return -EINVAL;
65
-
66
-
return 0;
60
+
return pmx->soc->ngroups;
67
61
}
68
62
69
63
static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
70
64
unsigned group)
71
65
{
72
66
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
73
-
74
-
if (group >= pmx->soc->ngroups)
75
-
return NULL;
76
67
77
68
return pmx->soc->groups[group].name;
78
69
}
···
76
81
unsigned *num_pins)
77
82
{
78
83
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
79
-
80
-
if (group >= pmx->soc->ngroups)
81
-
return -EINVAL;
82
84
83
85
*pins = pmx->soc->groups[group].pins;
84
86
*num_pins = pmx->soc->groups[group].npins;
···
90
98
seq_printf(s, " " DRIVER_NAME);
91
99
}
92
100
101
+
static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
102
+
unsigned *num_maps, unsigned reserve)
103
+
{
104
+
unsigned old_num = *reserved_maps;
105
+
unsigned new_num = *num_maps + reserve;
106
+
struct pinctrl_map *new_map;
107
+
108
+
if (old_num >= new_num)
109
+
return 0;
110
+
111
+
new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
112
+
if (!new_map)
113
+
return -ENOMEM;
114
+
115
+
memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
116
+
117
+
*map = new_map;
118
+
*reserved_maps = new_num;
119
+
120
+
return 0;
121
+
}
122
+
123
+
static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
124
+
unsigned *num_maps, const char *group,
125
+
const char *function)
126
+
{
127
+
if (*num_maps == *reserved_maps)
128
+
return -ENOSPC;
129
+
130
+
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
131
+
(*map)[*num_maps].data.mux.group = group;
132
+
(*map)[*num_maps].data.mux.function = function;
133
+
(*num_maps)++;
134
+
135
+
return 0;
136
+
}
137
+
138
+
static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps,
139
+
unsigned *num_maps, const char *group,
140
+
unsigned long *configs, unsigned num_configs)
141
+
{
142
+
unsigned long *dup_configs;
143
+
144
+
if (*num_maps == *reserved_maps)
145
+
return -ENOSPC;
146
+
147
+
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
148
+
GFP_KERNEL);
149
+
if (!dup_configs)
150
+
return -ENOMEM;
151
+
152
+
(*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
153
+
(*map)[*num_maps].data.configs.group_or_pin = group;
154
+
(*map)[*num_maps].data.configs.configs = dup_configs;
155
+
(*map)[*num_maps].data.configs.num_configs = num_configs;
156
+
(*num_maps)++;
157
+
158
+
return 0;
159
+
}
160
+
161
+
static int add_config(unsigned long **configs, unsigned *num_configs,
162
+
unsigned long config)
163
+
{
164
+
unsigned old_num = *num_configs;
165
+
unsigned new_num = old_num + 1;
166
+
unsigned long *new_configs;
167
+
168
+
new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
169
+
GFP_KERNEL);
170
+
if (!new_configs)
171
+
return -ENOMEM;
172
+
173
+
new_configs[old_num] = config;
174
+
175
+
*configs = new_configs;
176
+
*num_configs = new_num;
177
+
178
+
return 0;
179
+
}
180
+
181
+
void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
182
+
struct pinctrl_map *map, unsigned num_maps)
183
+
{
184
+
int i;
185
+
186
+
for (i = 0; i < num_maps; i++)
187
+
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
188
+
kfree(map[i].data.configs.configs);
189
+
190
+
kfree(map);
191
+
}
192
+
193
+
static const struct cfg_param {
194
+
const char *property;
195
+
enum tegra_pinconf_param param;
196
+
} cfg_params[] = {
197
+
{"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
198
+
{"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
199
+
{"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
200
+
{"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
201
+
{"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
202
+
{"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
203
+
{"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
204
+
{"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
205
+
{"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
206
+
{"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
207
+
{"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
208
+
{"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
209
+
{"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
210
+
};
211
+
212
+
int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
213
+
struct pinctrl_map **map,
214
+
unsigned *reserved_maps,
215
+
unsigned *num_maps)
216
+
{
217
+
int ret, i;
218
+
const char *function;
219
+
u32 val;
220
+
unsigned long config;
221
+
unsigned long *configs = NULL;
222
+
unsigned num_configs = 0;
223
+
unsigned reserve;
224
+
struct property *prop;
225
+
const char *group;
226
+
227
+
ret = of_property_read_string(np, "nvidia,function", &function);
228
+
if (ret < 0)
229
+
function = NULL;
230
+
231
+
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
232
+
ret = of_property_read_u32(np, cfg_params[i].property, &val);
233
+
if (!ret) {
234
+
config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
235
+
ret = add_config(&configs, &num_configs, config);
236
+
if (ret < 0)
237
+
goto exit;
238
+
}
239
+
}
240
+
241
+
reserve = 0;
242
+
if (function != NULL)
243
+
reserve++;
244
+
if (num_configs)
245
+
reserve++;
246
+
ret = of_property_count_strings(np, "nvidia,pins");
247
+
if (ret < 0)
248
+
goto exit;
249
+
reserve *= ret;
250
+
251
+
ret = reserve_map(map, reserved_maps, num_maps, reserve);
252
+
if (ret < 0)
253
+
goto exit;
254
+
255
+
of_property_for_each_string(np, "nvidia,pins", prop, group) {
256
+
if (function) {
257
+
ret = add_map_mux(map, reserved_maps, num_maps,
258
+
group, function);
259
+
if (ret < 0)
260
+
goto exit;
261
+
}
262
+
263
+
if (num_configs) {
264
+
ret = add_map_configs(map, reserved_maps, num_maps,
265
+
group, configs, num_configs);
266
+
if (ret < 0)
267
+
goto exit;
268
+
}
269
+
}
270
+
271
+
ret = 0;
272
+
273
+
exit:
274
+
kfree(configs);
275
+
return ret;
276
+
}
277
+
278
+
int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
279
+
struct device_node *np_config,
280
+
struct pinctrl_map **map, unsigned *num_maps)
281
+
{
282
+
unsigned reserved_maps;
283
+
struct device_node *np;
284
+
int ret;
285
+
286
+
reserved_maps = 0;
287
+
*map = NULL;
288
+
*num_maps = 0;
289
+
290
+
for_each_child_of_node(np_config, np) {
291
+
ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps,
292
+
num_maps);
293
+
if (ret < 0) {
294
+
tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
295
+
return ret;
296
+
}
297
+
}
298
+
299
+
return 0;
300
+
}
301
+
93
302
static struct pinctrl_ops tegra_pinctrl_ops = {
94
-
.list_groups = tegra_pinctrl_list_groups,
303
+
.get_groups_count = tegra_pinctrl_get_groups_count,
95
304
.get_group_name = tegra_pinctrl_get_group_name,
96
305
.get_group_pins = tegra_pinctrl_get_group_pins,
97
306
.pin_dbg_show = tegra_pinctrl_pin_dbg_show,
307
+
.dt_node_to_map = tegra_pinctrl_dt_node_to_map,
308
+
.dt_free_map = tegra_pinctrl_dt_free_map,
98
309
};
99
310
100
-
static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev,
101
-
unsigned function)
311
+
static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
102
312
{
103
313
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
104
314
105
-
if (function >= pmx->soc->nfunctions)
106
-
return -EINVAL;
107
-
108
-
return 0;
315
+
return pmx->soc->nfunctions;
109
316
}
110
317
111
318
static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
112
319
unsigned function)
113
320
{
114
321
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
115
-
116
-
if (function >= pmx->soc->nfunctions)
117
-
return NULL;
118
322
119
323
return pmx->soc->functions[function].name;
120
324
}
···
321
133
unsigned * const num_groups)
322
134
{
323
135
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
324
-
325
-
if (function >= pmx->soc->nfunctions)
326
-
return -EINVAL;
327
136
328
137
*groups = pmx->soc->functions[function].groups;
329
138
*num_groups = pmx->soc->functions[function].ngroups;
···
336
151
int i;
337
152
u32 val;
338
153
339
-
if (group >= pmx->soc->ngroups)
340
-
return -EINVAL;
341
154
g = &pmx->soc->groups[group];
342
155
343
156
if (g->mux_reg < 0)
···
363
180
const struct tegra_pingroup *g;
364
181
u32 val;
365
182
366
-
if (group >= pmx->soc->ngroups)
367
-
return;
368
183
g = &pmx->soc->groups[group];
369
184
370
185
if (g->mux_reg < 0)
···
375
194
}
376
195
377
196
static struct pinmux_ops tegra_pinmux_ops = {
378
-
.list_functions = tegra_pinctrl_list_funcs,
197
+
.get_functions_count = tegra_pinctrl_get_funcs_count,
379
198
.get_function_name = tegra_pinctrl_get_func_name,
380
199
.get_function_groups = tegra_pinctrl_get_func_groups,
381
200
.enable = tegra_pinctrl_enable,
···
505
324
s16 reg;
506
325
u32 val, mask;
507
326
508
-
if (group >= pmx->soc->ngroups)
509
-
return -EINVAL;
510
327
g = &pmx->soc->groups[group];
511
328
512
329
ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width);
···
532
353
s16 reg;
533
354
u32 val, mask;
534
355
535
-
if (group >= pmx->soc->ngroups)
536
-
return -EINVAL;
537
356
g = &pmx->soc->groups[group];
538
357
539
358
ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width);
+6
-14
drivers/pinctrl/pinctrl-u300.c
+6
-14
drivers/pinctrl/pinctrl-u300.c
···
836
836
},
837
837
};
838
838
839
-
static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
839
+
static int u300_get_groups_count(struct pinctrl_dev *pctldev)
840
840
{
841
-
if (selector >= ARRAY_SIZE(u300_pin_groups))
842
-
return -EINVAL;
843
-
return 0;
841
+
return ARRAY_SIZE(u300_pin_groups);
844
842
}
845
843
846
844
static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
847
845
unsigned selector)
848
846
{
849
-
if (selector >= ARRAY_SIZE(u300_pin_groups))
850
-
return NULL;
851
847
return u300_pin_groups[selector].name;
852
848
}
853
849
···
851
855
const unsigned **pins,
852
856
unsigned *num_pins)
853
857
{
854
-
if (selector >= ARRAY_SIZE(u300_pin_groups))
855
-
return -EINVAL;
856
858
*pins = u300_pin_groups[selector].pins;
857
859
*num_pins = u300_pin_groups[selector].num_pins;
858
860
return 0;
···
863
869
}
864
870
865
871
static struct pinctrl_ops u300_pctrl_ops = {
866
-
.list_groups = u300_list_groups,
872
+
.get_groups_count = u300_get_groups_count,
867
873
.get_group_name = u300_get_group_name,
868
874
.get_group_pins = u300_get_group_pins,
869
875
.pin_dbg_show = u300_pin_dbg_show,
···
985
991
u300_pmx_endisable(upmx, selector, false);
986
992
}
987
993
988
-
static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
994
+
static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
989
995
{
990
-
if (selector >= ARRAY_SIZE(u300_pmx_functions))
991
-
return -EINVAL;
992
-
return 0;
996
+
return ARRAY_SIZE(u300_pmx_functions);
993
997
}
994
998
995
999
static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
···
1006
1014
}
1007
1015
1008
1016
static struct pinmux_ops u300_pmx_ops = {
1009
-
.list_functions = u300_pmx_list_funcs,
1017
+
.get_functions_count = u300_pmx_get_funcs_count,
1010
1018
.get_function_name = u300_pmx_get_func_name,
1011
1019
.get_function_groups = u300_pmx_get_groups,
1012
1020
.enable = u300_pmx_enable,
+65
-28
drivers/pinctrl/pinmux.c
+65
-28
drivers/pinctrl/pinmux.c
···
33
33
int pinmux_check_ops(struct pinctrl_dev *pctldev)
34
34
{
35
35
const struct pinmux_ops *ops = pctldev->desc->pmxops;
36
+
unsigned nfuncs;
36
37
unsigned selector = 0;
37
38
38
39
/* Check that we implement required operations */
39
-
if (!ops->list_functions ||
40
+
if (!ops ||
41
+
!ops->get_functions_count ||
40
42
!ops->get_function_name ||
41
43
!ops->get_function_groups ||
42
44
!ops->enable ||
43
-
!ops->disable)
45
+
!ops->disable) {
46
+
dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
44
47
return -EINVAL;
45
-
48
+
}
46
49
/* Check that all functions registered have names */
47
-
while (ops->list_functions(pctldev, selector) >= 0) {
50
+
nfuncs = ops->get_functions_count(pctldev);
51
+
while (selector < nfuncs) {
48
52
const char *fname = ops->get_function_name(pctldev,
49
53
selector);
50
54
if (!fname) {
51
-
pr_err("pinmux ops has no name for function%u\n",
55
+
dev_err(pctldev->dev, "pinmux ops has no name for function%u\n",
52
56
selector);
53
57
return -EINVAL;
54
58
}
···
89
85
const struct pinmux_ops *ops = pctldev->desc->pmxops;
90
86
int status = -EINVAL;
91
87
92
-
dev_dbg(pctldev->dev, "request pin %d for %s\n", pin, owner);
93
-
94
88
desc = pin_desc_get(pctldev, pin);
95
89
if (desc == NULL) {
96
90
dev_err(pctldev->dev,
97
-
"pin is not registered so it cannot be requested\n");
91
+
"pin %d is not registered so it cannot be requested\n",
92
+
pin);
98
93
goto out;
99
94
}
95
+
96
+
dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n",
97
+
pin, desc->name, owner);
100
98
101
99
if (gpio_range) {
102
100
/* There's no need to support multiple GPIO requests */
103
101
if (desc->gpio_owner) {
104
102
dev_err(pctldev->dev,
105
-
"pin already requested\n");
103
+
"pin %s already requested by %s; cannot claim for %s\n",
104
+
desc->name, desc->gpio_owner, owner);
106
105
goto out;
107
106
}
108
107
···
113
106
} else {
114
107
if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) {
115
108
dev_err(pctldev->dev,
116
-
"pin already requested\n");
109
+
"pin %s already requested by %s; cannot claim for %s\n",
110
+
desc->name, desc->mux_owner, owner);
117
111
goto out;
118
112
}
119
113
···
147
139
status = 0;
148
140
149
141
if (status) {
150
-
dev_err(pctldev->dev, "->request on device %s failed for pin %d\n",
151
-
pctldev->desc->name, pin);
142
+
dev_err(pctldev->dev, "request() failed for pin %d\n", pin);
152
143
module_put(pctldev->owner);
153
144
}
154
145
···
164
157
out:
165
158
if (status)
166
159
dev_err(pctldev->dev, "pin-%d (%s) status %d\n",
167
-
pin, owner, status);
160
+
pin, owner, status);
168
161
169
162
return status;
170
163
}
···
294
287
const char *function)
295
288
{
296
289
const struct pinmux_ops *ops = pctldev->desc->pmxops;
290
+
unsigned nfuncs = ops->get_functions_count(pctldev);
297
291
unsigned selector = 0;
298
292
299
293
/* See if this pctldev has this function */
300
-
while (ops->list_functions(pctldev, selector) >= 0) {
294
+
while (selector < nfuncs) {
301
295
const char *fname = ops->get_function_name(pctldev,
302
296
selector);
303
297
···
327
319
const unsigned *pins;
328
320
unsigned num_pins;
329
321
330
-
setting->data.mux.func =
331
-
pinmux_func_name_to_selector(pctldev, map->data.mux.function);
332
-
if (setting->data.mux.func < 0)
333
-
return setting->data.mux.func;
322
+
if (!pmxops) {
323
+
dev_err(pctldev->dev, "does not support mux function\n");
324
+
return -EINVAL;
325
+
}
326
+
327
+
ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function);
328
+
if (ret < 0) {
329
+
dev_err(pctldev->dev, "invalid function %s in map table\n",
330
+
map->data.mux.function);
331
+
return ret;
332
+
}
333
+
setting->data.mux.func = ret;
334
334
335
335
ret = pmxops->get_function_groups(pctldev, setting->data.mux.func,
336
336
&groups, &num_groups);
337
-
if (ret < 0)
337
+
if (ret < 0) {
338
+
dev_err(pctldev->dev, "can't query groups for function %s\n",
339
+
map->data.mux.function);
338
340
return ret;
339
-
if (!num_groups)
341
+
}
342
+
if (!num_groups) {
343
+
dev_err(pctldev->dev,
344
+
"function %s can't be selected on any group\n",
345
+
map->data.mux.function);
340
346
return -EINVAL;
341
-
347
+
}
342
348
if (map->data.mux.group) {
343
349
bool found = false;
344
350
group = map->data.mux.group;
···
362
340
break;
363
341
}
364
342
}
365
-
if (!found)
343
+
if (!found) {
344
+
dev_err(pctldev->dev,
345
+
"invalid group \"%s\" for function \"%s\"\n",
346
+
group, map->data.mux.function);
366
347
return -EINVAL;
348
+
}
367
349
} else {
368
350
group = groups[0];
369
351
}
370
352
371
-
setting->data.mux.group = pinctrl_get_group_selector(pctldev, group);
372
-
if (setting->data.mux.group < 0)
373
-
return setting->data.mux.group;
353
+
ret = pinctrl_get_group_selector(pctldev, group);
354
+
if (ret < 0) {
355
+
dev_err(pctldev->dev, "invalid group %s in map table\n",
356
+
map->data.mux.group);
357
+
return ret;
358
+
}
359
+
setting->data.mux.group = ret;
374
360
375
361
ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins,
376
362
&num_pins);
···
394
364
ret = pin_request(pctldev, pins[i], map->dev_name, NULL);
395
365
if (ret) {
396
366
dev_err(pctldev->dev,
397
-
"could not get request pin %d on device %s\n",
367
+
"could not request pin %d on device %s\n",
398
368
pins[i], pinctrl_dev_get_name(pctldev));
399
369
/* On error release all taken pins */
400
370
i--; /* this pin just failed */
···
507
477
{
508
478
struct pinctrl_dev *pctldev = s->private;
509
479
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
480
+
unsigned nfuncs;
510
481
unsigned func_selector = 0;
511
482
512
-
mutex_lock(&pinctrl_mutex);
483
+
if (!pmxops)
484
+
return 0;
513
485
514
-
while (pmxops->list_functions(pctldev, func_selector) >= 0) {
486
+
mutex_lock(&pinctrl_mutex);
487
+
nfuncs = pmxops->get_functions_count(pctldev);
488
+
while (func_selector < nfuncs) {
515
489
const char *func = pmxops->get_function_name(pctldev,
516
490
func_selector);
517
491
const char * const *groups;
···
548
514
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
549
515
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
550
516
unsigned i, pin;
517
+
518
+
if (!pmxops)
519
+
return 0;
551
520
552
521
seq_puts(s, "Pinmux settings per pin\n");
553
522
seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n");
+12
-6
drivers/pinctrl/pinmux.h
+12
-6
drivers/pinctrl/pinmux.h
···
31
31
int pinmux_enable_setting(struct pinctrl_setting const *setting);
32
32
void pinmux_disable_setting(struct pinctrl_setting const *setting);
33
33
34
-
void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
35
-
void pinmux_show_setting(struct seq_file *s,
36
-
struct pinctrl_setting const *setting);
37
-
void pinmux_init_device_debugfs(struct dentry *devroot,
38
-
struct pinctrl_dev *pctldev);
39
-
40
34
#else
41
35
42
36
static inline int pinmux_check_ops(struct pinctrl_dev *pctldev)
···
82
88
struct pinctrl_setting const *setting)
83
89
{
84
90
}
91
+
92
+
#endif
93
+
94
+
#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS)
95
+
96
+
void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
97
+
void pinmux_show_setting(struct seq_file *s,
98
+
struct pinctrl_setting const *setting);
99
+
void pinmux_init_device_debugfs(struct dentry *devroot,
100
+
struct pinctrl_dev *pctldev);
101
+
102
+
#else
85
103
86
104
static inline void pinmux_show_map(struct seq_file *s,
87
105
struct pinctrl_map const *map)
+34
drivers/pinctrl/spear/Kconfig
+34
drivers/pinctrl/spear/Kconfig
···
1
+
#
2
+
# ST Microelectronics SPEAr PINCTRL drivers
3
+
#
4
+
5
+
if PLAT_SPEAR
6
+
7
+
config PINCTRL_SPEAR
8
+
bool
9
+
depends on OF
10
+
select PINMUX
11
+
help
12
+
This enables pin control drivers for SPEAr Platform
13
+
14
+
config PINCTRL_SPEAR3XX
15
+
bool
16
+
depends on ARCH_SPEAR3XX
17
+
select PINCTRL_SPEAR
18
+
19
+
config PINCTRL_SPEAR300
20
+
bool "ST Microelectronics SPEAr300 SoC pin controller driver"
21
+
depends on MACH_SPEAR300
22
+
select PINCTRL_SPEAR3XX
23
+
24
+
config PINCTRL_SPEAR310
25
+
bool "ST Microelectronics SPEAr310 SoC pin controller driver"
26
+
depends on MACH_SPEAR310
27
+
select PINCTRL_SPEAR3XX
28
+
29
+
config PINCTRL_SPEAR320
30
+
bool "ST Microelectronics SPEAr320 SoC pin controller driver"
31
+
depends on MACH_SPEAR320
32
+
select PINCTRL_SPEAR3XX
33
+
34
+
endif
+7
drivers/pinctrl/spear/Makefile
+7
drivers/pinctrl/spear/Makefile
···
1
+
# SPEAr pinmux support
2
+
3
+
obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o
4
+
obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
5
+
obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
6
+
obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o
7
+
obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o
+354
drivers/pinctrl/spear/pinctrl-spear.c
+354
drivers/pinctrl/spear/pinctrl-spear.c
···
1
+
/*
2
+
* Driver for the ST Microelectronics SPEAr pinmux
3
+
*
4
+
* Copyright (C) 2012 ST Microelectronics
5
+
* Viresh Kumar <viresh.kumar@st.com>
6
+
*
7
+
* Inspired from:
8
+
* - U300 Pinctl drivers
9
+
* - Tegra Pinctl drivers
10
+
*
11
+
* This file is licensed under the terms of the GNU General Public
12
+
* License version 2. This program is licensed "as is" without any
13
+
* warranty of any kind, whether express or implied.
14
+
*/
15
+
16
+
#include <linux/err.h>
17
+
#include <linux/io.h>
18
+
#include <linux/module.h>
19
+
#include <linux/of.h>
20
+
#include <linux/of_address.h>
21
+
#include <linux/pinctrl/machine.h>
22
+
#include <linux/pinctrl/pinctrl.h>
23
+
#include <linux/pinctrl/pinmux.h>
24
+
#include <linux/platform_device.h>
25
+
#include <linux/slab.h>
26
+
27
+
#include "pinctrl-spear.h"
28
+
29
+
#define DRIVER_NAME "spear-pinmux"
30
+
31
+
static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
32
+
{
33
+
return readl_relaxed(pmx->vbase + reg);
34
+
}
35
+
36
+
static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
37
+
{
38
+
writel_relaxed(val, pmx->vbase + reg);
39
+
}
40
+
41
+
static int set_mode(struct spear_pmx *pmx, int mode)
42
+
{
43
+
struct spear_pmx_mode *pmx_mode = NULL;
44
+
int i;
45
+
u32 val;
46
+
47
+
if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
48
+
return -EINVAL;
49
+
50
+
for (i = 0; i < pmx->machdata->npmx_modes; i++) {
51
+
if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
52
+
pmx_mode = pmx->machdata->pmx_modes[i];
53
+
break;
54
+
}
55
+
}
56
+
57
+
if (!pmx_mode)
58
+
return -EINVAL;
59
+
60
+
val = pmx_readl(pmx, pmx_mode->reg);
61
+
val &= ~pmx_mode->mask;
62
+
val |= pmx_mode->val;
63
+
pmx_writel(pmx, val, pmx_mode->reg);
64
+
65
+
pmx->machdata->mode = pmx_mode->mode;
66
+
dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
67
+
pmx_mode->name ? pmx_mode->name : "no_name",
68
+
pmx_mode->reg);
69
+
70
+
return 0;
71
+
}
72
+
73
+
void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
74
+
{
75
+
struct spear_pingroup *pgroup;
76
+
struct spear_modemux *modemux;
77
+
int i, j, group;
78
+
79
+
for (group = 0; group < machdata->ngroups; group++) {
80
+
pgroup = machdata->groups[group];
81
+
82
+
for (i = 0; i < pgroup->nmodemuxs; i++) {
83
+
modemux = &pgroup->modemuxs[i];
84
+
85
+
for (j = 0; j < modemux->nmuxregs; j++)
86
+
if (modemux->muxregs[j].reg == 0xFFFF)
87
+
modemux->muxregs[j].reg = reg;
88
+
}
89
+
}
90
+
}
91
+
92
+
static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
93
+
{
94
+
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
95
+
96
+
return pmx->machdata->ngroups;
97
+
}
98
+
99
+
static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
100
+
unsigned group)
101
+
{
102
+
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
103
+
104
+
return pmx->machdata->groups[group]->name;
105
+
}
106
+
107
+
static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
108
+
unsigned group, const unsigned **pins, unsigned *num_pins)
109
+
{
110
+
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
111
+
112
+
*pins = pmx->machdata->groups[group]->pins;
113
+
*num_pins = pmx->machdata->groups[group]->npins;
114
+
115
+
return 0;
116
+
}
117
+
118
+
static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
119
+
struct seq_file *s, unsigned offset)
120
+
{
121
+
seq_printf(s, " " DRIVER_NAME);
122
+
}
123
+
124
+
int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
125
+
struct device_node *np_config,
126
+
struct pinctrl_map **map, unsigned *num_maps)
127
+
{
128
+
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
129
+
struct device_node *np;
130
+
struct property *prop;
131
+
const char *function, *group;
132
+
int ret, index = 0, count = 0;
133
+
134
+
/* calculate number of maps required */
135
+
for_each_child_of_node(np_config, np) {
136
+
ret = of_property_read_string(np, "st,function", &function);
137
+
if (ret < 0)
138
+
return ret;
139
+
140
+
ret = of_property_count_strings(np, "st,pins");
141
+
if (ret < 0)
142
+
return ret;
143
+
144
+
count += ret;
145
+
}
146
+
147
+
if (!count) {
148
+
dev_err(pmx->dev, "No child nodes passed via DT\n");
149
+
return -ENODEV;
150
+
}
151
+
152
+
*map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
153
+
if (!*map)
154
+
return -ENOMEM;
155
+
156
+
for_each_child_of_node(np_config, np) {
157
+
of_property_read_string(np, "st,function", &function);
158
+
of_property_for_each_string(np, "st,pins", prop, group) {
159
+
(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
160
+
(*map)[index].data.mux.group = group;
161
+
(*map)[index].data.mux.function = function;
162
+
index++;
163
+
}
164
+
}
165
+
166
+
*num_maps = count;
167
+
168
+
return 0;
169
+
}
170
+
171
+
void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
172
+
struct pinctrl_map *map, unsigned num_maps)
173
+
{
174
+
kfree(map);
175
+
}
176
+
177
+
static struct pinctrl_ops spear_pinctrl_ops = {
178
+
.get_groups_count = spear_pinctrl_get_groups_cnt,
179
+
.get_group_name = spear_pinctrl_get_group_name,
180
+
.get_group_pins = spear_pinctrl_get_group_pins,
181
+
.pin_dbg_show = spear_pinctrl_pin_dbg_show,
182
+
.dt_node_to_map = spear_pinctrl_dt_node_to_map,
183
+
.dt_free_map = spear_pinctrl_dt_free_map,
184
+
};
185
+
186
+
static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
187
+
{
188
+
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
189
+
190
+
return pmx->machdata->nfunctions;
191
+
}
192
+
193
+
static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
194
+
unsigned function)
195
+
{
196
+
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
197
+
198
+
return pmx->machdata->functions[function]->name;
199
+
}
200
+
201
+
static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
202
+
unsigned function, const char *const **groups,
203
+
unsigned * const ngroups)
204
+
{
205
+
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
206
+
207
+
*groups = pmx->machdata->functions[function]->groups;
208
+
*ngroups = pmx->machdata->functions[function]->ngroups;
209
+
210
+
return 0;
211
+
}
212
+
213
+
static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
214
+
unsigned function, unsigned group, bool enable)
215
+
{
216
+
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
217
+
const struct spear_pingroup *pgroup;
218
+
const struct spear_modemux *modemux;
219
+
struct spear_muxreg *muxreg;
220
+
u32 val, temp;
221
+
int i, j;
222
+
bool found = false;
223
+
224
+
pgroup = pmx->machdata->groups[group];
225
+
226
+
for (i = 0; i < pgroup->nmodemuxs; i++) {
227
+
modemux = &pgroup->modemuxs[i];
228
+
229
+
/* SoC have any modes */
230
+
if (pmx->machdata->modes_supported) {
231
+
if (!(pmx->machdata->mode & modemux->modes))
232
+
continue;
233
+
}
234
+
235
+
found = true;
236
+
for (j = 0; j < modemux->nmuxregs; j++) {
237
+
muxreg = &modemux->muxregs[j];
238
+
239
+
val = pmx_readl(pmx, muxreg->reg);
240
+
val &= ~muxreg->mask;
241
+
242
+
if (enable)
243
+
temp = muxreg->val;
244
+
else
245
+
temp = ~muxreg->val;
246
+
247
+
val |= temp;
248
+
pmx_writel(pmx, val, muxreg->reg);
249
+
}
250
+
}
251
+
252
+
if (!found) {
253
+
dev_err(pmx->dev, "pinmux group: %s not supported\n",
254
+
pgroup->name);
255
+
return -ENODEV;
256
+
}
257
+
258
+
return 0;
259
+
}
260
+
261
+
static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
262
+
unsigned group)
263
+
{
264
+
return spear_pinctrl_endisable(pctldev, function, group, true);
265
+
}
266
+
267
+
static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
268
+
unsigned function, unsigned group)
269
+
{
270
+
spear_pinctrl_endisable(pctldev, function, group, false);
271
+
}
272
+
273
+
static struct pinmux_ops spear_pinmux_ops = {
274
+
.get_functions_count = spear_pinctrl_get_funcs_count,
275
+
.get_function_name = spear_pinctrl_get_func_name,
276
+
.get_function_groups = spear_pinctrl_get_func_groups,
277
+
.enable = spear_pinctrl_enable,
278
+
.disable = spear_pinctrl_disable,
279
+
};
280
+
281
+
static struct pinctrl_desc spear_pinctrl_desc = {
282
+
.name = DRIVER_NAME,
283
+
.pctlops = &spear_pinctrl_ops,
284
+
.pmxops = &spear_pinmux_ops,
285
+
.owner = THIS_MODULE,
286
+
};
287
+
288
+
int __devinit spear_pinctrl_probe(struct platform_device *pdev,
289
+
struct spear_pinctrl_machdata *machdata)
290
+
{
291
+
struct device_node *np = pdev->dev.of_node;
292
+
struct resource *res;
293
+
struct spear_pmx *pmx;
294
+
295
+
if (!machdata)
296
+
return -ENODEV;
297
+
298
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
299
+
if (!res)
300
+
return -EINVAL;
301
+
302
+
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
303
+
if (!pmx) {
304
+
dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
305
+
return -ENOMEM;
306
+
}
307
+
308
+
pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
309
+
if (!pmx->vbase) {
310
+
dev_err(&pdev->dev, "Couldn't ioremap at index 0\n");
311
+
return -ENODEV;
312
+
}
313
+
314
+
pmx->dev = &pdev->dev;
315
+
pmx->machdata = machdata;
316
+
317
+
/* configure mode, if supported by SoC */
318
+
if (machdata->modes_supported) {
319
+
int mode = 0;
320
+
321
+
if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
322
+
dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
323
+
return -EINVAL;
324
+
}
325
+
326
+
if (set_mode(pmx, mode)) {
327
+
dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
328
+
mode);
329
+
return -EINVAL;
330
+
}
331
+
}
332
+
333
+
platform_set_drvdata(pdev, pmx);
334
+
335
+
spear_pinctrl_desc.pins = machdata->pins;
336
+
spear_pinctrl_desc.npins = machdata->npins;
337
+
338
+
pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
339
+
if (IS_ERR(pmx->pctl)) {
340
+
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
341
+
return PTR_ERR(pmx->pctl);
342
+
}
343
+
344
+
return 0;
345
+
}
346
+
347
+
int __devexit spear_pinctrl_remove(struct platform_device *pdev)
348
+
{
349
+
struct spear_pmx *pmx = platform_get_drvdata(pdev);
350
+
351
+
pinctrl_unregister(pmx->pctl);
352
+
353
+
return 0;
354
+
}
+142
drivers/pinctrl/spear/pinctrl-spear.h
+142
drivers/pinctrl/spear/pinctrl-spear.h
···
1
+
/*
2
+
* Driver header file for the ST Microelectronics SPEAr pinmux
3
+
*
4
+
* Copyright (C) 2012 ST Microelectronics
5
+
* Viresh Kumar <viresh.kumar@st.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#ifndef __PINMUX_SPEAR_H__
13
+
#define __PINMUX_SPEAR_H__
14
+
15
+
#include <linux/pinctrl/pinctrl.h>
16
+
#include <linux/types.h>
17
+
18
+
struct platform_device;
19
+
struct device;
20
+
21
+
/**
22
+
* struct spear_pmx_mode - SPEAr pmx mode
23
+
* @name: name of pmx mode
24
+
* @mode: mode id
25
+
* @reg: register for configuring this mode
26
+
* @mask: mask of this mode in reg
27
+
* @val: val to be configured at reg after doing (val & mask)
28
+
*/
29
+
struct spear_pmx_mode {
30
+
const char *const name;
31
+
u16 mode;
32
+
u16 reg;
33
+
u16 mask;
34
+
u32 val;
35
+
};
36
+
37
+
/**
38
+
* struct spear_muxreg - SPEAr mux reg configuration
39
+
* @reg: register offset
40
+
* @mask: mask bits
41
+
* @val: val to be written on mask bits
42
+
*/
43
+
struct spear_muxreg {
44
+
u16 reg;
45
+
u32 mask;
46
+
u32 val;
47
+
};
48
+
49
+
/**
50
+
* struct spear_modemux - SPEAr mode mux configuration
51
+
* @modes: mode ids supported by this group of muxregs
52
+
* @nmuxregs: number of muxreg configurations to be done for modes
53
+
* @muxregs: array of muxreg configurations to be done for modes
54
+
*/
55
+
struct spear_modemux {
56
+
u16 modes;
57
+
u8 nmuxregs;
58
+
struct spear_muxreg *muxregs;
59
+
};
60
+
61
+
/**
62
+
* struct spear_pingroup - SPEAr pin group configurations
63
+
* @name: name of pin group
64
+
* @pins: array containing pin numbers
65
+
* @npins: size of pins array
66
+
* @modemuxs: array of modemux configurations for this pin group
67
+
* @nmodemuxs: size of array modemuxs
68
+
*
69
+
* A representation of a group of pins in the SPEAr pin controller. Each group
70
+
* allows some parameter or parameters to be configured.
71
+
*/
72
+
struct spear_pingroup {
73
+
const char *name;
74
+
const unsigned *pins;
75
+
unsigned npins;
76
+
struct spear_modemux *modemuxs;
77
+
unsigned nmodemuxs;
78
+
};
79
+
80
+
/**
81
+
* struct spear_function - SPEAr pinctrl mux function
82
+
* @name: The name of the function, exported to pinctrl core.
83
+
* @groups: An array of pin groups that may select this function.
84
+
* @ngroups: The number of entries in @groups.
85
+
*/
86
+
struct spear_function {
87
+
const char *name;
88
+
const char *const *groups;
89
+
unsigned ngroups;
90
+
};
91
+
92
+
/**
93
+
* struct spear_pinctrl_machdata - SPEAr pin controller machine driver
94
+
* configuration
95
+
* @pins: An array describing all pins the pin controller affects.
96
+
* All pins which are also GPIOs must be listed first within the *array,
97
+
* and be numbered identically to the GPIO controller's *numbering.
98
+
* @npins: The numbmer of entries in @pins.
99
+
* @functions: An array describing all mux functions the SoC supports.
100
+
* @nfunctions: The numbmer of entries in @functions.
101
+
* @groups: An array describing all pin groups the pin SoC supports.
102
+
* @ngroups: The numbmer of entries in @groups.
103
+
*
104
+
* @modes_supported: Does SoC support modes
105
+
* @mode: mode configured from probe
106
+
* @pmx_modes: array of modes supported by SoC
107
+
* @npmx_modes: number of entries in pmx_modes.
108
+
*/
109
+
struct spear_pinctrl_machdata {
110
+
const struct pinctrl_pin_desc *pins;
111
+
unsigned npins;
112
+
struct spear_function **functions;
113
+
unsigned nfunctions;
114
+
struct spear_pingroup **groups;
115
+
unsigned ngroups;
116
+
117
+
bool modes_supported;
118
+
u16 mode;
119
+
struct spear_pmx_mode **pmx_modes;
120
+
unsigned npmx_modes;
121
+
};
122
+
123
+
/**
124
+
* struct spear_pmx - SPEAr pinctrl mux
125
+
* @dev: pointer to struct dev of platform_device registered
126
+
* @pctl: pointer to struct pinctrl_dev
127
+
* @machdata: pointer to SoC or machine specific structure
128
+
* @vbase: virtual base address of pinmux controller
129
+
*/
130
+
struct spear_pmx {
131
+
struct device *dev;
132
+
struct pinctrl_dev *pctl;
133
+
struct spear_pinctrl_machdata *machdata;
134
+
void __iomem *vbase;
135
+
};
136
+
137
+
/* exported routines */
138
+
void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
139
+
int __devinit spear_pinctrl_probe(struct platform_device *pdev,
140
+
struct spear_pinctrl_machdata *machdata);
141
+
int __devexit spear_pinctrl_remove(struct platform_device *pdev);
142
+
#endif /* __PINMUX_SPEAR_H__ */
+708
drivers/pinctrl/spear/pinctrl-spear300.c
+708
drivers/pinctrl/spear/pinctrl-spear300.c
···
1
+
/*
2
+
* Driver for the ST Microelectronics SPEAr300 pinmux
3
+
*
4
+
* Copyright (C) 2012 ST Microelectronics
5
+
* Viresh Kumar <viresh.kumar@st.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#include <linux/err.h>
13
+
#include <linux/init.h>
14
+
#include <linux/module.h>
15
+
#include <linux/of_device.h>
16
+
#include <linux/platform_device.h>
17
+
#include "pinctrl-spear3xx.h"
18
+
19
+
#define DRIVER_NAME "spear300-pinmux"
20
+
21
+
/* addresses */
22
+
#define PMX_CONFIG_REG 0x00
23
+
#define MODE_CONFIG_REG 0x04
24
+
25
+
/* modes */
26
+
#define NAND_MODE (1 << 0)
27
+
#define NOR_MODE (1 << 1)
28
+
#define PHOTO_FRAME_MODE (1 << 2)
29
+
#define LEND_IP_PHONE_MODE (1 << 3)
30
+
#define HEND_IP_PHONE_MODE (1 << 4)
31
+
#define LEND_WIFI_PHONE_MODE (1 << 5)
32
+
#define HEND_WIFI_PHONE_MODE (1 << 6)
33
+
#define ATA_PABX_WI2S_MODE (1 << 7)
34
+
#define ATA_PABX_I2S_MODE (1 << 8)
35
+
#define CAML_LCDW_MODE (1 << 9)
36
+
#define CAMU_LCD_MODE (1 << 10)
37
+
#define CAMU_WLCD_MODE (1 << 11)
38
+
#define CAML_LCD_MODE (1 << 12)
39
+
40
+
static struct spear_pmx_mode pmx_mode_nand = {
41
+
.name = "nand",
42
+
.mode = NAND_MODE,
43
+
.reg = MODE_CONFIG_REG,
44
+
.mask = 0x0000000F,
45
+
.val = 0x00,
46
+
};
47
+
48
+
static struct spear_pmx_mode pmx_mode_nor = {
49
+
.name = "nor",
50
+
.mode = NOR_MODE,
51
+
.reg = MODE_CONFIG_REG,
52
+
.mask = 0x0000000F,
53
+
.val = 0x01,
54
+
};
55
+
56
+
static struct spear_pmx_mode pmx_mode_photo_frame = {
57
+
.name = "photo frame mode",
58
+
.mode = PHOTO_FRAME_MODE,
59
+
.reg = MODE_CONFIG_REG,
60
+
.mask = 0x0000000F,
61
+
.val = 0x02,
62
+
};
63
+
64
+
static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
65
+
.name = "lend ip phone mode",
66
+
.mode = LEND_IP_PHONE_MODE,
67
+
.reg = MODE_CONFIG_REG,
68
+
.mask = 0x0000000F,
69
+
.val = 0x03,
70
+
};
71
+
72
+
static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
73
+
.name = "hend ip phone mode",
74
+
.mode = HEND_IP_PHONE_MODE,
75
+
.reg = MODE_CONFIG_REG,
76
+
.mask = 0x0000000F,
77
+
.val = 0x04,
78
+
};
79
+
80
+
static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
81
+
.name = "lend wifi phone mode",
82
+
.mode = LEND_WIFI_PHONE_MODE,
83
+
.reg = MODE_CONFIG_REG,
84
+
.mask = 0x0000000F,
85
+
.val = 0x05,
86
+
};
87
+
88
+
static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
89
+
.name = "hend wifi phone mode",
90
+
.mode = HEND_WIFI_PHONE_MODE,
91
+
.reg = MODE_CONFIG_REG,
92
+
.mask = 0x0000000F,
93
+
.val = 0x06,
94
+
};
95
+
96
+
static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
97
+
.name = "ata pabx wi2s mode",
98
+
.mode = ATA_PABX_WI2S_MODE,
99
+
.reg = MODE_CONFIG_REG,
100
+
.mask = 0x0000000F,
101
+
.val = 0x07,
102
+
};
103
+
104
+
static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
105
+
.name = "ata pabx i2s mode",
106
+
.mode = ATA_PABX_I2S_MODE,
107
+
.reg = MODE_CONFIG_REG,
108
+
.mask = 0x0000000F,
109
+
.val = 0x08,
110
+
};
111
+
112
+
static struct spear_pmx_mode pmx_mode_caml_lcdw = {
113
+
.name = "caml lcdw mode",
114
+
.mode = CAML_LCDW_MODE,
115
+
.reg = MODE_CONFIG_REG,
116
+
.mask = 0x0000000F,
117
+
.val = 0x0C,
118
+
};
119
+
120
+
static struct spear_pmx_mode pmx_mode_camu_lcd = {
121
+
.name = "camu lcd mode",
122
+
.mode = CAMU_LCD_MODE,
123
+
.reg = MODE_CONFIG_REG,
124
+
.mask = 0x0000000F,
125
+
.val = 0x0D,
126
+
};
127
+
128
+
static struct spear_pmx_mode pmx_mode_camu_wlcd = {
129
+
.name = "camu wlcd mode",
130
+
.mode = CAMU_WLCD_MODE,
131
+
.reg = MODE_CONFIG_REG,
132
+
.mask = 0x0000000F,
133
+
.val = 0xE,
134
+
};
135
+
136
+
static struct spear_pmx_mode pmx_mode_caml_lcd = {
137
+
.name = "caml lcd mode",
138
+
.mode = CAML_LCD_MODE,
139
+
.reg = MODE_CONFIG_REG,
140
+
.mask = 0x0000000F,
141
+
.val = 0x0F,
142
+
};
143
+
144
+
static struct spear_pmx_mode *spear300_pmx_modes[] = {
145
+
&pmx_mode_nand,
146
+
&pmx_mode_nor,
147
+
&pmx_mode_photo_frame,
148
+
&pmx_mode_lend_ip_phone,
149
+
&pmx_mode_hend_ip_phone,
150
+
&pmx_mode_lend_wifi_phone,
151
+
&pmx_mode_hend_wifi_phone,
152
+
&pmx_mode_ata_pabx_wi2s,
153
+
&pmx_mode_ata_pabx_i2s,
154
+
&pmx_mode_caml_lcdw,
155
+
&pmx_mode_camu_lcd,
156
+
&pmx_mode_camu_wlcd,
157
+
&pmx_mode_caml_lcd,
158
+
};
159
+
160
+
/* fsmc_2chips_pins */
161
+
static const unsigned fsmc_2chips_pins[] = { 1, 97 };
162
+
static struct spear_muxreg fsmc_2chips_muxreg[] = {
163
+
{
164
+
.reg = PMX_CONFIG_REG,
165
+
.mask = PMX_FIRDA_MASK,
166
+
.val = 0,
167
+
},
168
+
};
169
+
170
+
static struct spear_modemux fsmc_2chips_modemux[] = {
171
+
{
172
+
.modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
173
+
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
174
+
.muxregs = fsmc_2chips_muxreg,
175
+
.nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
176
+
},
177
+
};
178
+
179
+
static struct spear_pingroup fsmc_2chips_pingroup = {
180
+
.name = "fsmc_2chips_grp",
181
+
.pins = fsmc_2chips_pins,
182
+
.npins = ARRAY_SIZE(fsmc_2chips_pins),
183
+
.modemuxs = fsmc_2chips_modemux,
184
+
.nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
185
+
};
186
+
187
+
/* fsmc_4chips_pins */
188
+
static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
189
+
static struct spear_muxreg fsmc_4chips_muxreg[] = {
190
+
{
191
+
.reg = PMX_CONFIG_REG,
192
+
.mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
193
+
.val = 0,
194
+
},
195
+
};
196
+
197
+
static struct spear_modemux fsmc_4chips_modemux[] = {
198
+
{
199
+
.modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
200
+
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
201
+
.muxregs = fsmc_4chips_muxreg,
202
+
.nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
203
+
},
204
+
};
205
+
206
+
static struct spear_pingroup fsmc_4chips_pingroup = {
207
+
.name = "fsmc_4chips_grp",
208
+
.pins = fsmc_4chips_pins,
209
+
.npins = ARRAY_SIZE(fsmc_4chips_pins),
210
+
.modemuxs = fsmc_4chips_modemux,
211
+
.nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
212
+
};
213
+
214
+
static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
215
+
};
216
+
static struct spear_function fsmc_function = {
217
+
.name = "fsmc",
218
+
.groups = fsmc_grps,
219
+
.ngroups = ARRAY_SIZE(fsmc_grps),
220
+
};
221
+
222
+
/* clcd_lcdmode_pins */
223
+
static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
224
+
static struct spear_muxreg clcd_lcdmode_muxreg[] = {
225
+
{
226
+
.reg = PMX_CONFIG_REG,
227
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
228
+
.val = 0,
229
+
},
230
+
};
231
+
232
+
static struct spear_modemux clcd_lcdmode_modemux[] = {
233
+
{
234
+
.modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
235
+
CAMU_LCD_MODE | CAML_LCD_MODE,
236
+
.muxregs = clcd_lcdmode_muxreg,
237
+
.nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
238
+
},
239
+
};
240
+
241
+
static struct spear_pingroup clcd_lcdmode_pingroup = {
242
+
.name = "clcd_lcdmode_grp",
243
+
.pins = clcd_lcdmode_pins,
244
+
.npins = ARRAY_SIZE(clcd_lcdmode_pins),
245
+
.modemuxs = clcd_lcdmode_modemux,
246
+
.nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
247
+
};
248
+
249
+
/* clcd_pfmode_pins */
250
+
static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
251
+
static struct spear_muxreg clcd_pfmode_muxreg[] = {
252
+
{
253
+
.reg = PMX_CONFIG_REG,
254
+
.mask = PMX_TIMER_2_3_MASK,
255
+
.val = 0,
256
+
},
257
+
};
258
+
259
+
static struct spear_modemux clcd_pfmode_modemux[] = {
260
+
{
261
+
.modes = PHOTO_FRAME_MODE,
262
+
.muxregs = clcd_pfmode_muxreg,
263
+
.nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
264
+
},
265
+
};
266
+
267
+
static struct spear_pingroup clcd_pfmode_pingroup = {
268
+
.name = "clcd_pfmode_grp",
269
+
.pins = clcd_pfmode_pins,
270
+
.npins = ARRAY_SIZE(clcd_pfmode_pins),
271
+
.modemuxs = clcd_pfmode_modemux,
272
+
.nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
273
+
};
274
+
275
+
static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
276
+
};
277
+
static struct spear_function clcd_function = {
278
+
.name = "clcd",
279
+
.groups = clcd_grps,
280
+
.ngroups = ARRAY_SIZE(clcd_grps),
281
+
};
282
+
283
+
/* tdm_pins */
284
+
static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
285
+
static struct spear_muxreg tdm_muxreg[] = {
286
+
{
287
+
.reg = PMX_CONFIG_REG,
288
+
.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
289
+
.val = 0,
290
+
},
291
+
};
292
+
293
+
static struct spear_modemux tdm_modemux[] = {
294
+
{
295
+
.modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
296
+
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
297
+
| HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
298
+
| ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
299
+
| CAMU_WLCD_MODE | CAML_LCD_MODE,
300
+
.muxregs = tdm_muxreg,
301
+
.nmuxregs = ARRAY_SIZE(tdm_muxreg),
302
+
},
303
+
};
304
+
305
+
static struct spear_pingroup tdm_pingroup = {
306
+
.name = "tdm_grp",
307
+
.pins = tdm_pins,
308
+
.npins = ARRAY_SIZE(tdm_pins),
309
+
.modemuxs = tdm_modemux,
310
+
.nmodemuxs = ARRAY_SIZE(tdm_modemux),
311
+
};
312
+
313
+
static const char *const tdm_grps[] = { "tdm_grp" };
314
+
static struct spear_function tdm_function = {
315
+
.name = "tdm",
316
+
.groups = tdm_grps,
317
+
.ngroups = ARRAY_SIZE(tdm_grps),
318
+
};
319
+
320
+
/* i2c_clk_pins */
321
+
static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
322
+
static struct spear_muxreg i2c_clk_muxreg[] = {
323
+
{
324
+
.reg = PMX_CONFIG_REG,
325
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
326
+
.val = 0,
327
+
},
328
+
};
329
+
330
+
static struct spear_modemux i2c_clk_modemux[] = {
331
+
{
332
+
.modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
333
+
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
334
+
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
335
+
| CAML_LCD_MODE,
336
+
.muxregs = i2c_clk_muxreg,
337
+
.nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
338
+
},
339
+
};
340
+
341
+
static struct spear_pingroup i2c_clk_pingroup = {
342
+
.name = "i2c_clk_grp_grp",
343
+
.pins = i2c_clk_pins,
344
+
.npins = ARRAY_SIZE(i2c_clk_pins),
345
+
.modemuxs = i2c_clk_modemux,
346
+
.nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
347
+
};
348
+
349
+
static const char *const i2c_grps[] = { "i2c_clk_grp" };
350
+
static struct spear_function i2c_function = {
351
+
.name = "i2c1",
352
+
.groups = i2c_grps,
353
+
.ngroups = ARRAY_SIZE(i2c_grps),
354
+
};
355
+
356
+
/* caml_pins */
357
+
static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
358
+
static struct spear_muxreg caml_muxreg[] = {
359
+
{
360
+
.reg = PMX_CONFIG_REG,
361
+
.mask = PMX_MII_MASK,
362
+
.val = 0,
363
+
},
364
+
};
365
+
366
+
static struct spear_modemux caml_modemux[] = {
367
+
{
368
+
.modes = CAML_LCDW_MODE | CAML_LCD_MODE,
369
+
.muxregs = caml_muxreg,
370
+
.nmuxregs = ARRAY_SIZE(caml_muxreg),
371
+
},
372
+
};
373
+
374
+
static struct spear_pingroup caml_pingroup = {
375
+
.name = "caml_grp",
376
+
.pins = caml_pins,
377
+
.npins = ARRAY_SIZE(caml_pins),
378
+
.modemuxs = caml_modemux,
379
+
.nmodemuxs = ARRAY_SIZE(caml_modemux),
380
+
};
381
+
382
+
/* camu_pins */
383
+
static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
384
+
static struct spear_muxreg camu_muxreg[] = {
385
+
{
386
+
.reg = PMX_CONFIG_REG,
387
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
388
+
.val = 0,
389
+
},
390
+
};
391
+
392
+
static struct spear_modemux camu_modemux[] = {
393
+
{
394
+
.modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
395
+
.muxregs = camu_muxreg,
396
+
.nmuxregs = ARRAY_SIZE(camu_muxreg),
397
+
},
398
+
};
399
+
400
+
static struct spear_pingroup camu_pingroup = {
401
+
.name = "camu_grp",
402
+
.pins = camu_pins,
403
+
.npins = ARRAY_SIZE(camu_pins),
404
+
.modemuxs = camu_modemux,
405
+
.nmodemuxs = ARRAY_SIZE(camu_modemux),
406
+
};
407
+
408
+
static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
409
+
static struct spear_function cam_function = {
410
+
.name = "cam",
411
+
.groups = cam_grps,
412
+
.ngroups = ARRAY_SIZE(cam_grps),
413
+
};
414
+
415
+
/* dac_pins */
416
+
static const unsigned dac_pins[] = { 43, 44 };
417
+
static struct spear_muxreg dac_muxreg[] = {
418
+
{
419
+
.reg = PMX_CONFIG_REG,
420
+
.mask = PMX_TIMER_0_1_MASK,
421
+
.val = 0,
422
+
},
423
+
};
424
+
425
+
static struct spear_modemux dac_modemux[] = {
426
+
{
427
+
.modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
428
+
| CAMU_WLCD_MODE | CAML_LCD_MODE,
429
+
.muxregs = dac_muxreg,
430
+
.nmuxregs = ARRAY_SIZE(dac_muxreg),
431
+
},
432
+
};
433
+
434
+
static struct spear_pingroup dac_pingroup = {
435
+
.name = "dac_grp",
436
+
.pins = dac_pins,
437
+
.npins = ARRAY_SIZE(dac_pins),
438
+
.modemuxs = dac_modemux,
439
+
.nmodemuxs = ARRAY_SIZE(dac_modemux),
440
+
};
441
+
442
+
static const char *const dac_grps[] = { "dac_grp" };
443
+
static struct spear_function dac_function = {
444
+
.name = "dac",
445
+
.groups = dac_grps,
446
+
.ngroups = ARRAY_SIZE(dac_grps),
447
+
};
448
+
449
+
/* i2s_pins */
450
+
static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
451
+
static struct spear_muxreg i2s_muxreg[] = {
452
+
{
453
+
.reg = PMX_CONFIG_REG,
454
+
.mask = PMX_UART0_MODEM_MASK,
455
+
.val = 0,
456
+
},
457
+
};
458
+
459
+
static struct spear_modemux i2s_modemux[] = {
460
+
{
461
+
.modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
462
+
| LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
463
+
ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
464
+
| CAMU_WLCD_MODE | CAML_LCD_MODE,
465
+
.muxregs = i2s_muxreg,
466
+
.nmuxregs = ARRAY_SIZE(i2s_muxreg),
467
+
},
468
+
};
469
+
470
+
static struct spear_pingroup i2s_pingroup = {
471
+
.name = "i2s_grp",
472
+
.pins = i2s_pins,
473
+
.npins = ARRAY_SIZE(i2s_pins),
474
+
.modemuxs = i2s_modemux,
475
+
.nmodemuxs = ARRAY_SIZE(i2s_modemux),
476
+
};
477
+
478
+
static const char *const i2s_grps[] = { "i2s_grp" };
479
+
static struct spear_function i2s_function = {
480
+
.name = "i2s",
481
+
.groups = i2s_grps,
482
+
.ngroups = ARRAY_SIZE(i2s_grps),
483
+
};
484
+
485
+
/* sdhci_4bit_pins */
486
+
static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
487
+
static struct spear_muxreg sdhci_4bit_muxreg[] = {
488
+
{
489
+
.reg = PMX_CONFIG_REG,
490
+
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
491
+
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
492
+
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
493
+
.val = 0,
494
+
},
495
+
};
496
+
497
+
static struct spear_modemux sdhci_4bit_modemux[] = {
498
+
{
499
+
.modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
500
+
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
501
+
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
502
+
CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
503
+
.muxregs = sdhci_4bit_muxreg,
504
+
.nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
505
+
},
506
+
};
507
+
508
+
static struct spear_pingroup sdhci_4bit_pingroup = {
509
+
.name = "sdhci_4bit_grp",
510
+
.pins = sdhci_4bit_pins,
511
+
.npins = ARRAY_SIZE(sdhci_4bit_pins),
512
+
.modemuxs = sdhci_4bit_modemux,
513
+
.nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
514
+
};
515
+
516
+
/* sdhci_8bit_pins */
517
+
static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
518
+
33 };
519
+
static struct spear_muxreg sdhci_8bit_muxreg[] = {
520
+
{
521
+
.reg = PMX_CONFIG_REG,
522
+
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
523
+
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
524
+
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
525
+
.val = 0,
526
+
},
527
+
};
528
+
529
+
static struct spear_modemux sdhci_8bit_modemux[] = {
530
+
{
531
+
.modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
532
+
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
533
+
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
534
+
CAMU_WLCD_MODE | CAML_LCD_MODE,
535
+
.muxregs = sdhci_8bit_muxreg,
536
+
.nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
537
+
},
538
+
};
539
+
540
+
static struct spear_pingroup sdhci_8bit_pingroup = {
541
+
.name = "sdhci_8bit_grp",
542
+
.pins = sdhci_8bit_pins,
543
+
.npins = ARRAY_SIZE(sdhci_8bit_pins),
544
+
.modemuxs = sdhci_8bit_modemux,
545
+
.nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
546
+
};
547
+
548
+
static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
549
+
static struct spear_function sdhci_function = {
550
+
.name = "sdhci",
551
+
.groups = sdhci_grps,
552
+
.ngroups = ARRAY_SIZE(sdhci_grps),
553
+
};
554
+
555
+
/* gpio1_0_to_3_pins */
556
+
static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
557
+
static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
558
+
{
559
+
.reg = PMX_CONFIG_REG,
560
+
.mask = PMX_UART0_MODEM_MASK,
561
+
.val = 0,
562
+
},
563
+
};
564
+
565
+
static struct spear_modemux gpio1_0_to_3_modemux[] = {
566
+
{
567
+
.modes = PHOTO_FRAME_MODE,
568
+
.muxregs = gpio1_0_to_3_muxreg,
569
+
.nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
570
+
},
571
+
};
572
+
573
+
static struct spear_pingroup gpio1_0_to_3_pingroup = {
574
+
.name = "gpio1_0_to_3_grp",
575
+
.pins = gpio1_0_to_3_pins,
576
+
.npins = ARRAY_SIZE(gpio1_0_to_3_pins),
577
+
.modemuxs = gpio1_0_to_3_modemux,
578
+
.nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
579
+
};
580
+
581
+
/* gpio1_4_to_7_pins */
582
+
static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
583
+
584
+
static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
585
+
{
586
+
.reg = PMX_CONFIG_REG,
587
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
588
+
.val = 0,
589
+
},
590
+
};
591
+
592
+
static struct spear_modemux gpio1_4_to_7_modemux[] = {
593
+
{
594
+
.modes = PHOTO_FRAME_MODE,
595
+
.muxregs = gpio1_4_to_7_muxreg,
596
+
.nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
597
+
},
598
+
};
599
+
600
+
static struct spear_pingroup gpio1_4_to_7_pingroup = {
601
+
.name = "gpio1_4_to_7_grp",
602
+
.pins = gpio1_4_to_7_pins,
603
+
.npins = ARRAY_SIZE(gpio1_4_to_7_pins),
604
+
.modemuxs = gpio1_4_to_7_modemux,
605
+
.nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
606
+
};
607
+
608
+
static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
609
+
};
610
+
static struct spear_function gpio1_function = {
611
+
.name = "gpio1",
612
+
.groups = gpio1_grps,
613
+
.ngroups = ARRAY_SIZE(gpio1_grps),
614
+
};
615
+
616
+
/* pingroups */
617
+
static struct spear_pingroup *spear300_pingroups[] = {
618
+
SPEAR3XX_COMMON_PINGROUPS,
619
+
&fsmc_2chips_pingroup,
620
+
&fsmc_4chips_pingroup,
621
+
&clcd_lcdmode_pingroup,
622
+
&clcd_pfmode_pingroup,
623
+
&tdm_pingroup,
624
+
&i2c_clk_pingroup,
625
+
&caml_pingroup,
626
+
&camu_pingroup,
627
+
&dac_pingroup,
628
+
&i2s_pingroup,
629
+
&sdhci_4bit_pingroup,
630
+
&sdhci_8bit_pingroup,
631
+
&gpio1_0_to_3_pingroup,
632
+
&gpio1_4_to_7_pingroup,
633
+
};
634
+
635
+
/* functions */
636
+
static struct spear_function *spear300_functions[] = {
637
+
SPEAR3XX_COMMON_FUNCTIONS,
638
+
&fsmc_function,
639
+
&clcd_function,
640
+
&tdm_function,
641
+
&i2c_function,
642
+
&cam_function,
643
+
&dac_function,
644
+
&i2s_function,
645
+
&sdhci_function,
646
+
&gpio1_function,
647
+
};
648
+
649
+
static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = {
650
+
{
651
+
.compatible = "st,spear300-pinmux",
652
+
},
653
+
{},
654
+
};
655
+
656
+
static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
657
+
{
658
+
int ret;
659
+
660
+
spear3xx_machdata.groups = spear300_pingroups;
661
+
spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
662
+
spear3xx_machdata.functions = spear300_functions;
663
+
spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
664
+
665
+
spear3xx_machdata.modes_supported = true;
666
+
spear3xx_machdata.pmx_modes = spear300_pmx_modes;
667
+
spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
668
+
669
+
pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
670
+
671
+
ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
672
+
if (ret)
673
+
return ret;
674
+
675
+
return 0;
676
+
}
677
+
678
+
static int __devexit spear300_pinctrl_remove(struct platform_device *pdev)
679
+
{
680
+
return spear_pinctrl_remove(pdev);
681
+
}
682
+
683
+
static struct platform_driver spear300_pinctrl_driver = {
684
+
.driver = {
685
+
.name = DRIVER_NAME,
686
+
.owner = THIS_MODULE,
687
+
.of_match_table = spear300_pinctrl_of_match,
688
+
},
689
+
.probe = spear300_pinctrl_probe,
690
+
.remove = __devexit_p(spear300_pinctrl_remove),
691
+
};
692
+
693
+
static int __init spear300_pinctrl_init(void)
694
+
{
695
+
return platform_driver_register(&spear300_pinctrl_driver);
696
+
}
697
+
arch_initcall(spear300_pinctrl_init);
698
+
699
+
static void __exit spear300_pinctrl_exit(void)
700
+
{
701
+
platform_driver_unregister(&spear300_pinctrl_driver);
702
+
}
703
+
module_exit(spear300_pinctrl_exit);
704
+
705
+
MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
706
+
MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver");
707
+
MODULE_LICENSE("GPL v2");
708
+
MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match);
+431
drivers/pinctrl/spear/pinctrl-spear310.c
+431
drivers/pinctrl/spear/pinctrl-spear310.c
···
1
+
/*
2
+
* Driver for the ST Microelectronics SPEAr310 pinmux
3
+
*
4
+
* Copyright (C) 2012 ST Microelectronics
5
+
* Viresh Kumar <viresh.kumar@st.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#include <linux/err.h>
13
+
#include <linux/init.h>
14
+
#include <linux/module.h>
15
+
#include <linux/of_device.h>
16
+
#include <linux/platform_device.h>
17
+
#include "pinctrl-spear3xx.h"
18
+
19
+
#define DRIVER_NAME "spear310-pinmux"
20
+
21
+
/* addresses */
22
+
#define PMX_CONFIG_REG 0x08
23
+
24
+
/* emi_cs_0_to_5_pins */
25
+
static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
26
+
static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
27
+
{
28
+
.reg = PMX_CONFIG_REG,
29
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
30
+
.val = 0,
31
+
},
32
+
};
33
+
34
+
static struct spear_modemux emi_cs_0_to_5_modemux[] = {
35
+
{
36
+
.muxregs = emi_cs_0_to_5_muxreg,
37
+
.nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
38
+
},
39
+
};
40
+
41
+
static struct spear_pingroup emi_cs_0_to_5_pingroup = {
42
+
.name = "emi_cs_0_to_5_grp",
43
+
.pins = emi_cs_0_to_5_pins,
44
+
.npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
45
+
.modemuxs = emi_cs_0_to_5_modemux,
46
+
.nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
47
+
};
48
+
49
+
static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
50
+
static struct spear_function emi_cs_0_to_5_function = {
51
+
.name = "emi",
52
+
.groups = emi_cs_0_to_5_grps,
53
+
.ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
54
+
};
55
+
56
+
/* uart1_pins */
57
+
static const unsigned uart1_pins[] = { 0, 1 };
58
+
static struct spear_muxreg uart1_muxreg[] = {
59
+
{
60
+
.reg = PMX_CONFIG_REG,
61
+
.mask = PMX_FIRDA_MASK,
62
+
.val = 0,
63
+
},
64
+
};
65
+
66
+
static struct spear_modemux uart1_modemux[] = {
67
+
{
68
+
.muxregs = uart1_muxreg,
69
+
.nmuxregs = ARRAY_SIZE(uart1_muxreg),
70
+
},
71
+
};
72
+
73
+
static struct spear_pingroup uart1_pingroup = {
74
+
.name = "uart1_grp",
75
+
.pins = uart1_pins,
76
+
.npins = ARRAY_SIZE(uart1_pins),
77
+
.modemuxs = uart1_modemux,
78
+
.nmodemuxs = ARRAY_SIZE(uart1_modemux),
79
+
};
80
+
81
+
static const char *const uart1_grps[] = { "uart1_grp" };
82
+
static struct spear_function uart1_function = {
83
+
.name = "uart1",
84
+
.groups = uart1_grps,
85
+
.ngroups = ARRAY_SIZE(uart1_grps),
86
+
};
87
+
88
+
/* uart2_pins */
89
+
static const unsigned uart2_pins[] = { 43, 44 };
90
+
static struct spear_muxreg uart2_muxreg[] = {
91
+
{
92
+
.reg = PMX_CONFIG_REG,
93
+
.mask = PMX_TIMER_0_1_MASK,
94
+
.val = 0,
95
+
},
96
+
};
97
+
98
+
static struct spear_modemux uart2_modemux[] = {
99
+
{
100
+
.muxregs = uart2_muxreg,
101
+
.nmuxregs = ARRAY_SIZE(uart2_muxreg),
102
+
},
103
+
};
104
+
105
+
static struct spear_pingroup uart2_pingroup = {
106
+
.name = "uart2_grp",
107
+
.pins = uart2_pins,
108
+
.npins = ARRAY_SIZE(uart2_pins),
109
+
.modemuxs = uart2_modemux,
110
+
.nmodemuxs = ARRAY_SIZE(uart2_modemux),
111
+
};
112
+
113
+
static const char *const uart2_grps[] = { "uart2_grp" };
114
+
static struct spear_function uart2_function = {
115
+
.name = "uart2",
116
+
.groups = uart2_grps,
117
+
.ngroups = ARRAY_SIZE(uart2_grps),
118
+
};
119
+
120
+
/* uart3_pins */
121
+
static const unsigned uart3_pins[] = { 37, 38 };
122
+
static struct spear_muxreg uart3_muxreg[] = {
123
+
{
124
+
.reg = PMX_CONFIG_REG,
125
+
.mask = PMX_UART0_MODEM_MASK,
126
+
.val = 0,
127
+
},
128
+
};
129
+
130
+
static struct spear_modemux uart3_modemux[] = {
131
+
{
132
+
.muxregs = uart3_muxreg,
133
+
.nmuxregs = ARRAY_SIZE(uart3_muxreg),
134
+
},
135
+
};
136
+
137
+
static struct spear_pingroup uart3_pingroup = {
138
+
.name = "uart3_grp",
139
+
.pins = uart3_pins,
140
+
.npins = ARRAY_SIZE(uart3_pins),
141
+
.modemuxs = uart3_modemux,
142
+
.nmodemuxs = ARRAY_SIZE(uart3_modemux),
143
+
};
144
+
145
+
static const char *const uart3_grps[] = { "uart3_grp" };
146
+
static struct spear_function uart3_function = {
147
+
.name = "uart3",
148
+
.groups = uart3_grps,
149
+
.ngroups = ARRAY_SIZE(uart3_grps),
150
+
};
151
+
152
+
/* uart4_pins */
153
+
static const unsigned uart4_pins[] = { 39, 40 };
154
+
static struct spear_muxreg uart4_muxreg[] = {
155
+
{
156
+
.reg = PMX_CONFIG_REG,
157
+
.mask = PMX_UART0_MODEM_MASK,
158
+
.val = 0,
159
+
},
160
+
};
161
+
162
+
static struct spear_modemux uart4_modemux[] = {
163
+
{
164
+
.muxregs = uart4_muxreg,
165
+
.nmuxregs = ARRAY_SIZE(uart4_muxreg),
166
+
},
167
+
};
168
+
169
+
static struct spear_pingroup uart4_pingroup = {
170
+
.name = "uart4_grp",
171
+
.pins = uart4_pins,
172
+
.npins = ARRAY_SIZE(uart4_pins),
173
+
.modemuxs = uart4_modemux,
174
+
.nmodemuxs = ARRAY_SIZE(uart4_modemux),
175
+
};
176
+
177
+
static const char *const uart4_grps[] = { "uart4_grp" };
178
+
static struct spear_function uart4_function = {
179
+
.name = "uart4",
180
+
.groups = uart4_grps,
181
+
.ngroups = ARRAY_SIZE(uart4_grps),
182
+
};
183
+
184
+
/* uart5_pins */
185
+
static const unsigned uart5_pins[] = { 41, 42 };
186
+
static struct spear_muxreg uart5_muxreg[] = {
187
+
{
188
+
.reg = PMX_CONFIG_REG,
189
+
.mask = PMX_UART0_MODEM_MASK,
190
+
.val = 0,
191
+
},
192
+
};
193
+
194
+
static struct spear_modemux uart5_modemux[] = {
195
+
{
196
+
.muxregs = uart5_muxreg,
197
+
.nmuxregs = ARRAY_SIZE(uart5_muxreg),
198
+
},
199
+
};
200
+
201
+
static struct spear_pingroup uart5_pingroup = {
202
+
.name = "uart5_grp",
203
+
.pins = uart5_pins,
204
+
.npins = ARRAY_SIZE(uart5_pins),
205
+
.modemuxs = uart5_modemux,
206
+
.nmodemuxs = ARRAY_SIZE(uart5_modemux),
207
+
};
208
+
209
+
static const char *const uart5_grps[] = { "uart5_grp" };
210
+
static struct spear_function uart5_function = {
211
+
.name = "uart5",
212
+
.groups = uart5_grps,
213
+
.ngroups = ARRAY_SIZE(uart5_grps),
214
+
};
215
+
216
+
/* fsmc_pins */
217
+
static const unsigned fsmc_pins[] = { 34, 35, 36 };
218
+
static struct spear_muxreg fsmc_muxreg[] = {
219
+
{
220
+
.reg = PMX_CONFIG_REG,
221
+
.mask = PMX_SSP_CS_MASK,
222
+
.val = 0,
223
+
},
224
+
};
225
+
226
+
static struct spear_modemux fsmc_modemux[] = {
227
+
{
228
+
.muxregs = fsmc_muxreg,
229
+
.nmuxregs = ARRAY_SIZE(fsmc_muxreg),
230
+
},
231
+
};
232
+
233
+
static struct spear_pingroup fsmc_pingroup = {
234
+
.name = "fsmc_grp",
235
+
.pins = fsmc_pins,
236
+
.npins = ARRAY_SIZE(fsmc_pins),
237
+
.modemuxs = fsmc_modemux,
238
+
.nmodemuxs = ARRAY_SIZE(fsmc_modemux),
239
+
};
240
+
241
+
static const char *const fsmc_grps[] = { "fsmc_grp" };
242
+
static struct spear_function fsmc_function = {
243
+
.name = "fsmc",
244
+
.groups = fsmc_grps,
245
+
.ngroups = ARRAY_SIZE(fsmc_grps),
246
+
};
247
+
248
+
/* rs485_0_pins */
249
+
static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
250
+
static struct spear_muxreg rs485_0_muxreg[] = {
251
+
{
252
+
.reg = PMX_CONFIG_REG,
253
+
.mask = PMX_MII_MASK,
254
+
.val = 0,
255
+
},
256
+
};
257
+
258
+
static struct spear_modemux rs485_0_modemux[] = {
259
+
{
260
+
.muxregs = rs485_0_muxreg,
261
+
.nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
262
+
},
263
+
};
264
+
265
+
static struct spear_pingroup rs485_0_pingroup = {
266
+
.name = "rs485_0_grp",
267
+
.pins = rs485_0_pins,
268
+
.npins = ARRAY_SIZE(rs485_0_pins),
269
+
.modemuxs = rs485_0_modemux,
270
+
.nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
271
+
};
272
+
273
+
static const char *const rs485_0_grps[] = { "rs485_0" };
274
+
static struct spear_function rs485_0_function = {
275
+
.name = "rs485_0",
276
+
.groups = rs485_0_grps,
277
+
.ngroups = ARRAY_SIZE(rs485_0_grps),
278
+
};
279
+
280
+
/* rs485_1_pins */
281
+
static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
282
+
static struct spear_muxreg rs485_1_muxreg[] = {
283
+
{
284
+
.reg = PMX_CONFIG_REG,
285
+
.mask = PMX_MII_MASK,
286
+
.val = 0,
287
+
},
288
+
};
289
+
290
+
static struct spear_modemux rs485_1_modemux[] = {
291
+
{
292
+
.muxregs = rs485_1_muxreg,
293
+
.nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
294
+
},
295
+
};
296
+
297
+
static struct spear_pingroup rs485_1_pingroup = {
298
+
.name = "rs485_1_grp",
299
+
.pins = rs485_1_pins,
300
+
.npins = ARRAY_SIZE(rs485_1_pins),
301
+
.modemuxs = rs485_1_modemux,
302
+
.nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
303
+
};
304
+
305
+
static const char *const rs485_1_grps[] = { "rs485_1" };
306
+
static struct spear_function rs485_1_function = {
307
+
.name = "rs485_1",
308
+
.groups = rs485_1_grps,
309
+
.ngroups = ARRAY_SIZE(rs485_1_grps),
310
+
};
311
+
312
+
/* tdm_pins */
313
+
static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
314
+
static struct spear_muxreg tdm_muxreg[] = {
315
+
{
316
+
.reg = PMX_CONFIG_REG,
317
+
.mask = PMX_MII_MASK,
318
+
.val = 0,
319
+
},
320
+
};
321
+
322
+
static struct spear_modemux tdm_modemux[] = {
323
+
{
324
+
.muxregs = tdm_muxreg,
325
+
.nmuxregs = ARRAY_SIZE(tdm_muxreg),
326
+
},
327
+
};
328
+
329
+
static struct spear_pingroup tdm_pingroup = {
330
+
.name = "tdm_grp",
331
+
.pins = tdm_pins,
332
+
.npins = ARRAY_SIZE(tdm_pins),
333
+
.modemuxs = tdm_modemux,
334
+
.nmodemuxs = ARRAY_SIZE(tdm_modemux),
335
+
};
336
+
337
+
static const char *const tdm_grps[] = { "tdm_grp" };
338
+
static struct spear_function tdm_function = {
339
+
.name = "tdm",
340
+
.groups = tdm_grps,
341
+
.ngroups = ARRAY_SIZE(tdm_grps),
342
+
};
343
+
344
+
/* pingroups */
345
+
static struct spear_pingroup *spear310_pingroups[] = {
346
+
SPEAR3XX_COMMON_PINGROUPS,
347
+
&emi_cs_0_to_5_pingroup,
348
+
&uart1_pingroup,
349
+
&uart2_pingroup,
350
+
&uart3_pingroup,
351
+
&uart4_pingroup,
352
+
&uart5_pingroup,
353
+
&fsmc_pingroup,
354
+
&rs485_0_pingroup,
355
+
&rs485_1_pingroup,
356
+
&tdm_pingroup,
357
+
};
358
+
359
+
/* functions */
360
+
static struct spear_function *spear310_functions[] = {
361
+
SPEAR3XX_COMMON_FUNCTIONS,
362
+
&emi_cs_0_to_5_function,
363
+
&uart1_function,
364
+
&uart2_function,
365
+
&uart3_function,
366
+
&uart4_function,
367
+
&uart5_function,
368
+
&fsmc_function,
369
+
&rs485_0_function,
370
+
&rs485_1_function,
371
+
&tdm_function,
372
+
};
373
+
374
+
static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = {
375
+
{
376
+
.compatible = "st,spear310-pinmux",
377
+
},
378
+
{},
379
+
};
380
+
381
+
static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
382
+
{
383
+
int ret;
384
+
385
+
spear3xx_machdata.groups = spear310_pingroups;
386
+
spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
387
+
spear3xx_machdata.functions = spear310_functions;
388
+
spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
389
+
390
+
pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
391
+
392
+
spear3xx_machdata.modes_supported = false;
393
+
394
+
ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
395
+
if (ret)
396
+
return ret;
397
+
398
+
return 0;
399
+
}
400
+
401
+
static int __devexit spear310_pinctrl_remove(struct platform_device *pdev)
402
+
{
403
+
return spear_pinctrl_remove(pdev);
404
+
}
405
+
406
+
static struct platform_driver spear310_pinctrl_driver = {
407
+
.driver = {
408
+
.name = DRIVER_NAME,
409
+
.owner = THIS_MODULE,
410
+
.of_match_table = spear310_pinctrl_of_match,
411
+
},
412
+
.probe = spear310_pinctrl_probe,
413
+
.remove = __devexit_p(spear310_pinctrl_remove),
414
+
};
415
+
416
+
static int __init spear310_pinctrl_init(void)
417
+
{
418
+
return platform_driver_register(&spear310_pinctrl_driver);
419
+
}
420
+
arch_initcall(spear310_pinctrl_init);
421
+
422
+
static void __exit spear310_pinctrl_exit(void)
423
+
{
424
+
platform_driver_unregister(&spear310_pinctrl_driver);
425
+
}
426
+
module_exit(spear310_pinctrl_exit);
427
+
428
+
MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
429
+
MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
430
+
MODULE_LICENSE("GPL v2");
431
+
MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);
+3468
drivers/pinctrl/spear/pinctrl-spear320.c
+3468
drivers/pinctrl/spear/pinctrl-spear320.c
···
1
+
/*
2
+
* Driver for the ST Microelectronics SPEAr320 pinmux
3
+
*
4
+
* Copyright (C) 2012 ST Microelectronics
5
+
* Viresh Kumar <viresh.kumar@st.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#include <linux/err.h>
13
+
#include <linux/init.h>
14
+
#include <linux/module.h>
15
+
#include <linux/of_device.h>
16
+
#include <linux/platform_device.h>
17
+
#include "pinctrl-spear3xx.h"
18
+
19
+
#define DRIVER_NAME "spear320-pinmux"
20
+
21
+
/* addresses */
22
+
#define PMX_CONFIG_REG 0x0C
23
+
#define MODE_CONFIG_REG 0x10
24
+
#define MODE_EXT_CONFIG_REG 0x18
25
+
26
+
/* modes */
27
+
#define AUTO_NET_SMII_MODE (1 << 0)
28
+
#define AUTO_NET_MII_MODE (1 << 1)
29
+
#define AUTO_EXP_MODE (1 << 2)
30
+
#define SMALL_PRINTERS_MODE (1 << 3)
31
+
#define EXTENDED_MODE (1 << 4)
32
+
33
+
static struct spear_pmx_mode pmx_mode_auto_net_smii = {
34
+
.name = "Automation Networking SMII mode",
35
+
.mode = AUTO_NET_SMII_MODE,
36
+
.reg = MODE_CONFIG_REG,
37
+
.mask = 0x00000007,
38
+
.val = 0x0,
39
+
};
40
+
41
+
static struct spear_pmx_mode pmx_mode_auto_net_mii = {
42
+
.name = "Automation Networking MII mode",
43
+
.mode = AUTO_NET_MII_MODE,
44
+
.reg = MODE_CONFIG_REG,
45
+
.mask = 0x00000007,
46
+
.val = 0x1,
47
+
};
48
+
49
+
static struct spear_pmx_mode pmx_mode_auto_exp = {
50
+
.name = "Automation Expanded mode",
51
+
.mode = AUTO_EXP_MODE,
52
+
.reg = MODE_CONFIG_REG,
53
+
.mask = 0x00000007,
54
+
.val = 0x2,
55
+
};
56
+
57
+
static struct spear_pmx_mode pmx_mode_small_printers = {
58
+
.name = "Small Printers mode",
59
+
.mode = SMALL_PRINTERS_MODE,
60
+
.reg = MODE_CONFIG_REG,
61
+
.mask = 0x00000007,
62
+
.val = 0x3,
63
+
};
64
+
65
+
static struct spear_pmx_mode pmx_mode_extended = {
66
+
.name = "extended mode",
67
+
.mode = EXTENDED_MODE,
68
+
.reg = MODE_EXT_CONFIG_REG,
69
+
.mask = 0x00000001,
70
+
.val = 0x1,
71
+
};
72
+
73
+
static struct spear_pmx_mode *spear320_pmx_modes[] = {
74
+
&pmx_mode_auto_net_smii,
75
+
&pmx_mode_auto_net_mii,
76
+
&pmx_mode_auto_exp,
77
+
&pmx_mode_small_printers,
78
+
&pmx_mode_extended,
79
+
};
80
+
81
+
/* Extended mode registers and their offsets */
82
+
#define EXT_CTRL_REG 0x0018
83
+
#define MII_MDIO_MASK (1 << 4)
84
+
#define MII_MDIO_10_11_VAL 0
85
+
#define MII_MDIO_81_VAL (1 << 4)
86
+
#define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
87
+
#define MAC_MODE_MII 0
88
+
#define MAC_MODE_RMII 1
89
+
#define MAC_MODE_SMII 2
90
+
#define MAC_MODE_SS_SMII 3
91
+
#define MAC_MODE_MASK 0x3
92
+
#define MAC1_MODE_SHIFT 16
93
+
#define MAC2_MODE_SHIFT 18
94
+
95
+
#define IP_SEL_PAD_0_9_REG 0x00A4
96
+
#define PMX_PL_0_1_MASK (0x3F << 0)
97
+
#define PMX_UART2_PL_0_1_VAL 0x0
98
+
#define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
99
+
100
+
#define PMX_PL_2_3_MASK (0x3F << 6)
101
+
#define PMX_I2C2_PL_2_3_VAL 0x0
102
+
#define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
103
+
#define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
104
+
105
+
#define PMX_PL_4_5_MASK (0x3F << 12)
106
+
#define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
107
+
#define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
108
+
#define PMX_PL_5_MASK (0x7 << 15)
109
+
#define PMX_TOUCH_Y_PL_5_VAL 0x0
110
+
111
+
#define PMX_PL_6_7_MASK (0x3F << 18)
112
+
#define PMX_PL_6_MASK (0x7 << 18)
113
+
#define PMX_PL_7_MASK (0x7 << 21)
114
+
#define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
115
+
#define PMX_PWM_3_PL_6_VAL (0x2 << 18)
116
+
#define PMX_PWM_2_PL_7_VAL (0x2 << 21)
117
+
#define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
118
+
119
+
#define PMX_PL_8_9_MASK (0x3F << 24)
120
+
#define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
121
+
#define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
122
+
#define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
123
+
124
+
#define IP_SEL_PAD_10_19_REG 0x00A8
125
+
#define PMX_PL_10_11_MASK (0x3F << 0)
126
+
#define PMX_SMII_PL_10_11_VAL 0
127
+
#define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
128
+
129
+
#define PMX_PL_12_MASK (0x7 << 6)
130
+
#define PMX_PWM3_PL_12_VAL 0
131
+
#define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
132
+
133
+
#define PMX_PL_13_14_MASK (0x3F << 9)
134
+
#define PMX_PL_13_MASK (0x7 << 9)
135
+
#define PMX_PL_14_MASK (0x7 << 12)
136
+
#define PMX_SSP2_PL_13_14_15_16_VAL 0
137
+
#define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
138
+
#define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
139
+
#define PMX_PWM2_PL_13_VAL (0x2 << 9)
140
+
#define PMX_PWM1_PL_14_VAL (0x2 << 12)
141
+
142
+
#define PMX_PL_15_MASK (0x7 << 15)
143
+
#define PMX_PWM0_PL_15_VAL (0x2 << 15)
144
+
#define PMX_PL_15_16_MASK (0x3F << 15)
145
+
#define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
146
+
#define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
147
+
148
+
#define PMX_PL_17_18_MASK (0x3F << 21)
149
+
#define PMX_SSP1_PL_17_18_19_20_VAL 0
150
+
#define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
151
+
152
+
#define PMX_PL_19_MASK (0x7 << 27)
153
+
#define PMX_I2C2_PL_19_VAL (0x1 << 27)
154
+
#define PMX_RMII_PL_19_VAL (0x4 << 27)
155
+
156
+
#define IP_SEL_PAD_20_29_REG 0x00AC
157
+
#define PMX_PL_20_MASK (0x7 << 0)
158
+
#define PMX_I2C2_PL_20_VAL (0x1 << 0)
159
+
#define PMX_RMII_PL_20_VAL (0x4 << 0)
160
+
161
+
#define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
162
+
#define PMX_SMII_PL_21_TO_27_VAL 0
163
+
#define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
164
+
165
+
#define PMX_PL_28_29_MASK (0x3F << 24)
166
+
#define PMX_PL_28_MASK (0x7 << 24)
167
+
#define PMX_PL_29_MASK (0x7 << 27)
168
+
#define PMX_UART1_PL_28_29_VAL 0
169
+
#define PMX_PWM_3_PL_28_VAL (0x4 << 24)
170
+
#define PMX_PWM_2_PL_29_VAL (0x4 << 27)
171
+
172
+
#define IP_SEL_PAD_30_39_REG 0x00B0
173
+
#define PMX_PL_30_31_MASK (0x3F << 0)
174
+
#define PMX_CAN1_PL_30_31_VAL (0)
175
+
#define PMX_PL_30_MASK (0x7 << 0)
176
+
#define PMX_PL_31_MASK (0x7 << 3)
177
+
#define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
178
+
#define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
179
+
#define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
180
+
181
+
#define PMX_PL_32_33_MASK (0x3F << 6)
182
+
#define PMX_CAN0_PL_32_33_VAL 0
183
+
#define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
184
+
#define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
185
+
186
+
#define PMX_PL_34_MASK (0x7 << 12)
187
+
#define PMX_PWM2_PL_34_VAL 0
188
+
#define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
189
+
#define PMX_SSP2_PL_34_VAL (0x4 << 12)
190
+
191
+
#define PMX_PL_35_MASK (0x7 << 15)
192
+
#define PMX_I2S_REF_CLK_PL_35_VAL 0
193
+
#define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
194
+
#define PMX_SSP2_PL_35_VAL (0x4 << 15)
195
+
196
+
#define PMX_PL_36_MASK (0x7 << 18)
197
+
#define PMX_TOUCH_X_PL_36_VAL 0
198
+
#define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
199
+
#define PMX_SSP1_PL_36_VAL (0x4 << 18)
200
+
201
+
#define PMX_PL_37_38_MASK (0x3F << 21)
202
+
#define PMX_PWM0_1_PL_37_38_VAL 0
203
+
#define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
204
+
#define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
205
+
206
+
#define PMX_PL_39_MASK (0x7 << 27)
207
+
#define PMX_I2S_PL_39_VAL 0
208
+
#define PMX_UART4_PL_39_VAL (0x2 << 27)
209
+
#define PMX_SSP1_PL_39_VAL (0x4 << 27)
210
+
211
+
#define IP_SEL_PAD_40_49_REG 0x00B4
212
+
#define PMX_PL_40_MASK (0x7 << 0)
213
+
#define PMX_I2S_PL_40_VAL 0
214
+
#define PMX_UART4_PL_40_VAL (0x2 << 0)
215
+
#define PMX_PWM3_PL_40_VAL (0x4 << 0)
216
+
217
+
#define PMX_PL_41_42_MASK (0x3F << 3)
218
+
#define PMX_PL_41_MASK (0x7 << 3)
219
+
#define PMX_PL_42_MASK (0x7 << 6)
220
+
#define PMX_I2S_PL_41_42_VAL 0
221
+
#define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
222
+
#define PMX_PWM2_PL_41_VAL (0x4 << 3)
223
+
#define PMX_PWM1_PL_42_VAL (0x4 << 6)
224
+
225
+
#define PMX_PL_43_MASK (0x7 << 9)
226
+
#define PMX_SDHCI_PL_43_VAL 0
227
+
#define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
228
+
#define PMX_PWM0_PL_43_VAL (0x4 << 9)
229
+
230
+
#define PMX_PL_44_45_MASK (0x3F << 12)
231
+
#define PMX_SDHCI_PL_44_45_VAL 0
232
+
#define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
233
+
#define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
234
+
235
+
#define PMX_PL_46_47_MASK (0x3F << 18)
236
+
#define PMX_SDHCI_PL_46_47_VAL 0
237
+
#define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
238
+
#define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
239
+
240
+
#define PMX_PL_48_49_MASK (0x3F << 24)
241
+
#define PMX_SDHCI_PL_48_49_VAL 0
242
+
#define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
243
+
#define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
244
+
245
+
#define IP_SEL_PAD_50_59_REG 0x00B8
246
+
#define PMX_PL_50_51_MASK (0x3F << 0)
247
+
#define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
248
+
#define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
249
+
#define PMX_PL_50_MASK (0x7 << 0)
250
+
#define PMX_PL_51_MASK (0x7 << 3)
251
+
#define PMX_SDHCI_PL_50_VAL 0
252
+
#define PMX_SDHCI_CD_PL_51_VAL 0
253
+
254
+
#define PMX_PL_52_53_MASK (0x3F << 6)
255
+
#define PMX_FSMC_PL_52_53_VAL 0
256
+
#define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
257
+
#define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
258
+
259
+
#define PMX_PL_54_55_56_MASK (0x1FF << 12)
260
+
#define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
261
+
262
+
#define PMX_PL_57_MASK (0x7 << 21)
263
+
#define PMX_FSMC_PL_57_VAL 0
264
+
#define PMX_PWM3_PL_57_VAL (0x4 << 21)
265
+
266
+
#define PMX_PL_58_59_MASK (0x3F << 24)
267
+
#define PMX_PL_58_MASK (0x7 << 24)
268
+
#define PMX_PL_59_MASK (0x7 << 27)
269
+
#define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
270
+
#define PMX_PWM2_PL_58_VAL (0x4 << 24)
271
+
#define PMX_PWM1_PL_59_VAL (0x4 << 27)
272
+
273
+
#define IP_SEL_PAD_60_69_REG 0x00BC
274
+
#define PMX_PL_60_MASK (0x7 << 0)
275
+
#define PMX_FSMC_PL_60_VAL 0
276
+
#define PMX_PWM0_PL_60_VAL (0x4 << 0)
277
+
278
+
#define PMX_PL_61_TO_64_MASK (0xFFF << 3)
279
+
#define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
280
+
#define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
281
+
282
+
#define PMX_PL_65_TO_68_MASK (0xFFF << 15)
283
+
#define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
284
+
#define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
285
+
286
+
#define PMX_PL_69_MASK (0x7 << 27)
287
+
#define PMX_CLCD_PL_69_VAL (0)
288
+
#define PMX_EMI_PL_69_VAL (0x2 << 27)
289
+
#define PMX_SPP_PL_69_VAL (0x3 << 27)
290
+
#define PMX_UART5_PL_69_VAL (0x4 << 27)
291
+
292
+
#define IP_SEL_PAD_70_79_REG 0x00C0
293
+
#define PMX_PL_70_MASK (0x7 << 0)
294
+
#define PMX_CLCD_PL_70_VAL (0)
295
+
#define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
296
+
#define PMX_SPP_PL_70_VAL (0x3 << 0)
297
+
#define PMX_UART5_PL_70_VAL (0x4 << 0)
298
+
299
+
#define PMX_PL_71_72_MASK (0x3F << 3)
300
+
#define PMX_CLCD_PL_71_72_VAL (0)
301
+
#define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
302
+
#define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
303
+
#define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
304
+
305
+
#define PMX_PL_73_MASK (0x7 << 9)
306
+
#define PMX_CLCD_PL_73_VAL (0)
307
+
#define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
308
+
#define PMX_SPP_PL_73_VAL (0x3 << 9)
309
+
#define PMX_UART3_PL_73_VAL (0x4 << 9)
310
+
311
+
#define PMX_PL_74_MASK (0x7 << 12)
312
+
#define PMX_CLCD_PL_74_VAL (0)
313
+
#define PMX_EMI_PL_74_VAL (0x2 << 12)
314
+
#define PMX_SPP_PL_74_VAL (0x3 << 12)
315
+
#define PMX_UART3_PL_74_VAL (0x4 << 12)
316
+
317
+
#define PMX_PL_75_76_MASK (0x3F << 15)
318
+
#define PMX_CLCD_PL_75_76_VAL (0)
319
+
#define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
320
+
#define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
321
+
#define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
322
+
323
+
#define PMX_PL_77_78_79_MASK (0x1FF << 21)
324
+
#define PMX_CLCD_PL_77_78_79_VAL (0)
325
+
#define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
326
+
#define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
327
+
#define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
328
+
329
+
#define IP_SEL_PAD_80_89_REG 0x00C4
330
+
#define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
331
+
#define PMX_CLCD_PL_80_TO_85_VAL 0
332
+
#define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
333
+
#define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
334
+
#define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
335
+
#define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
336
+
337
+
#define PMX_PL_86_87_MASK (0x3F << 18)
338
+
#define PMX_PL_86_MASK (0x7 << 18)
339
+
#define PMX_PL_87_MASK (0x7 << 21)
340
+
#define PMX_CLCD_PL_86_87_VAL 0
341
+
#define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
342
+
#define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
343
+
#define PMX_PWM3_PL_86_VAL (0x4 << 18)
344
+
#define PMX_PWM2_PL_87_VAL (0x4 << 21)
345
+
346
+
#define PMX_PL_88_89_MASK (0x3F << 24)
347
+
#define PMX_CLCD_PL_88_89_VAL 0
348
+
#define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
349
+
#define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
350
+
#define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
351
+
#define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
352
+
353
+
#define IP_SEL_PAD_90_99_REG 0x00C8
354
+
#define PMX_PL_90_91_MASK (0x3F << 0)
355
+
#define PMX_CLCD_PL_90_91_VAL 0
356
+
#define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
357
+
#define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
358
+
#define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
359
+
#define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
360
+
361
+
#define PMX_PL_92_93_MASK (0x3F << 6)
362
+
#define PMX_CLCD_PL_92_93_VAL 0
363
+
#define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
364
+
#define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
365
+
#define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
366
+
#define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
367
+
368
+
#define PMX_PL_94_95_MASK (0x3F << 12)
369
+
#define PMX_CLCD_PL_94_95_VAL 0
370
+
#define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
371
+
#define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
372
+
#define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
373
+
#define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
374
+
375
+
#define PMX_PL_96_97_MASK (0x3F << 18)
376
+
#define PMX_CLCD_PL_96_97_VAL 0
377
+
#define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
378
+
#define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
379
+
#define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
380
+
#define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
381
+
382
+
#define PMX_PL_98_MASK (0x7 << 24)
383
+
#define PMX_CLCD_PL_98_VAL 0
384
+
#define PMX_I2C1_PL_98_VAL (0x2 << 24)
385
+
#define PMX_UART3_PL_98_VAL (0x4 << 24)
386
+
387
+
#define PMX_PL_99_MASK (0x7 << 27)
388
+
#define PMX_SDHCI_PL_99_VAL 0
389
+
#define PMX_I2C1_PL_99_VAL (0x2 << 27)
390
+
#define PMX_UART3_PL_99_VAL (0x4 << 27)
391
+
392
+
#define IP_SEL_MIX_PAD_REG 0x00CC
393
+
#define PMX_PL_100_101_MASK (0x3F << 0)
394
+
#define PMX_SDHCI_PL_100_101_VAL 0
395
+
#define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
396
+
397
+
#define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
398
+
#define PMX_SSP1_PORT_94_TO_97_VAL 0
399
+
#define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
400
+
#define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
401
+
#define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
402
+
#define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
403
+
404
+
#define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
405
+
#define PMX_SSP2_PORT_90_TO_93_VAL 0
406
+
#define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
407
+
#define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
408
+
#define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
409
+
#define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
410
+
411
+
#define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
412
+
#define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
413
+
#define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
414
+
#define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
415
+
#define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
416
+
417
+
#define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
418
+
#define PMX_UART3_PORT_94_VAL 0
419
+
#define PMX_UART3_PORT_73_VAL (0x1 << 16)
420
+
#define PMX_UART3_PORT_52_VAL (0x2 << 16)
421
+
#define PMX_UART3_PORT_41_VAL (0x3 << 16)
422
+
#define PMX_UART3_PORT_15_VAL (0x4 << 16)
423
+
#define PMX_UART3_PORT_8_VAL (0x5 << 16)
424
+
#define PMX_UART3_PORT_99_VAL (0x6 << 16)
425
+
426
+
#define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
427
+
#define PMX_UART4_PORT_92_VAL 0
428
+
#define PMX_UART4_PORT_71_VAL (0x1 << 19)
429
+
#define PMX_UART4_PORT_39_VAL (0x2 << 19)
430
+
#define PMX_UART4_PORT_13_VAL (0x3 << 19)
431
+
#define PMX_UART4_PORT_6_VAL (0x4 << 19)
432
+
#define PMX_UART4_PORT_101_VAL (0x5 << 19)
433
+
434
+
#define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
435
+
#define PMX_UART5_PORT_90_VAL 0
436
+
#define PMX_UART5_PORT_69_VAL (0x1 << 22)
437
+
#define PMX_UART5_PORT_37_VAL (0x2 << 22)
438
+
#define PMX_UART5_PORT_4_VAL (0x3 << 22)
439
+
440
+
#define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
441
+
#define PMX_UART6_PORT_88_VAL 0
442
+
#define PMX_UART6_PORT_2_VAL (0x1 << 24)
443
+
444
+
#define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
445
+
#define PMX_I2C1_PORT_8_9_VAL 0
446
+
#define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
447
+
448
+
#define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
449
+
#define PMX_I2C2_PORT_96_97_VAL 0
450
+
#define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
451
+
#define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
452
+
#define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
453
+
#define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
454
+
455
+
#define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
456
+
#define PMX_SDHCI_CD_PORT_12_VAL 0
457
+
#define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
458
+
459
+
/* Pad multiplexing for CLCD device */
460
+
static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
461
+
79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
462
+
97 };
463
+
static struct spear_muxreg clcd_muxreg[] = {
464
+
{
465
+
.reg = IP_SEL_PAD_60_69_REG,
466
+
.mask = PMX_PL_69_MASK,
467
+
.val = PMX_CLCD_PL_69_VAL,
468
+
}, {
469
+
.reg = IP_SEL_PAD_70_79_REG,
470
+
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
471
+
PMX_PL_74_MASK | PMX_PL_75_76_MASK |
472
+
PMX_PL_77_78_79_MASK,
473
+
.val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
474
+
PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
475
+
PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
476
+
}, {
477
+
.reg = IP_SEL_PAD_80_89_REG,
478
+
.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
479
+
PMX_PL_88_89_MASK,
480
+
.val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
481
+
PMX_CLCD_PL_88_89_VAL,
482
+
}, {
483
+
.reg = IP_SEL_PAD_90_99_REG,
484
+
.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
485
+
PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
486
+
.val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
487
+
PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
488
+
PMX_CLCD_PL_98_VAL,
489
+
},
490
+
};
491
+
492
+
static struct spear_modemux clcd_modemux[] = {
493
+
{
494
+
.modes = EXTENDED_MODE,
495
+
.muxregs = clcd_muxreg,
496
+
.nmuxregs = ARRAY_SIZE(clcd_muxreg),
497
+
},
498
+
};
499
+
500
+
static struct spear_pingroup clcd_pingroup = {
501
+
.name = "clcd_grp",
502
+
.pins = clcd_pins,
503
+
.npins = ARRAY_SIZE(clcd_pins),
504
+
.modemuxs = clcd_modemux,
505
+
.nmodemuxs = ARRAY_SIZE(clcd_modemux),
506
+
};
507
+
508
+
static const char *const clcd_grps[] = { "clcd_grp" };
509
+
static struct spear_function clcd_function = {
510
+
.name = "clcd",
511
+
.groups = clcd_grps,
512
+
.ngroups = ARRAY_SIZE(clcd_grps),
513
+
};
514
+
515
+
/* Pad multiplexing for EMI (Parallel NOR flash) device */
516
+
static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
517
+
57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
518
+
75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
519
+
93, 94, 95, 96, 97 };
520
+
static struct spear_muxreg emi_muxreg[] = {
521
+
{
522
+
.reg = PMX_CONFIG_REG,
523
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
524
+
.val = 0,
525
+
},
526
+
};
527
+
528
+
static struct spear_muxreg emi_ext_muxreg[] = {
529
+
{
530
+
.reg = IP_SEL_PAD_40_49_REG,
531
+
.mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
532
+
.val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
533
+
}, {
534
+
.reg = IP_SEL_PAD_50_59_REG,
535
+
.mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
536
+
PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
537
+
.val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
538
+
PMX_FSMC_EMI_PL_54_55_56_VAL |
539
+
PMX_FSMC_EMI_PL_58_59_VAL,
540
+
}, {
541
+
.reg = IP_SEL_PAD_60_69_REG,
542
+
.mask = PMX_PL_69_MASK,
543
+
.val = PMX_EMI_PL_69_VAL,
544
+
}, {
545
+
.reg = IP_SEL_PAD_70_79_REG,
546
+
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
547
+
PMX_PL_74_MASK | PMX_PL_75_76_MASK |
548
+
PMX_PL_77_78_79_MASK,
549
+
.val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
550
+
PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
551
+
PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
552
+
}, {
553
+
.reg = IP_SEL_PAD_80_89_REG,
554
+
.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
555
+
PMX_PL_88_89_MASK,
556
+
.val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
557
+
PMX_EMI_PL_88_89_VAL,
558
+
}, {
559
+
.reg = IP_SEL_PAD_90_99_REG,
560
+
.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
561
+
PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
562
+
.val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
563
+
PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
564
+
}, {
565
+
.reg = EXT_CTRL_REG,
566
+
.mask = EMI_FSMC_DYNAMIC_MUX_MASK,
567
+
.val = EMI_FSMC_DYNAMIC_MUX_MASK,
568
+
},
569
+
};
570
+
571
+
static struct spear_modemux emi_modemux[] = {
572
+
{
573
+
.modes = AUTO_EXP_MODE | EXTENDED_MODE,
574
+
.muxregs = emi_muxreg,
575
+
.nmuxregs = ARRAY_SIZE(emi_muxreg),
576
+
}, {
577
+
.modes = EXTENDED_MODE,
578
+
.muxregs = emi_ext_muxreg,
579
+
.nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
580
+
},
581
+
};
582
+
583
+
static struct spear_pingroup emi_pingroup = {
584
+
.name = "emi_grp",
585
+
.pins = emi_pins,
586
+
.npins = ARRAY_SIZE(emi_pins),
587
+
.modemuxs = emi_modemux,
588
+
.nmodemuxs = ARRAY_SIZE(emi_modemux),
589
+
};
590
+
591
+
static const char *const emi_grps[] = { "emi_grp" };
592
+
static struct spear_function emi_function = {
593
+
.name = "emi",
594
+
.groups = emi_grps,
595
+
.ngroups = ARRAY_SIZE(emi_grps),
596
+
};
597
+
598
+
/* Pad multiplexing for FSMC (NAND flash) device */
599
+
static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
600
+
61, 62, 63, 64, 65, 66, 67, 68 };
601
+
static struct spear_muxreg fsmc_8bit_muxreg[] = {
602
+
{
603
+
.reg = IP_SEL_PAD_50_59_REG,
604
+
.mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
605
+
PMX_PL_57_MASK | PMX_PL_58_59_MASK,
606
+
.val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
607
+
PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
608
+
}, {
609
+
.reg = IP_SEL_PAD_60_69_REG,
610
+
.mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
611
+
PMX_PL_65_TO_68_MASK,
612
+
.val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
613
+
PMX_FSMC_PL_65_TO_68_VAL,
614
+
}, {
615
+
.reg = EXT_CTRL_REG,
616
+
.mask = EMI_FSMC_DYNAMIC_MUX_MASK,
617
+
.val = EMI_FSMC_DYNAMIC_MUX_MASK,
618
+
},
619
+
};
620
+
621
+
static struct spear_modemux fsmc_8bit_modemux[] = {
622
+
{
623
+
.modes = EXTENDED_MODE,
624
+
.muxregs = fsmc_8bit_muxreg,
625
+
.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
626
+
},
627
+
};
628
+
629
+
static struct spear_pingroup fsmc_8bit_pingroup = {
630
+
.name = "fsmc_8bit_grp",
631
+
.pins = fsmc_8bit_pins,
632
+
.npins = ARRAY_SIZE(fsmc_8bit_pins),
633
+
.modemuxs = fsmc_8bit_modemux,
634
+
.nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
635
+
};
636
+
637
+
static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
638
+
57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
639
+
static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
640
+
{
641
+
.reg = PMX_CONFIG_REG,
642
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
643
+
.val = 0,
644
+
},
645
+
};
646
+
647
+
static struct spear_muxreg fsmc_16bit_muxreg[] = {
648
+
{
649
+
.reg = IP_SEL_PAD_40_49_REG,
650
+
.mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
651
+
.val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
652
+
}, {
653
+
.reg = IP_SEL_PAD_70_79_REG,
654
+
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
655
+
.val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
656
+
PMX_FSMC_EMI_PL_73_VAL,
657
+
}
658
+
};
659
+
660
+
static struct spear_modemux fsmc_16bit_modemux[] = {
661
+
{
662
+
.modes = EXTENDED_MODE,
663
+
.muxregs = fsmc_8bit_muxreg,
664
+
.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
665
+
}, {
666
+
.modes = AUTO_EXP_MODE | EXTENDED_MODE,
667
+
.muxregs = fsmc_16bit_autoexp_muxreg,
668
+
.nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
669
+
}, {
670
+
.modes = EXTENDED_MODE,
671
+
.muxregs = fsmc_16bit_muxreg,
672
+
.nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
673
+
},
674
+
};
675
+
676
+
static struct spear_pingroup fsmc_16bit_pingroup = {
677
+
.name = "fsmc_16bit_grp",
678
+
.pins = fsmc_16bit_pins,
679
+
.npins = ARRAY_SIZE(fsmc_16bit_pins),
680
+
.modemuxs = fsmc_16bit_modemux,
681
+
.nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
682
+
};
683
+
684
+
static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
685
+
static struct spear_function fsmc_function = {
686
+
.name = "fsmc",
687
+
.groups = fsmc_grps,
688
+
.ngroups = ARRAY_SIZE(fsmc_grps),
689
+
};
690
+
691
+
/* Pad multiplexing for SPP device */
692
+
static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
693
+
80, 81, 82, 83, 84, 85 };
694
+
static struct spear_muxreg spp_muxreg[] = {
695
+
{
696
+
.reg = IP_SEL_PAD_60_69_REG,
697
+
.mask = PMX_PL_69_MASK,
698
+
.val = PMX_SPP_PL_69_VAL,
699
+
}, {
700
+
.reg = IP_SEL_PAD_70_79_REG,
701
+
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
702
+
PMX_PL_74_MASK | PMX_PL_75_76_MASK |
703
+
PMX_PL_77_78_79_MASK,
704
+
.val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
705
+
PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
706
+
PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
707
+
}, {
708
+
.reg = IP_SEL_PAD_80_89_REG,
709
+
.mask = PMX_PL_80_TO_85_MASK,
710
+
.val = PMX_SPP_PL_80_TO_85_VAL,
711
+
},
712
+
};
713
+
714
+
static struct spear_modemux spp_modemux[] = {
715
+
{
716
+
.modes = EXTENDED_MODE,
717
+
.muxregs = spp_muxreg,
718
+
.nmuxregs = ARRAY_SIZE(spp_muxreg),
719
+
},
720
+
};
721
+
722
+
static struct spear_pingroup spp_pingroup = {
723
+
.name = "spp_grp",
724
+
.pins = spp_pins,
725
+
.npins = ARRAY_SIZE(spp_pins),
726
+
.modemuxs = spp_modemux,
727
+
.nmodemuxs = ARRAY_SIZE(spp_modemux),
728
+
};
729
+
730
+
static const char *const spp_grps[] = { "spp_grp" };
731
+
static struct spear_function spp_function = {
732
+
.name = "spp",
733
+
.groups = spp_grps,
734
+
.ngroups = ARRAY_SIZE(spp_grps),
735
+
};
736
+
737
+
/* Pad multiplexing for SDHCI device */
738
+
static const unsigned sdhci_led_pins[] = { 34 };
739
+
static struct spear_muxreg sdhci_led_muxreg[] = {
740
+
{
741
+
.reg = PMX_CONFIG_REG,
742
+
.mask = PMX_SSP_CS_MASK,
743
+
.val = 0,
744
+
},
745
+
};
746
+
747
+
static struct spear_muxreg sdhci_led_ext_muxreg[] = {
748
+
{
749
+
.reg = IP_SEL_PAD_30_39_REG,
750
+
.mask = PMX_PL_34_MASK,
751
+
.val = PMX_PWM2_PL_34_VAL,
752
+
},
753
+
};
754
+
755
+
static struct spear_modemux sdhci_led_modemux[] = {
756
+
{
757
+
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
758
+
.muxregs = sdhci_led_muxreg,
759
+
.nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
760
+
}, {
761
+
.modes = EXTENDED_MODE,
762
+
.muxregs = sdhci_led_ext_muxreg,
763
+
.nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
764
+
},
765
+
};
766
+
767
+
static struct spear_pingroup sdhci_led_pingroup = {
768
+
.name = "sdhci_led_grp",
769
+
.pins = sdhci_led_pins,
770
+
.npins = ARRAY_SIZE(sdhci_led_pins),
771
+
.modemuxs = sdhci_led_modemux,
772
+
.nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
773
+
};
774
+
775
+
static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
776
+
50};
777
+
static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
778
+
};
779
+
static struct spear_muxreg sdhci_muxreg[] = {
780
+
{
781
+
.reg = PMX_CONFIG_REG,
782
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
783
+
.val = 0,
784
+
},
785
+
};
786
+
787
+
static struct spear_muxreg sdhci_ext_muxreg[] = {
788
+
{
789
+
.reg = IP_SEL_PAD_40_49_REG,
790
+
.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
791
+
PMX_PL_48_49_MASK,
792
+
.val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
793
+
PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
794
+
}, {
795
+
.reg = IP_SEL_PAD_50_59_REG,
796
+
.mask = PMX_PL_50_MASK,
797
+
.val = PMX_SDHCI_PL_50_VAL,
798
+
}, {
799
+
.reg = IP_SEL_PAD_90_99_REG,
800
+
.mask = PMX_PL_99_MASK,
801
+
.val = PMX_SDHCI_PL_99_VAL,
802
+
}, {
803
+
.reg = IP_SEL_MIX_PAD_REG,
804
+
.mask = PMX_PL_100_101_MASK,
805
+
.val = PMX_SDHCI_PL_100_101_VAL,
806
+
},
807
+
};
808
+
809
+
static struct spear_muxreg sdhci_cd_12_muxreg[] = {
810
+
{
811
+
.reg = PMX_CONFIG_REG,
812
+
.mask = PMX_MII_MASK,
813
+
.val = 0,
814
+
}, {
815
+
.reg = IP_SEL_PAD_10_19_REG,
816
+
.mask = PMX_PL_12_MASK,
817
+
.val = PMX_SDHCI_CD_PL_12_VAL,
818
+
}, {
819
+
.reg = IP_SEL_MIX_PAD_REG,
820
+
.mask = PMX_SDHCI_CD_PORT_SEL_MASK,
821
+
.val = PMX_SDHCI_CD_PORT_12_VAL,
822
+
},
823
+
};
824
+
825
+
static struct spear_muxreg sdhci_cd_51_muxreg[] = {
826
+
{
827
+
.reg = IP_SEL_PAD_50_59_REG,
828
+
.mask = PMX_PL_51_MASK,
829
+
.val = PMX_SDHCI_CD_PL_51_VAL,
830
+
}, {
831
+
.reg = IP_SEL_MIX_PAD_REG,
832
+
.mask = PMX_SDHCI_CD_PORT_SEL_MASK,
833
+
.val = PMX_SDHCI_CD_PORT_51_VAL,
834
+
},
835
+
};
836
+
837
+
#define pmx_sdhci_common_modemux \
838
+
{ \
839
+
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
840
+
SMALL_PRINTERS_MODE | EXTENDED_MODE, \
841
+
.muxregs = sdhci_muxreg, \
842
+
.nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
843
+
}, { \
844
+
.modes = EXTENDED_MODE, \
845
+
.muxregs = sdhci_ext_muxreg, \
846
+
.nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
847
+
}
848
+
849
+
static struct spear_modemux sdhci_modemux[][3] = {
850
+
{
851
+
/* select pin 12 for cd */
852
+
pmx_sdhci_common_modemux,
853
+
{
854
+
.modes = EXTENDED_MODE,
855
+
.muxregs = sdhci_cd_12_muxreg,
856
+
.nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
857
+
},
858
+
}, {
859
+
/* select pin 51 for cd */
860
+
pmx_sdhci_common_modemux,
861
+
{
862
+
.modes = EXTENDED_MODE,
863
+
.muxregs = sdhci_cd_51_muxreg,
864
+
.nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
865
+
},
866
+
}
867
+
};
868
+
869
+
static struct spear_pingroup sdhci_pingroup[] = {
870
+
{
871
+
.name = "sdhci_cd_12_grp",
872
+
.pins = sdhci_cd_12_pins,
873
+
.npins = ARRAY_SIZE(sdhci_cd_12_pins),
874
+
.modemuxs = sdhci_modemux[0],
875
+
.nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
876
+
}, {
877
+
.name = "sdhci_cd_51_grp",
878
+
.pins = sdhci_cd_51_pins,
879
+
.npins = ARRAY_SIZE(sdhci_cd_51_pins),
880
+
.modemuxs = sdhci_modemux[1],
881
+
.nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
882
+
},
883
+
};
884
+
885
+
static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
886
+
"sdhci_led_grp" };
887
+
888
+
static struct spear_function sdhci_function = {
889
+
.name = "sdhci",
890
+
.groups = sdhci_grps,
891
+
.ngroups = ARRAY_SIZE(sdhci_grps),
892
+
};
893
+
894
+
/* Pad multiplexing for I2S device */
895
+
static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
896
+
static struct spear_muxreg i2s_muxreg[] = {
897
+
{
898
+
.reg = PMX_CONFIG_REG,
899
+
.mask = PMX_SSP_CS_MASK,
900
+
.val = 0,
901
+
}, {
902
+
.reg = PMX_CONFIG_REG,
903
+
.mask = PMX_UART0_MODEM_MASK,
904
+
.val = 0,
905
+
},
906
+
};
907
+
908
+
static struct spear_muxreg i2s_ext_muxreg[] = {
909
+
{
910
+
.reg = IP_SEL_PAD_30_39_REG,
911
+
.mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
912
+
.val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
913
+
}, {
914
+
.reg = IP_SEL_PAD_40_49_REG,
915
+
.mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
916
+
.val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
917
+
},
918
+
};
919
+
920
+
static struct spear_modemux i2s_modemux[] = {
921
+
{
922
+
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
923
+
.muxregs = i2s_muxreg,
924
+
.nmuxregs = ARRAY_SIZE(i2s_muxreg),
925
+
}, {
926
+
.modes = EXTENDED_MODE,
927
+
.muxregs = i2s_ext_muxreg,
928
+
.nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
929
+
},
930
+
};
931
+
932
+
static struct spear_pingroup i2s_pingroup = {
933
+
.name = "i2s_grp",
934
+
.pins = i2s_pins,
935
+
.npins = ARRAY_SIZE(i2s_pins),
936
+
.modemuxs = i2s_modemux,
937
+
.nmodemuxs = ARRAY_SIZE(i2s_modemux),
938
+
};
939
+
940
+
static const char *const i2s_grps[] = { "i2s_grp" };
941
+
static struct spear_function i2s_function = {
942
+
.name = "i2s",
943
+
.groups = i2s_grps,
944
+
.ngroups = ARRAY_SIZE(i2s_grps),
945
+
};
946
+
947
+
/* Pad multiplexing for UART1 device */
948
+
static const unsigned uart1_pins[] = { 28, 29 };
949
+
static struct spear_muxreg uart1_muxreg[] = {
950
+
{
951
+
.reg = PMX_CONFIG_REG,
952
+
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
953
+
.val = 0,
954
+
},
955
+
};
956
+
957
+
static struct spear_muxreg uart1_ext_muxreg[] = {
958
+
{
959
+
.reg = IP_SEL_PAD_20_29_REG,
960
+
.mask = PMX_PL_28_29_MASK,
961
+
.val = PMX_UART1_PL_28_29_VAL,
962
+
},
963
+
};
964
+
965
+
static struct spear_modemux uart1_modemux[] = {
966
+
{
967
+
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
968
+
| SMALL_PRINTERS_MODE | EXTENDED_MODE,
969
+
.muxregs = uart1_muxreg,
970
+
.nmuxregs = ARRAY_SIZE(uart1_muxreg),
971
+
}, {
972
+
.modes = EXTENDED_MODE,
973
+
.muxregs = uart1_ext_muxreg,
974
+
.nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
975
+
},
976
+
};
977
+
978
+
static struct spear_pingroup uart1_pingroup = {
979
+
.name = "uart1_grp",
980
+
.pins = uart1_pins,
981
+
.npins = ARRAY_SIZE(uart1_pins),
982
+
.modemuxs = uart1_modemux,
983
+
.nmodemuxs = ARRAY_SIZE(uart1_modemux),
984
+
};
985
+
986
+
static const char *const uart1_grps[] = { "uart1_grp" };
987
+
static struct spear_function uart1_function = {
988
+
.name = "uart1",
989
+
.groups = uart1_grps,
990
+
.ngroups = ARRAY_SIZE(uart1_grps),
991
+
};
992
+
993
+
/* Pad multiplexing for UART1 Modem device */
994
+
static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
995
+
static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
996
+
static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
997
+
static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
998
+
999
+
static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
1000
+
{
1001
+
.reg = PMX_CONFIG_REG,
1002
+
.mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
1003
+
.val = 0,
1004
+
}, {
1005
+
.reg = IP_SEL_PAD_0_9_REG,
1006
+
.mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
1007
+
.val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
1008
+
PMX_UART1_ENH_PL_6_7_VAL,
1009
+
}, {
1010
+
.reg = IP_SEL_MIX_PAD_REG,
1011
+
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1012
+
.val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
1013
+
},
1014
+
};
1015
+
1016
+
static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
1017
+
{
1018
+
.reg = PMX_CONFIG_REG,
1019
+
.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
1020
+
PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
1021
+
.val = 0,
1022
+
},
1023
+
};
1024
+
1025
+
static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
1026
+
{
1027
+
.reg = IP_SEL_PAD_30_39_REG,
1028
+
.mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
1029
+
PMX_PL_35_MASK | PMX_PL_36_MASK,
1030
+
.val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
1031
+
PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1032
+
PMX_UART1_ENH_PL_36_VAL,
1033
+
}, {
1034
+
.reg = IP_SEL_MIX_PAD_REG,
1035
+
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1036
+
.val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
1037
+
},
1038
+
};
1039
+
1040
+
static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
1041
+
{
1042
+
.reg = PMX_CONFIG_REG,
1043
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
1044
+
PMX_SSP_CS_MASK,
1045
+
.val = 0,
1046
+
},
1047
+
};
1048
+
1049
+
static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
1050
+
{
1051
+
.reg = IP_SEL_PAD_30_39_REG,
1052
+
.mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
1053
+
.val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1054
+
PMX_UART1_ENH_PL_36_VAL,
1055
+
}, {
1056
+
.reg = IP_SEL_PAD_40_49_REG,
1057
+
.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1058
+
.val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1059
+
}, {
1060
+
.reg = IP_SEL_MIX_PAD_REG,
1061
+
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1062
+
.val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
1063
+
},
1064
+
};
1065
+
1066
+
static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
1067
+
{
1068
+
.reg = IP_SEL_PAD_80_89_REG,
1069
+
.mask = PMX_PL_80_TO_85_MASK,
1070
+
.val = PMX_UART1_ENH_PL_80_TO_85_VAL,
1071
+
}, {
1072
+
.reg = IP_SEL_PAD_40_49_REG,
1073
+
.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1074
+
.val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1075
+
}, {
1076
+
.reg = IP_SEL_MIX_PAD_REG,
1077
+
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1078
+
.val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
1079
+
},
1080
+
};
1081
+
1082
+
static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
1083
+
{
1084
+
.modes = EXTENDED_MODE,
1085
+
.muxregs = uart1_modem_ext_2_to_7_muxreg,
1086
+
.nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
1087
+
},
1088
+
};
1089
+
1090
+
static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
1091
+
{
1092
+
.modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
1093
+
.muxregs = uart1_modem_31_to_36_muxreg,
1094
+
.nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
1095
+
}, {
1096
+
.modes = EXTENDED_MODE,
1097
+
.muxregs = uart1_modem_ext_31_to_36_muxreg,
1098
+
.nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
1099
+
},
1100
+
};
1101
+
1102
+
static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
1103
+
{
1104
+
.modes = AUTO_EXP_MODE | EXTENDED_MODE,
1105
+
.muxregs = uart1_modem_34_to_45_muxreg,
1106
+
.nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
1107
+
}, {
1108
+
.modes = EXTENDED_MODE,
1109
+
.muxregs = uart1_modem_ext_34_to_45_muxreg,
1110
+
.nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
1111
+
},
1112
+
};
1113
+
1114
+
static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
1115
+
{
1116
+
.modes = EXTENDED_MODE,
1117
+
.muxregs = uart1_modem_ext_80_to_85_muxreg,
1118
+
.nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
1119
+
},
1120
+
};
1121
+
1122
+
static struct spear_pingroup uart1_modem_pingroup[] = {
1123
+
{
1124
+
.name = "uart1_modem_2_to_7_grp",
1125
+
.pins = uart1_modem_2_to_7_pins,
1126
+
.npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
1127
+
.modemuxs = uart1_modem_2_to_7_modemux,
1128
+
.nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
1129
+
}, {
1130
+
.name = "uart1_modem_31_to_36_grp",
1131
+
.pins = uart1_modem_31_to_36_pins,
1132
+
.npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
1133
+
.modemuxs = uart1_modem_31_to_36_modemux,
1134
+
.nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
1135
+
}, {
1136
+
.name = "uart1_modem_34_to_45_grp",
1137
+
.pins = uart1_modem_34_to_45_pins,
1138
+
.npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
1139
+
.modemuxs = uart1_modem_34_to_45_modemux,
1140
+
.nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
1141
+
}, {
1142
+
.name = "uart1_modem_80_to_85_grp",
1143
+
.pins = uart1_modem_80_to_85_pins,
1144
+
.npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
1145
+
.modemuxs = uart1_modem_80_to_85_modemux,
1146
+
.nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
1147
+
},
1148
+
};
1149
+
1150
+
static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
1151
+
"uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
1152
+
"uart1_modem_80_to_85_grp" };
1153
+
static struct spear_function uart1_modem_function = {
1154
+
.name = "uart1_modem",
1155
+
.groups = uart1_modem_grps,
1156
+
.ngroups = ARRAY_SIZE(uart1_modem_grps),
1157
+
};
1158
+
1159
+
/* Pad multiplexing for UART2 device */
1160
+
static const unsigned uart2_pins[] = { 0, 1 };
1161
+
static struct spear_muxreg uart2_muxreg[] = {
1162
+
{
1163
+
.reg = PMX_CONFIG_REG,
1164
+
.mask = PMX_FIRDA_MASK,
1165
+
.val = 0,
1166
+
},
1167
+
};
1168
+
1169
+
static struct spear_muxreg uart2_ext_muxreg[] = {
1170
+
{
1171
+
.reg = IP_SEL_PAD_0_9_REG,
1172
+
.mask = PMX_PL_0_1_MASK,
1173
+
.val = PMX_UART2_PL_0_1_VAL,
1174
+
},
1175
+
};
1176
+
1177
+
static struct spear_modemux uart2_modemux[] = {
1178
+
{
1179
+
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1180
+
| SMALL_PRINTERS_MODE | EXTENDED_MODE,
1181
+
.muxregs = uart2_muxreg,
1182
+
.nmuxregs = ARRAY_SIZE(uart2_muxreg),
1183
+
}, {
1184
+
.modes = EXTENDED_MODE,
1185
+
.muxregs = uart2_ext_muxreg,
1186
+
.nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
1187
+
},
1188
+
};
1189
+
1190
+
static struct spear_pingroup uart2_pingroup = {
1191
+
.name = "uart2_grp",
1192
+
.pins = uart2_pins,
1193
+
.npins = ARRAY_SIZE(uart2_pins),
1194
+
.modemuxs = uart2_modemux,
1195
+
.nmodemuxs = ARRAY_SIZE(uart2_modemux),
1196
+
};
1197
+
1198
+
static const char *const uart2_grps[] = { "uart2_grp" };
1199
+
static struct spear_function uart2_function = {
1200
+
.name = "uart2",
1201
+
.groups = uart2_grps,
1202
+
.ngroups = ARRAY_SIZE(uart2_grps),
1203
+
};
1204
+
1205
+
/* Pad multiplexing for uart3 device */
1206
+
static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
1207
+
{ 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
1208
+
1209
+
static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
1210
+
{
1211
+
.reg = PMX_CONFIG_REG,
1212
+
.mask = PMX_SSP_MASK,
1213
+
.val = 0,
1214
+
}, {
1215
+
.reg = IP_SEL_PAD_0_9_REG,
1216
+
.mask = PMX_PL_8_9_MASK,
1217
+
.val = PMX_UART3_PL_8_9_VAL,
1218
+
}, {
1219
+
.reg = IP_SEL_MIX_PAD_REG,
1220
+
.mask = PMX_UART3_PORT_SEL_MASK,
1221
+
.val = PMX_UART3_PORT_8_VAL,
1222
+
},
1223
+
};
1224
+
1225
+
static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
1226
+
{
1227
+
.reg = PMX_CONFIG_REG,
1228
+
.mask = PMX_MII_MASK,
1229
+
.val = 0,
1230
+
}, {
1231
+
.reg = IP_SEL_PAD_10_19_REG,
1232
+
.mask = PMX_PL_15_16_MASK,
1233
+
.val = PMX_UART3_PL_15_16_VAL,
1234
+
}, {
1235
+
.reg = IP_SEL_MIX_PAD_REG,
1236
+
.mask = PMX_UART3_PORT_SEL_MASK,
1237
+
.val = PMX_UART3_PORT_15_VAL,
1238
+
},
1239
+
};
1240
+
1241
+
static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
1242
+
{
1243
+
.reg = PMX_CONFIG_REG,
1244
+
.mask = PMX_UART0_MODEM_MASK,
1245
+
.val = 0,
1246
+
}, {
1247
+
.reg = IP_SEL_PAD_40_49_REG,
1248
+
.mask = PMX_PL_41_42_MASK,
1249
+
.val = PMX_UART3_PL_41_42_VAL,
1250
+
}, {
1251
+
.reg = IP_SEL_MIX_PAD_REG,
1252
+
.mask = PMX_UART3_PORT_SEL_MASK,
1253
+
.val = PMX_UART3_PORT_41_VAL,
1254
+
},
1255
+
};
1256
+
1257
+
static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
1258
+
{
1259
+
.reg = IP_SEL_PAD_50_59_REG,
1260
+
.mask = PMX_PL_52_53_MASK,
1261
+
.val = PMX_UART3_PL_52_53_VAL,
1262
+
}, {
1263
+
.reg = IP_SEL_MIX_PAD_REG,
1264
+
.mask = PMX_UART3_PORT_SEL_MASK,
1265
+
.val = PMX_UART3_PORT_52_VAL,
1266
+
},
1267
+
};
1268
+
1269
+
static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
1270
+
{
1271
+
.reg = IP_SEL_PAD_70_79_REG,
1272
+
.mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
1273
+
.val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
1274
+
}, {
1275
+
.reg = IP_SEL_MIX_PAD_REG,
1276
+
.mask = PMX_UART3_PORT_SEL_MASK,
1277
+
.val = PMX_UART3_PORT_73_VAL,
1278
+
},
1279
+
};
1280
+
1281
+
static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
1282
+
{
1283
+
.reg = IP_SEL_PAD_90_99_REG,
1284
+
.mask = PMX_PL_94_95_MASK,
1285
+
.val = PMX_UART3_PL_94_95_VAL,
1286
+
}, {
1287
+
.reg = IP_SEL_MIX_PAD_REG,
1288
+
.mask = PMX_UART3_PORT_SEL_MASK,
1289
+
.val = PMX_UART3_PORT_94_VAL,
1290
+
},
1291
+
};
1292
+
1293
+
static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
1294
+
{
1295
+
.reg = IP_SEL_PAD_90_99_REG,
1296
+
.mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
1297
+
.val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
1298
+
}, {
1299
+
.reg = IP_SEL_MIX_PAD_REG,
1300
+
.mask = PMX_UART3_PORT_SEL_MASK,
1301
+
.val = PMX_UART3_PORT_99_VAL,
1302
+
},
1303
+
};
1304
+
1305
+
static struct spear_modemux uart3_modemux[][1] = {
1306
+
{
1307
+
/* Select signals on pins 8_9 */
1308
+
{
1309
+
.modes = EXTENDED_MODE,
1310
+
.muxregs = uart3_ext_8_9_muxreg,
1311
+
.nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
1312
+
},
1313
+
}, {
1314
+
/* Select signals on pins 15_16 */
1315
+
{
1316
+
.modes = EXTENDED_MODE,
1317
+
.muxregs = uart3_ext_15_16_muxreg,
1318
+
.nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
1319
+
},
1320
+
}, {
1321
+
/* Select signals on pins 41_42 */
1322
+
{
1323
+
.modes = EXTENDED_MODE,
1324
+
.muxregs = uart3_ext_41_42_muxreg,
1325
+
.nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
1326
+
},
1327
+
}, {
1328
+
/* Select signals on pins 52_53 */
1329
+
{
1330
+
.modes = EXTENDED_MODE,
1331
+
.muxregs = uart3_ext_52_53_muxreg,
1332
+
.nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
1333
+
},
1334
+
}, {
1335
+
/* Select signals on pins 73_74 */
1336
+
{
1337
+
.modes = EXTENDED_MODE,
1338
+
.muxregs = uart3_ext_73_74_muxreg,
1339
+
.nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
1340
+
},
1341
+
}, {
1342
+
/* Select signals on pins 94_95 */
1343
+
{
1344
+
.modes = EXTENDED_MODE,
1345
+
.muxregs = uart3_ext_94_95_muxreg,
1346
+
.nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
1347
+
},
1348
+
}, {
1349
+
/* Select signals on pins 98_99 */
1350
+
{
1351
+
.modes = EXTENDED_MODE,
1352
+
.muxregs = uart3_ext_98_99_muxreg,
1353
+
.nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
1354
+
},
1355
+
},
1356
+
};
1357
+
1358
+
static struct spear_pingroup uart3_pingroup[] = {
1359
+
{
1360
+
.name = "uart3_8_9_grp",
1361
+
.pins = uart3_pins[0],
1362
+
.npins = ARRAY_SIZE(uart3_pins[0]),
1363
+
.modemuxs = uart3_modemux[0],
1364
+
.nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
1365
+
}, {
1366
+
.name = "uart3_15_16_grp",
1367
+
.pins = uart3_pins[1],
1368
+
.npins = ARRAY_SIZE(uart3_pins[1]),
1369
+
.modemuxs = uart3_modemux[1],
1370
+
.nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
1371
+
}, {
1372
+
.name = "uart3_41_42_grp",
1373
+
.pins = uart3_pins[2],
1374
+
.npins = ARRAY_SIZE(uart3_pins[2]),
1375
+
.modemuxs = uart3_modemux[2],
1376
+
.nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
1377
+
}, {
1378
+
.name = "uart3_52_53_grp",
1379
+
.pins = uart3_pins[3],
1380
+
.npins = ARRAY_SIZE(uart3_pins[3]),
1381
+
.modemuxs = uart3_modemux[3],
1382
+
.nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
1383
+
}, {
1384
+
.name = "uart3_73_74_grp",
1385
+
.pins = uart3_pins[4],
1386
+
.npins = ARRAY_SIZE(uart3_pins[4]),
1387
+
.modemuxs = uart3_modemux[4],
1388
+
.nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
1389
+
}, {
1390
+
.name = "uart3_94_95_grp",
1391
+
.pins = uart3_pins[5],
1392
+
.npins = ARRAY_SIZE(uart3_pins[5]),
1393
+
.modemuxs = uart3_modemux[5],
1394
+
.nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
1395
+
}, {
1396
+
.name = "uart3_98_99_grp",
1397
+
.pins = uart3_pins[6],
1398
+
.npins = ARRAY_SIZE(uart3_pins[6]),
1399
+
.modemuxs = uart3_modemux[6],
1400
+
.nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
1401
+
},
1402
+
};
1403
+
1404
+
static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
1405
+
"uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
1406
+
"uart3_94_95_grp", "uart3_98_99_grp" };
1407
+
1408
+
static struct spear_function uart3_function = {
1409
+
.name = "uart3",
1410
+
.groups = uart3_grps,
1411
+
.ngroups = ARRAY_SIZE(uart3_grps),
1412
+
};
1413
+
1414
+
/* Pad multiplexing for uart4 device */
1415
+
static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
1416
+
{ 71, 72 }, { 92, 93 }, { 100, 101 } };
1417
+
1418
+
static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
1419
+
{
1420
+
.reg = PMX_CONFIG_REG,
1421
+
.mask = PMX_SSP_MASK,
1422
+
.val = 0,
1423
+
}, {
1424
+
.reg = IP_SEL_PAD_0_9_REG,
1425
+
.mask = PMX_PL_6_7_MASK,
1426
+
.val = PMX_UART4_PL_6_7_VAL,
1427
+
}, {
1428
+
.reg = IP_SEL_MIX_PAD_REG,
1429
+
.mask = PMX_UART4_PORT_SEL_MASK,
1430
+
.val = PMX_UART4_PORT_6_VAL,
1431
+
},
1432
+
};
1433
+
1434
+
static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
1435
+
{
1436
+
.reg = PMX_CONFIG_REG,
1437
+
.mask = PMX_MII_MASK,
1438
+
.val = 0,
1439
+
}, {
1440
+
.reg = IP_SEL_PAD_10_19_REG,
1441
+
.mask = PMX_PL_13_14_MASK,
1442
+
.val = PMX_UART4_PL_13_14_VAL,
1443
+
}, {
1444
+
.reg = IP_SEL_MIX_PAD_REG,
1445
+
.mask = PMX_UART4_PORT_SEL_MASK,
1446
+
.val = PMX_UART4_PORT_13_VAL,
1447
+
},
1448
+
};
1449
+
1450
+
static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
1451
+
{
1452
+
.reg = PMX_CONFIG_REG,
1453
+
.mask = PMX_UART0_MODEM_MASK,
1454
+
.val = 0,
1455
+
}, {
1456
+
.reg = IP_SEL_PAD_30_39_REG,
1457
+
.mask = PMX_PL_39_MASK,
1458
+
.val = PMX_UART4_PL_39_VAL,
1459
+
}, {
1460
+
.reg = IP_SEL_PAD_40_49_REG,
1461
+
.mask = PMX_PL_40_MASK,
1462
+
.val = PMX_UART4_PL_40_VAL,
1463
+
}, {
1464
+
.reg = IP_SEL_MIX_PAD_REG,
1465
+
.mask = PMX_UART4_PORT_SEL_MASK,
1466
+
.val = PMX_UART4_PORT_39_VAL,
1467
+
},
1468
+
};
1469
+
1470
+
static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
1471
+
{
1472
+
.reg = IP_SEL_PAD_70_79_REG,
1473
+
.mask = PMX_PL_71_72_MASK,
1474
+
.val = PMX_UART4_PL_71_72_VAL,
1475
+
}, {
1476
+
.reg = IP_SEL_MIX_PAD_REG,
1477
+
.mask = PMX_UART4_PORT_SEL_MASK,
1478
+
.val = PMX_UART4_PORT_71_VAL,
1479
+
},
1480
+
};
1481
+
1482
+
static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
1483
+
{
1484
+
.reg = IP_SEL_PAD_90_99_REG,
1485
+
.mask = PMX_PL_92_93_MASK,
1486
+
.val = PMX_UART4_PL_92_93_VAL,
1487
+
}, {
1488
+
.reg = IP_SEL_MIX_PAD_REG,
1489
+
.mask = PMX_UART4_PORT_SEL_MASK,
1490
+
.val = PMX_UART4_PORT_92_VAL,
1491
+
},
1492
+
};
1493
+
1494
+
static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
1495
+
{
1496
+
.reg = IP_SEL_MIX_PAD_REG,
1497
+
.mask = PMX_PL_100_101_MASK |
1498
+
PMX_UART4_PORT_SEL_MASK,
1499
+
.val = PMX_UART4_PL_100_101_VAL |
1500
+
PMX_UART4_PORT_101_VAL,
1501
+
},
1502
+
};
1503
+
1504
+
static struct spear_modemux uart4_modemux[][1] = {
1505
+
{
1506
+
/* Select signals on pins 6_7 */
1507
+
{
1508
+
.modes = EXTENDED_MODE,
1509
+
.muxregs = uart4_ext_6_7_muxreg,
1510
+
.nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
1511
+
},
1512
+
}, {
1513
+
/* Select signals on pins 13_14 */
1514
+
{
1515
+
.modes = EXTENDED_MODE,
1516
+
.muxregs = uart4_ext_13_14_muxreg,
1517
+
.nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
1518
+
},
1519
+
}, {
1520
+
/* Select signals on pins 39_40 */
1521
+
{
1522
+
.modes = EXTENDED_MODE,
1523
+
.muxregs = uart4_ext_39_40_muxreg,
1524
+
.nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
1525
+
},
1526
+
}, {
1527
+
/* Select signals on pins 71_72 */
1528
+
{
1529
+
.modes = EXTENDED_MODE,
1530
+
.muxregs = uart4_ext_71_72_muxreg,
1531
+
.nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
1532
+
},
1533
+
}, {
1534
+
/* Select signals on pins 92_93 */
1535
+
{
1536
+
.modes = EXTENDED_MODE,
1537
+
.muxregs = uart4_ext_92_93_muxreg,
1538
+
.nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
1539
+
},
1540
+
}, {
1541
+
/* Select signals on pins 100_101_ */
1542
+
{
1543
+
.modes = EXTENDED_MODE,
1544
+
.muxregs = uart4_ext_100_101_muxreg,
1545
+
.nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
1546
+
},
1547
+
},
1548
+
};
1549
+
1550
+
static struct spear_pingroup uart4_pingroup[] = {
1551
+
{
1552
+
.name = "uart4_6_7_grp",
1553
+
.pins = uart4_pins[0],
1554
+
.npins = ARRAY_SIZE(uart4_pins[0]),
1555
+
.modemuxs = uart4_modemux[0],
1556
+
.nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
1557
+
}, {
1558
+
.name = "uart4_13_14_grp",
1559
+
.pins = uart4_pins[1],
1560
+
.npins = ARRAY_SIZE(uart4_pins[1]),
1561
+
.modemuxs = uart4_modemux[1],
1562
+
.nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
1563
+
}, {
1564
+
.name = "uart4_39_40_grp",
1565
+
.pins = uart4_pins[2],
1566
+
.npins = ARRAY_SIZE(uart4_pins[2]),
1567
+
.modemuxs = uart4_modemux[2],
1568
+
.nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
1569
+
}, {
1570
+
.name = "uart4_71_72_grp",
1571
+
.pins = uart4_pins[3],
1572
+
.npins = ARRAY_SIZE(uart4_pins[3]),
1573
+
.modemuxs = uart4_modemux[3],
1574
+
.nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
1575
+
}, {
1576
+
.name = "uart4_92_93_grp",
1577
+
.pins = uart4_pins[4],
1578
+
.npins = ARRAY_SIZE(uart4_pins[4]),
1579
+
.modemuxs = uart4_modemux[4],
1580
+
.nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
1581
+
}, {
1582
+
.name = "uart4_100_101_grp",
1583
+
.pins = uart4_pins[5],
1584
+
.npins = ARRAY_SIZE(uart4_pins[5]),
1585
+
.modemuxs = uart4_modemux[5],
1586
+
.nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
1587
+
},
1588
+
};
1589
+
1590
+
static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
1591
+
"uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
1592
+
"uart4_100_101_grp" };
1593
+
1594
+
static struct spear_function uart4_function = {
1595
+
.name = "uart4",
1596
+
.groups = uart4_grps,
1597
+
.ngroups = ARRAY_SIZE(uart4_grps),
1598
+
};
1599
+
1600
+
/* Pad multiplexing for uart5 device */
1601
+
static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
1602
+
{ 90, 91 } };
1603
+
1604
+
static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
1605
+
{
1606
+
.reg = PMX_CONFIG_REG,
1607
+
.mask = PMX_I2C_MASK,
1608
+
.val = 0,
1609
+
}, {
1610
+
.reg = IP_SEL_PAD_0_9_REG,
1611
+
.mask = PMX_PL_4_5_MASK,
1612
+
.val = PMX_UART5_PL_4_5_VAL,
1613
+
}, {
1614
+
.reg = IP_SEL_MIX_PAD_REG,
1615
+
.mask = PMX_UART5_PORT_SEL_MASK,
1616
+
.val = PMX_UART5_PORT_4_VAL,
1617
+
},
1618
+
};
1619
+
1620
+
static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
1621
+
{
1622
+
.reg = PMX_CONFIG_REG,
1623
+
.mask = PMX_UART0_MODEM_MASK,
1624
+
.val = 0,
1625
+
}, {
1626
+
.reg = IP_SEL_PAD_30_39_REG,
1627
+
.mask = PMX_PL_37_38_MASK,
1628
+
.val = PMX_UART5_PL_37_38_VAL,
1629
+
}, {
1630
+
.reg = IP_SEL_MIX_PAD_REG,
1631
+
.mask = PMX_UART5_PORT_SEL_MASK,
1632
+
.val = PMX_UART5_PORT_37_VAL,
1633
+
},
1634
+
};
1635
+
1636
+
static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
1637
+
{
1638
+
.reg = IP_SEL_PAD_60_69_REG,
1639
+
.mask = PMX_PL_69_MASK,
1640
+
.val = PMX_UART5_PL_69_VAL,
1641
+
}, {
1642
+
.reg = IP_SEL_PAD_70_79_REG,
1643
+
.mask = PMX_PL_70_MASK,
1644
+
.val = PMX_UART5_PL_70_VAL,
1645
+
}, {
1646
+
.reg = IP_SEL_MIX_PAD_REG,
1647
+
.mask = PMX_UART5_PORT_SEL_MASK,
1648
+
.val = PMX_UART5_PORT_69_VAL,
1649
+
},
1650
+
};
1651
+
1652
+
static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
1653
+
{
1654
+
.reg = IP_SEL_PAD_90_99_REG,
1655
+
.mask = PMX_PL_90_91_MASK,
1656
+
.val = PMX_UART5_PL_90_91_VAL,
1657
+
}, {
1658
+
.reg = IP_SEL_MIX_PAD_REG,
1659
+
.mask = PMX_UART5_PORT_SEL_MASK,
1660
+
.val = PMX_UART5_PORT_90_VAL,
1661
+
},
1662
+
};
1663
+
1664
+
static struct spear_modemux uart5_modemux[][1] = {
1665
+
{
1666
+
/* Select signals on pins 4_5 */
1667
+
{
1668
+
.modes = EXTENDED_MODE,
1669
+
.muxregs = uart5_ext_4_5_muxreg,
1670
+
.nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
1671
+
},
1672
+
}, {
1673
+
/* Select signals on pins 37_38 */
1674
+
{
1675
+
.modes = EXTENDED_MODE,
1676
+
.muxregs = uart5_ext_37_38_muxreg,
1677
+
.nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
1678
+
},
1679
+
}, {
1680
+
/* Select signals on pins 69_70 */
1681
+
{
1682
+
.modes = EXTENDED_MODE,
1683
+
.muxregs = uart5_ext_69_70_muxreg,
1684
+
.nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
1685
+
},
1686
+
}, {
1687
+
/* Select signals on pins 90_91 */
1688
+
{
1689
+
.modes = EXTENDED_MODE,
1690
+
.muxregs = uart5_ext_90_91_muxreg,
1691
+
.nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
1692
+
},
1693
+
},
1694
+
};
1695
+
1696
+
static struct spear_pingroup uart5_pingroup[] = {
1697
+
{
1698
+
.name = "uart5_4_5_grp",
1699
+
.pins = uart5_pins[0],
1700
+
.npins = ARRAY_SIZE(uart5_pins[0]),
1701
+
.modemuxs = uart5_modemux[0],
1702
+
.nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
1703
+
}, {
1704
+
.name = "uart5_37_38_grp",
1705
+
.pins = uart5_pins[1],
1706
+
.npins = ARRAY_SIZE(uart5_pins[1]),
1707
+
.modemuxs = uart5_modemux[1],
1708
+
.nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
1709
+
}, {
1710
+
.name = "uart5_69_70_grp",
1711
+
.pins = uart5_pins[2],
1712
+
.npins = ARRAY_SIZE(uart5_pins[2]),
1713
+
.modemuxs = uart5_modemux[2],
1714
+
.nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
1715
+
}, {
1716
+
.name = "uart5_90_91_grp",
1717
+
.pins = uart5_pins[3],
1718
+
.npins = ARRAY_SIZE(uart5_pins[3]),
1719
+
.modemuxs = uart5_modemux[3],
1720
+
.nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
1721
+
},
1722
+
};
1723
+
1724
+
static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
1725
+
"uart5_69_70_grp", "uart5_90_91_grp" };
1726
+
static struct spear_function uart5_function = {
1727
+
.name = "uart5",
1728
+
.groups = uart5_grps,
1729
+
.ngroups = ARRAY_SIZE(uart5_grps),
1730
+
};
1731
+
1732
+
/* Pad multiplexing for uart6 device */
1733
+
static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
1734
+
static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
1735
+
{
1736
+
.reg = PMX_CONFIG_REG,
1737
+
.mask = PMX_UART0_MASK,
1738
+
.val = 0,
1739
+
}, {
1740
+
.reg = IP_SEL_PAD_0_9_REG,
1741
+
.mask = PMX_PL_2_3_MASK,
1742
+
.val = PMX_UART6_PL_2_3_VAL,
1743
+
}, {
1744
+
.reg = IP_SEL_MIX_PAD_REG,
1745
+
.mask = PMX_UART6_PORT_SEL_MASK,
1746
+
.val = PMX_UART6_PORT_2_VAL,
1747
+
},
1748
+
};
1749
+
1750
+
static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
1751
+
{
1752
+
.reg = IP_SEL_PAD_80_89_REG,
1753
+
.mask = PMX_PL_88_89_MASK,
1754
+
.val = PMX_UART6_PL_88_89_VAL,
1755
+
}, {
1756
+
.reg = IP_SEL_MIX_PAD_REG,
1757
+
.mask = PMX_UART6_PORT_SEL_MASK,
1758
+
.val = PMX_UART6_PORT_88_VAL,
1759
+
},
1760
+
};
1761
+
1762
+
static struct spear_modemux uart6_modemux[][1] = {
1763
+
{
1764
+
/* Select signals on pins 2_3 */
1765
+
{
1766
+
.modes = EXTENDED_MODE,
1767
+
.muxregs = uart6_ext_2_3_muxreg,
1768
+
.nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
1769
+
},
1770
+
}, {
1771
+
/* Select signals on pins 88_89 */
1772
+
{
1773
+
.modes = EXTENDED_MODE,
1774
+
.muxregs = uart6_ext_88_89_muxreg,
1775
+
.nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
1776
+
},
1777
+
},
1778
+
};
1779
+
1780
+
static struct spear_pingroup uart6_pingroup[] = {
1781
+
{
1782
+
.name = "uart6_2_3_grp",
1783
+
.pins = uart6_pins[0],
1784
+
.npins = ARRAY_SIZE(uart6_pins[0]),
1785
+
.modemuxs = uart6_modemux[0],
1786
+
.nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
1787
+
}, {
1788
+
.name = "uart6_88_89_grp",
1789
+
.pins = uart6_pins[1],
1790
+
.npins = ARRAY_SIZE(uart6_pins[1]),
1791
+
.modemuxs = uart6_modemux[1],
1792
+
.nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
1793
+
},
1794
+
};
1795
+
1796
+
static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
1797
+
static struct spear_function uart6_function = {
1798
+
.name = "uart6",
1799
+
.groups = uart6_grps,
1800
+
.ngroups = ARRAY_SIZE(uart6_grps),
1801
+
};
1802
+
1803
+
/* UART - RS485 pmx */
1804
+
static const unsigned rs485_pins[] = { 77, 78, 79 };
1805
+
static struct spear_muxreg rs485_muxreg[] = {
1806
+
{
1807
+
.reg = IP_SEL_PAD_70_79_REG,
1808
+
.mask = PMX_PL_77_78_79_MASK,
1809
+
.val = PMX_RS485_PL_77_78_79_VAL,
1810
+
},
1811
+
};
1812
+
1813
+
static struct spear_modemux rs485_modemux[] = {
1814
+
{
1815
+
.modes = EXTENDED_MODE,
1816
+
.muxregs = rs485_muxreg,
1817
+
.nmuxregs = ARRAY_SIZE(rs485_muxreg),
1818
+
},
1819
+
};
1820
+
1821
+
static struct spear_pingroup rs485_pingroup = {
1822
+
.name = "rs485_grp",
1823
+
.pins = rs485_pins,
1824
+
.npins = ARRAY_SIZE(rs485_pins),
1825
+
.modemuxs = rs485_modemux,
1826
+
.nmodemuxs = ARRAY_SIZE(rs485_modemux),
1827
+
};
1828
+
1829
+
static const char *const rs485_grps[] = { "rs485_grp" };
1830
+
static struct spear_function rs485_function = {
1831
+
.name = "rs485",
1832
+
.groups = rs485_grps,
1833
+
.ngroups = ARRAY_SIZE(rs485_grps),
1834
+
};
1835
+
1836
+
/* Pad multiplexing for Touchscreen device */
1837
+
static const unsigned touchscreen_pins[] = { 5, 36 };
1838
+
static struct spear_muxreg touchscreen_muxreg[] = {
1839
+
{
1840
+
.reg = PMX_CONFIG_REG,
1841
+
.mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
1842
+
.val = 0,
1843
+
},
1844
+
};
1845
+
1846
+
static struct spear_muxreg touchscreen_ext_muxreg[] = {
1847
+
{
1848
+
.reg = IP_SEL_PAD_0_9_REG,
1849
+
.mask = PMX_PL_5_MASK,
1850
+
.val = PMX_TOUCH_Y_PL_5_VAL,
1851
+
}, {
1852
+
.reg = IP_SEL_PAD_30_39_REG,
1853
+
.mask = PMX_PL_36_MASK,
1854
+
.val = PMX_TOUCH_X_PL_36_VAL,
1855
+
},
1856
+
};
1857
+
1858
+
static struct spear_modemux touchscreen_modemux[] = {
1859
+
{
1860
+
.modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
1861
+
.muxregs = touchscreen_muxreg,
1862
+
.nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
1863
+
}, {
1864
+
.modes = EXTENDED_MODE,
1865
+
.muxregs = touchscreen_ext_muxreg,
1866
+
.nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
1867
+
},
1868
+
};
1869
+
1870
+
static struct spear_pingroup touchscreen_pingroup = {
1871
+
.name = "touchscreen_grp",
1872
+
.pins = touchscreen_pins,
1873
+
.npins = ARRAY_SIZE(touchscreen_pins),
1874
+
.modemuxs = touchscreen_modemux,
1875
+
.nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
1876
+
};
1877
+
1878
+
static const char *const touchscreen_grps[] = { "touchscreen_grp" };
1879
+
static struct spear_function touchscreen_function = {
1880
+
.name = "touchscreen",
1881
+
.groups = touchscreen_grps,
1882
+
.ngroups = ARRAY_SIZE(touchscreen_grps),
1883
+
};
1884
+
1885
+
/* Pad multiplexing for CAN device */
1886
+
static const unsigned can0_pins[] = { 32, 33 };
1887
+
static struct spear_muxreg can0_muxreg[] = {
1888
+
{
1889
+
.reg = PMX_CONFIG_REG,
1890
+
.mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
1891
+
.val = 0,
1892
+
},
1893
+
};
1894
+
1895
+
static struct spear_muxreg can0_ext_muxreg[] = {
1896
+
{
1897
+
.reg = IP_SEL_PAD_30_39_REG,
1898
+
.mask = PMX_PL_32_33_MASK,
1899
+
.val = PMX_CAN0_PL_32_33_VAL,
1900
+
},
1901
+
};
1902
+
1903
+
static struct spear_modemux can0_modemux[] = {
1904
+
{
1905
+
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1906
+
| EXTENDED_MODE,
1907
+
.muxregs = can0_muxreg,
1908
+
.nmuxregs = ARRAY_SIZE(can0_muxreg),
1909
+
}, {
1910
+
.modes = EXTENDED_MODE,
1911
+
.muxregs = can0_ext_muxreg,
1912
+
.nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
1913
+
},
1914
+
};
1915
+
1916
+
static struct spear_pingroup can0_pingroup = {
1917
+
.name = "can0_grp",
1918
+
.pins = can0_pins,
1919
+
.npins = ARRAY_SIZE(can0_pins),
1920
+
.modemuxs = can0_modemux,
1921
+
.nmodemuxs = ARRAY_SIZE(can0_modemux),
1922
+
};
1923
+
1924
+
static const char *const can0_grps[] = { "can0_grp" };
1925
+
static struct spear_function can0_function = {
1926
+
.name = "can0",
1927
+
.groups = can0_grps,
1928
+
.ngroups = ARRAY_SIZE(can0_grps),
1929
+
};
1930
+
1931
+
static const unsigned can1_pins[] = { 30, 31 };
1932
+
static struct spear_muxreg can1_muxreg[] = {
1933
+
{
1934
+
.reg = PMX_CONFIG_REG,
1935
+
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
1936
+
.val = 0,
1937
+
},
1938
+
};
1939
+
1940
+
static struct spear_muxreg can1_ext_muxreg[] = {
1941
+
{
1942
+
.reg = IP_SEL_PAD_30_39_REG,
1943
+
.mask = PMX_PL_30_31_MASK,
1944
+
.val = PMX_CAN1_PL_30_31_VAL,
1945
+
},
1946
+
};
1947
+
1948
+
static struct spear_modemux can1_modemux[] = {
1949
+
{
1950
+
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1951
+
| EXTENDED_MODE,
1952
+
.muxregs = can1_muxreg,
1953
+
.nmuxregs = ARRAY_SIZE(can1_muxreg),
1954
+
}, {
1955
+
.modes = EXTENDED_MODE,
1956
+
.muxregs = can1_ext_muxreg,
1957
+
.nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
1958
+
},
1959
+
};
1960
+
1961
+
static struct spear_pingroup can1_pingroup = {
1962
+
.name = "can1_grp",
1963
+
.pins = can1_pins,
1964
+
.npins = ARRAY_SIZE(can1_pins),
1965
+
.modemuxs = can1_modemux,
1966
+
.nmodemuxs = ARRAY_SIZE(can1_modemux),
1967
+
};
1968
+
1969
+
static const char *const can1_grps[] = { "can1_grp" };
1970
+
static struct spear_function can1_function = {
1971
+
.name = "can1",
1972
+
.groups = can1_grps,
1973
+
.ngroups = ARRAY_SIZE(can1_grps),
1974
+
};
1975
+
1976
+
/* Pad multiplexing for PWM0_1 device */
1977
+
static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
1978
+
{ 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
1979
+
1980
+
static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
1981
+
{
1982
+
.reg = PMX_CONFIG_REG,
1983
+
.mask = PMX_SSP_MASK,
1984
+
.val = 0,
1985
+
}, {
1986
+
.reg = IP_SEL_PAD_0_9_REG,
1987
+
.mask = PMX_PL_8_9_MASK,
1988
+
.val = PMX_PWM_0_1_PL_8_9_VAL,
1989
+
},
1990
+
};
1991
+
1992
+
static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
1993
+
{
1994
+
.reg = PMX_CONFIG_REG,
1995
+
.mask = PMX_MII_MASK,
1996
+
.val = 0,
1997
+
},
1998
+
};
1999
+
2000
+
static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
2001
+
{
2002
+
.reg = IP_SEL_PAD_10_19_REG,
2003
+
.mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
2004
+
.val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
2005
+
},
2006
+
};
2007
+
2008
+
static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
2009
+
{
2010
+
.reg = PMX_CONFIG_REG,
2011
+
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
2012
+
.val = 0,
2013
+
}, {
2014
+
.reg = IP_SEL_PAD_30_39_REG,
2015
+
.mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
2016
+
.val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
2017
+
},
2018
+
};
2019
+
2020
+
static struct spear_muxreg pwm0_1_net_muxreg[] = {
2021
+
{
2022
+
.reg = PMX_CONFIG_REG,
2023
+
.mask = PMX_UART0_MODEM_MASK,
2024
+
.val = 0,
2025
+
},
2026
+
};
2027
+
2028
+
static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
2029
+
{
2030
+
.reg = IP_SEL_PAD_30_39_REG,
2031
+
.mask = PMX_PL_37_38_MASK,
2032
+
.val = PMX_PWM0_1_PL_37_38_VAL,
2033
+
},
2034
+
};
2035
+
2036
+
static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
2037
+
{
2038
+
.reg = PMX_CONFIG_REG,
2039
+
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
2040
+
.val = 0,
2041
+
}, {
2042
+
.reg = IP_SEL_PAD_40_49_REG,
2043
+
.mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
2044
+
.val = PMX_PWM1_PL_42_VAL |
2045
+
PMX_PWM0_PL_43_VAL,
2046
+
},
2047
+
};
2048
+
2049
+
static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
2050
+
{
2051
+
.reg = IP_SEL_PAD_50_59_REG,
2052
+
.mask = PMX_PL_59_MASK,
2053
+
.val = PMX_PWM1_PL_59_VAL,
2054
+
}, {
2055
+
.reg = IP_SEL_PAD_60_69_REG,
2056
+
.mask = PMX_PL_60_MASK,
2057
+
.val = PMX_PWM0_PL_60_VAL,
2058
+
},
2059
+
};
2060
+
2061
+
static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
2062
+
{
2063
+
.reg = IP_SEL_PAD_80_89_REG,
2064
+
.mask = PMX_PL_88_89_MASK,
2065
+
.val = PMX_PWM0_1_PL_88_89_VAL,
2066
+
},
2067
+
};
2068
+
2069
+
static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
2070
+
{
2071
+
.modes = EXTENDED_MODE,
2072
+
.muxregs = pwm0_1_pin_8_9_muxreg,
2073
+
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
2074
+
},
2075
+
};
2076
+
2077
+
static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
2078
+
{
2079
+
.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2080
+
.muxregs = pwm0_1_autoexpsmallpri_muxreg,
2081
+
.nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
2082
+
}, {
2083
+
.modes = EXTENDED_MODE,
2084
+
.muxregs = pwm0_1_pin_14_15_muxreg,
2085
+
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
2086
+
},
2087
+
};
2088
+
2089
+
static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
2090
+
{
2091
+
.modes = EXTENDED_MODE,
2092
+
.muxregs = pwm0_1_pin_30_31_muxreg,
2093
+
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
2094
+
},
2095
+
};
2096
+
2097
+
static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
2098
+
{
2099
+
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2100
+
.muxregs = pwm0_1_net_muxreg,
2101
+
.nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
2102
+
}, {
2103
+
.modes = EXTENDED_MODE,
2104
+
.muxregs = pwm0_1_pin_37_38_muxreg,
2105
+
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
2106
+
},
2107
+
};
2108
+
2109
+
static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
2110
+
{
2111
+
.modes = EXTENDED_MODE,
2112
+
.muxregs = pwm0_1_pin_42_43_muxreg,
2113
+
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
2114
+
},
2115
+
};
2116
+
2117
+
static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
2118
+
{
2119
+
.modes = EXTENDED_MODE,
2120
+
.muxregs = pwm0_1_pin_59_60_muxreg,
2121
+
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
2122
+
},
2123
+
};
2124
+
2125
+
static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
2126
+
{
2127
+
.modes = EXTENDED_MODE,
2128
+
.muxregs = pwm0_1_pin_88_89_muxreg,
2129
+
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
2130
+
},
2131
+
};
2132
+
2133
+
static struct spear_pingroup pwm0_1_pingroup[] = {
2134
+
{
2135
+
.name = "pwm0_1_pin_8_9_grp",
2136
+
.pins = pwm0_1_pins[0],
2137
+
.npins = ARRAY_SIZE(pwm0_1_pins[0]),
2138
+
.modemuxs = pwm0_1_pin_8_9_modemux,
2139
+
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
2140
+
}, {
2141
+
.name = "pwm0_1_pin_14_15_grp",
2142
+
.pins = pwm0_1_pins[1],
2143
+
.npins = ARRAY_SIZE(pwm0_1_pins[1]),
2144
+
.modemuxs = pwm0_1_pin_14_15_modemux,
2145
+
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
2146
+
}, {
2147
+
.name = "pwm0_1_pin_30_31_grp",
2148
+
.pins = pwm0_1_pins[2],
2149
+
.npins = ARRAY_SIZE(pwm0_1_pins[2]),
2150
+
.modemuxs = pwm0_1_pin_30_31_modemux,
2151
+
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
2152
+
}, {
2153
+
.name = "pwm0_1_pin_37_38_grp",
2154
+
.pins = pwm0_1_pins[3],
2155
+
.npins = ARRAY_SIZE(pwm0_1_pins[3]),
2156
+
.modemuxs = pwm0_1_pin_37_38_modemux,
2157
+
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
2158
+
}, {
2159
+
.name = "pwm0_1_pin_42_43_grp",
2160
+
.pins = pwm0_1_pins[4],
2161
+
.npins = ARRAY_SIZE(pwm0_1_pins[4]),
2162
+
.modemuxs = pwm0_1_pin_42_43_modemux,
2163
+
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
2164
+
}, {
2165
+
.name = "pwm0_1_pin_59_60_grp",
2166
+
.pins = pwm0_1_pins[5],
2167
+
.npins = ARRAY_SIZE(pwm0_1_pins[5]),
2168
+
.modemuxs = pwm0_1_pin_59_60_modemux,
2169
+
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
2170
+
}, {
2171
+
.name = "pwm0_1_pin_88_89_grp",
2172
+
.pins = pwm0_1_pins[6],
2173
+
.npins = ARRAY_SIZE(pwm0_1_pins[6]),
2174
+
.modemuxs = pwm0_1_pin_88_89_modemux,
2175
+
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
2176
+
},
2177
+
};
2178
+
2179
+
static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
2180
+
"pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
2181
+
"pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
2182
+
};
2183
+
2184
+
static struct spear_function pwm0_1_function = {
2185
+
.name = "pwm0_1",
2186
+
.groups = pwm0_1_grps,
2187
+
.ngroups = ARRAY_SIZE(pwm0_1_grps),
2188
+
};
2189
+
2190
+
/* Pad multiplexing for PWM2 device */
2191
+
static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
2192
+
{ 58 }, { 87 } };
2193
+
static struct spear_muxreg pwm2_net_muxreg[] = {
2194
+
{
2195
+
.reg = PMX_CONFIG_REG,
2196
+
.mask = PMX_SSP_CS_MASK,
2197
+
.val = 0,
2198
+
},
2199
+
};
2200
+
2201
+
static struct spear_muxreg pwm2_pin_7_muxreg[] = {
2202
+
{
2203
+
.reg = IP_SEL_PAD_0_9_REG,
2204
+
.mask = PMX_PL_7_MASK,
2205
+
.val = PMX_PWM_2_PL_7_VAL,
2206
+
},
2207
+
};
2208
+
2209
+
static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
2210
+
{
2211
+
.reg = PMX_CONFIG_REG,
2212
+
.mask = PMX_MII_MASK,
2213
+
.val = 0,
2214
+
},
2215
+
};
2216
+
2217
+
static struct spear_muxreg pwm2_pin_13_muxreg[] = {
2218
+
{
2219
+
.reg = IP_SEL_PAD_10_19_REG,
2220
+
.mask = PMX_PL_13_MASK,
2221
+
.val = PMX_PWM2_PL_13_VAL,
2222
+
},
2223
+
};
2224
+
2225
+
static struct spear_muxreg pwm2_pin_29_muxreg[] = {
2226
+
{
2227
+
.reg = PMX_CONFIG_REG,
2228
+
.mask = PMX_GPIO_PIN1_MASK,
2229
+
.val = 0,
2230
+
}, {
2231
+
.reg = IP_SEL_PAD_20_29_REG,
2232
+
.mask = PMX_PL_29_MASK,
2233
+
.val = PMX_PWM_2_PL_29_VAL,
2234
+
},
2235
+
};
2236
+
2237
+
static struct spear_muxreg pwm2_pin_34_muxreg[] = {
2238
+
{
2239
+
.reg = PMX_CONFIG_REG,
2240
+
.mask = PMX_SSP_CS_MASK,
2241
+
.val = 0,
2242
+
}, {
2243
+
.reg = IP_SEL_PAD_30_39_REG,
2244
+
.mask = PMX_PL_34_MASK,
2245
+
.val = PMX_PWM2_PL_34_VAL,
2246
+
},
2247
+
};
2248
+
2249
+
static struct spear_muxreg pwm2_pin_41_muxreg[] = {
2250
+
{
2251
+
.reg = PMX_CONFIG_REG,
2252
+
.mask = PMX_UART0_MODEM_MASK,
2253
+
.val = 0,
2254
+
}, {
2255
+
.reg = IP_SEL_PAD_40_49_REG,
2256
+
.mask = PMX_PL_41_MASK,
2257
+
.val = PMX_PWM2_PL_41_VAL,
2258
+
},
2259
+
};
2260
+
2261
+
static struct spear_muxreg pwm2_pin_58_muxreg[] = {
2262
+
{
2263
+
.reg = IP_SEL_PAD_50_59_REG,
2264
+
.mask = PMX_PL_58_MASK,
2265
+
.val = PMX_PWM2_PL_58_VAL,
2266
+
},
2267
+
};
2268
+
2269
+
static struct spear_muxreg pwm2_pin_87_muxreg[] = {
2270
+
{
2271
+
.reg = IP_SEL_PAD_80_89_REG,
2272
+
.mask = PMX_PL_87_MASK,
2273
+
.val = PMX_PWM2_PL_87_VAL,
2274
+
},
2275
+
};
2276
+
2277
+
static struct spear_modemux pwm2_pin_7_modemux[] = {
2278
+
{
2279
+
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2280
+
.muxregs = pwm2_net_muxreg,
2281
+
.nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
2282
+
}, {
2283
+
.modes = EXTENDED_MODE,
2284
+
.muxregs = pwm2_pin_7_muxreg,
2285
+
.nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
2286
+
},
2287
+
};
2288
+
static struct spear_modemux pwm2_pin_13_modemux[] = {
2289
+
{
2290
+
.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2291
+
.muxregs = pwm2_autoexpsmallpri_muxreg,
2292
+
.nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
2293
+
}, {
2294
+
.modes = EXTENDED_MODE,
2295
+
.muxregs = pwm2_pin_13_muxreg,
2296
+
.nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
2297
+
},
2298
+
};
2299
+
static struct spear_modemux pwm2_pin_29_modemux[] = {
2300
+
{
2301
+
.modes = EXTENDED_MODE,
2302
+
.muxregs = pwm2_pin_29_muxreg,
2303
+
.nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
2304
+
},
2305
+
};
2306
+
static struct spear_modemux pwm2_pin_34_modemux[] = {
2307
+
{
2308
+
.modes = EXTENDED_MODE,
2309
+
.muxregs = pwm2_pin_34_muxreg,
2310
+
.nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
2311
+
},
2312
+
};
2313
+
2314
+
static struct spear_modemux pwm2_pin_41_modemux[] = {
2315
+
{
2316
+
.modes = EXTENDED_MODE,
2317
+
.muxregs = pwm2_pin_41_muxreg,
2318
+
.nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
2319
+
},
2320
+
};
2321
+
2322
+
static struct spear_modemux pwm2_pin_58_modemux[] = {
2323
+
{
2324
+
.modes = EXTENDED_MODE,
2325
+
.muxregs = pwm2_pin_58_muxreg,
2326
+
.nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
2327
+
},
2328
+
};
2329
+
2330
+
static struct spear_modemux pwm2_pin_87_modemux[] = {
2331
+
{
2332
+
.modes = EXTENDED_MODE,
2333
+
.muxregs = pwm2_pin_87_muxreg,
2334
+
.nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
2335
+
},
2336
+
};
2337
+
2338
+
static struct spear_pingroup pwm2_pingroup[] = {
2339
+
{
2340
+
.name = "pwm2_pin_7_grp",
2341
+
.pins = pwm2_pins[0],
2342
+
.npins = ARRAY_SIZE(pwm2_pins[0]),
2343
+
.modemuxs = pwm2_pin_7_modemux,
2344
+
.nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
2345
+
}, {
2346
+
.name = "pwm2_pin_13_grp",
2347
+
.pins = pwm2_pins[1],
2348
+
.npins = ARRAY_SIZE(pwm2_pins[1]),
2349
+
.modemuxs = pwm2_pin_13_modemux,
2350
+
.nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
2351
+
}, {
2352
+
.name = "pwm2_pin_29_grp",
2353
+
.pins = pwm2_pins[2],
2354
+
.npins = ARRAY_SIZE(pwm2_pins[2]),
2355
+
.modemuxs = pwm2_pin_29_modemux,
2356
+
.nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
2357
+
}, {
2358
+
.name = "pwm2_pin_34_grp",
2359
+
.pins = pwm2_pins[3],
2360
+
.npins = ARRAY_SIZE(pwm2_pins[3]),
2361
+
.modemuxs = pwm2_pin_34_modemux,
2362
+
.nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
2363
+
}, {
2364
+
.name = "pwm2_pin_41_grp",
2365
+
.pins = pwm2_pins[4],
2366
+
.npins = ARRAY_SIZE(pwm2_pins[4]),
2367
+
.modemuxs = pwm2_pin_41_modemux,
2368
+
.nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
2369
+
}, {
2370
+
.name = "pwm2_pin_58_grp",
2371
+
.pins = pwm2_pins[5],
2372
+
.npins = ARRAY_SIZE(pwm2_pins[5]),
2373
+
.modemuxs = pwm2_pin_58_modemux,
2374
+
.nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
2375
+
}, {
2376
+
.name = "pwm2_pin_87_grp",
2377
+
.pins = pwm2_pins[6],
2378
+
.npins = ARRAY_SIZE(pwm2_pins[6]),
2379
+
.modemuxs = pwm2_pin_87_modemux,
2380
+
.nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
2381
+
},
2382
+
};
2383
+
2384
+
static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
2385
+
"pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
2386
+
"pwm2_pin_58_grp", "pwm2_pin_87_grp" };
2387
+
static struct spear_function pwm2_function = {
2388
+
.name = "pwm2",
2389
+
.groups = pwm2_grps,
2390
+
.ngroups = ARRAY_SIZE(pwm2_grps),
2391
+
};
2392
+
2393
+
/* Pad multiplexing for PWM3 device */
2394
+
static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
2395
+
{ 86 } };
2396
+
static struct spear_muxreg pwm3_pin_6_muxreg[] = {
2397
+
{
2398
+
.reg = PMX_CONFIG_REG,
2399
+
.mask = PMX_SSP_MASK,
2400
+
.val = 0,
2401
+
}, {
2402
+
.reg = IP_SEL_PAD_0_9_REG,
2403
+
.mask = PMX_PL_6_MASK,
2404
+
.val = PMX_PWM_3_PL_6_VAL,
2405
+
},
2406
+
};
2407
+
2408
+
static struct spear_muxreg pwm3_muxreg[] = {
2409
+
{
2410
+
.reg = PMX_CONFIG_REG,
2411
+
.mask = PMX_MII_MASK,
2412
+
.val = 0,
2413
+
},
2414
+
};
2415
+
2416
+
static struct spear_muxreg pwm3_pin_12_muxreg[] = {
2417
+
{
2418
+
.reg = IP_SEL_PAD_10_19_REG,
2419
+
.mask = PMX_PL_12_MASK,
2420
+
.val = PMX_PWM3_PL_12_VAL,
2421
+
},
2422
+
};
2423
+
2424
+
static struct spear_muxreg pwm3_pin_28_muxreg[] = {
2425
+
{
2426
+
.reg = PMX_CONFIG_REG,
2427
+
.mask = PMX_GPIO_PIN0_MASK,
2428
+
.val = 0,
2429
+
}, {
2430
+
.reg = IP_SEL_PAD_20_29_REG,
2431
+
.mask = PMX_PL_28_MASK,
2432
+
.val = PMX_PWM_3_PL_28_VAL,
2433
+
},
2434
+
};
2435
+
2436
+
static struct spear_muxreg pwm3_pin_40_muxreg[] = {
2437
+
{
2438
+
.reg = PMX_CONFIG_REG,
2439
+
.mask = PMX_UART0_MODEM_MASK,
2440
+
.val = 0,
2441
+
}, {
2442
+
.reg = IP_SEL_PAD_40_49_REG,
2443
+
.mask = PMX_PL_40_MASK,
2444
+
.val = PMX_PWM3_PL_40_VAL,
2445
+
},
2446
+
};
2447
+
2448
+
static struct spear_muxreg pwm3_pin_57_muxreg[] = {
2449
+
{
2450
+
.reg = IP_SEL_PAD_50_59_REG,
2451
+
.mask = PMX_PL_57_MASK,
2452
+
.val = PMX_PWM3_PL_57_VAL,
2453
+
},
2454
+
};
2455
+
2456
+
static struct spear_muxreg pwm3_pin_86_muxreg[] = {
2457
+
{
2458
+
.reg = IP_SEL_PAD_80_89_REG,
2459
+
.mask = PMX_PL_86_MASK,
2460
+
.val = PMX_PWM3_PL_86_VAL,
2461
+
},
2462
+
};
2463
+
2464
+
static struct spear_modemux pwm3_pin_6_modemux[] = {
2465
+
{
2466
+
.modes = EXTENDED_MODE,
2467
+
.muxregs = pwm3_pin_6_muxreg,
2468
+
.nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
2469
+
},
2470
+
};
2471
+
2472
+
static struct spear_modemux pwm3_pin_12_modemux[] = {
2473
+
{
2474
+
.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
2475
+
AUTO_NET_SMII_MODE | EXTENDED_MODE,
2476
+
.muxregs = pwm3_muxreg,
2477
+
.nmuxregs = ARRAY_SIZE(pwm3_muxreg),
2478
+
}, {
2479
+
.modes = EXTENDED_MODE,
2480
+
.muxregs = pwm3_pin_12_muxreg,
2481
+
.nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
2482
+
},
2483
+
};
2484
+
2485
+
static struct spear_modemux pwm3_pin_28_modemux[] = {
2486
+
{
2487
+
.modes = EXTENDED_MODE,
2488
+
.muxregs = pwm3_pin_28_muxreg,
2489
+
.nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
2490
+
},
2491
+
};
2492
+
2493
+
static struct spear_modemux pwm3_pin_40_modemux[] = {
2494
+
{
2495
+
.modes = EXTENDED_MODE,
2496
+
.muxregs = pwm3_pin_40_muxreg,
2497
+
.nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
2498
+
},
2499
+
};
2500
+
2501
+
static struct spear_modemux pwm3_pin_57_modemux[] = {
2502
+
{
2503
+
.modes = EXTENDED_MODE,
2504
+
.muxregs = pwm3_pin_57_muxreg,
2505
+
.nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
2506
+
},
2507
+
};
2508
+
2509
+
static struct spear_modemux pwm3_pin_86_modemux[] = {
2510
+
{
2511
+
.modes = EXTENDED_MODE,
2512
+
.muxregs = pwm3_pin_86_muxreg,
2513
+
.nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
2514
+
},
2515
+
};
2516
+
2517
+
static struct spear_pingroup pwm3_pingroup[] = {
2518
+
{
2519
+
.name = "pwm3_pin_6_grp",
2520
+
.pins = pwm3_pins[0],
2521
+
.npins = ARRAY_SIZE(pwm3_pins[0]),
2522
+
.modemuxs = pwm3_pin_6_modemux,
2523
+
.nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
2524
+
}, {
2525
+
.name = "pwm3_pin_12_grp",
2526
+
.pins = pwm3_pins[1],
2527
+
.npins = ARRAY_SIZE(pwm3_pins[1]),
2528
+
.modemuxs = pwm3_pin_12_modemux,
2529
+
.nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
2530
+
}, {
2531
+
.name = "pwm3_pin_28_grp",
2532
+
.pins = pwm3_pins[2],
2533
+
.npins = ARRAY_SIZE(pwm3_pins[2]),
2534
+
.modemuxs = pwm3_pin_28_modemux,
2535
+
.nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
2536
+
}, {
2537
+
.name = "pwm3_pin_40_grp",
2538
+
.pins = pwm3_pins[3],
2539
+
.npins = ARRAY_SIZE(pwm3_pins[3]),
2540
+
.modemuxs = pwm3_pin_40_modemux,
2541
+
.nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
2542
+
}, {
2543
+
.name = "pwm3_pin_57_grp",
2544
+
.pins = pwm3_pins[4],
2545
+
.npins = ARRAY_SIZE(pwm3_pins[4]),
2546
+
.modemuxs = pwm3_pin_57_modemux,
2547
+
.nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
2548
+
}, {
2549
+
.name = "pwm3_pin_86_grp",
2550
+
.pins = pwm3_pins[5],
2551
+
.npins = ARRAY_SIZE(pwm3_pins[5]),
2552
+
.modemuxs = pwm3_pin_86_modemux,
2553
+
.nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
2554
+
},
2555
+
};
2556
+
2557
+
static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
2558
+
"pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
2559
+
"pwm3_pin_86_grp" };
2560
+
static struct spear_function pwm3_function = {
2561
+
.name = "pwm3",
2562
+
.groups = pwm3_grps,
2563
+
.ngroups = ARRAY_SIZE(pwm3_grps),
2564
+
};
2565
+
2566
+
/* Pad multiplexing for SSP1 device */
2567
+
static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
2568
+
{ 65, 68 }, { 94, 97 } };
2569
+
static struct spear_muxreg ssp1_muxreg[] = {
2570
+
{
2571
+
.reg = PMX_CONFIG_REG,
2572
+
.mask = PMX_MII_MASK,
2573
+
.val = 0,
2574
+
},
2575
+
};
2576
+
2577
+
static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
2578
+
{
2579
+
.reg = IP_SEL_PAD_10_19_REG,
2580
+
.mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2581
+
.val = PMX_SSP1_PL_17_18_19_20_VAL,
2582
+
}, {
2583
+
.reg = IP_SEL_PAD_20_29_REG,
2584
+
.mask = PMX_PL_20_MASK,
2585
+
.val = PMX_SSP1_PL_17_18_19_20_VAL,
2586
+
}, {
2587
+
.reg = IP_SEL_MIX_PAD_REG,
2588
+
.mask = PMX_SSP1_PORT_SEL_MASK,
2589
+
.val = PMX_SSP1_PORT_17_TO_20_VAL,
2590
+
},
2591
+
};
2592
+
2593
+
static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
2594
+
{
2595
+
.reg = PMX_CONFIG_REG,
2596
+
.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
2597
+
.val = 0,
2598
+
}, {
2599
+
.reg = IP_SEL_PAD_30_39_REG,
2600
+
.mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
2601
+
.val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
2602
+
PMX_SSP1_PL_39_VAL,
2603
+
}, {
2604
+
.reg = IP_SEL_MIX_PAD_REG,
2605
+
.mask = PMX_SSP1_PORT_SEL_MASK,
2606
+
.val = PMX_SSP1_PORT_36_TO_39_VAL,
2607
+
},
2608
+
};
2609
+
2610
+
static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
2611
+
{
2612
+
.reg = PMX_CONFIG_REG,
2613
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2614
+
.val = 0,
2615
+
}, {
2616
+
.reg = IP_SEL_PAD_40_49_REG,
2617
+
.mask = PMX_PL_48_49_MASK,
2618
+
.val = PMX_SSP1_PL_48_49_VAL,
2619
+
}, {
2620
+
.reg = IP_SEL_PAD_50_59_REG,
2621
+
.mask = PMX_PL_50_51_MASK,
2622
+
.val = PMX_SSP1_PL_50_51_VAL,
2623
+
}, {
2624
+
.reg = IP_SEL_MIX_PAD_REG,
2625
+
.mask = PMX_SSP1_PORT_SEL_MASK,
2626
+
.val = PMX_SSP1_PORT_48_TO_51_VAL,
2627
+
},
2628
+
};
2629
+
2630
+
static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
2631
+
{
2632
+
.reg = IP_SEL_PAD_60_69_REG,
2633
+
.mask = PMX_PL_65_TO_68_MASK,
2634
+
.val = PMX_SSP1_PL_65_TO_68_VAL,
2635
+
}, {
2636
+
.reg = IP_SEL_MIX_PAD_REG,
2637
+
.mask = PMX_SSP1_PORT_SEL_MASK,
2638
+
.val = PMX_SSP1_PORT_65_TO_68_VAL,
2639
+
},
2640
+
};
2641
+
2642
+
static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
2643
+
{
2644
+
.reg = IP_SEL_PAD_90_99_REG,
2645
+
.mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2646
+
.val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
2647
+
}, {
2648
+
.reg = IP_SEL_MIX_PAD_REG,
2649
+
.mask = PMX_SSP1_PORT_SEL_MASK,
2650
+
.val = PMX_SSP1_PORT_94_TO_97_VAL,
2651
+
},
2652
+
};
2653
+
2654
+
static struct spear_modemux ssp1_17_20_modemux[] = {
2655
+
{
2656
+
.modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
2657
+
EXTENDED_MODE,
2658
+
.muxregs = ssp1_muxreg,
2659
+
.nmuxregs = ARRAY_SIZE(ssp1_muxreg),
2660
+
}, {
2661
+
.modes = EXTENDED_MODE,
2662
+
.muxregs = ssp1_ext_17_20_muxreg,
2663
+
.nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
2664
+
},
2665
+
};
2666
+
2667
+
static struct spear_modemux ssp1_36_39_modemux[] = {
2668
+
{
2669
+
.modes = EXTENDED_MODE,
2670
+
.muxregs = ssp1_ext_36_39_muxreg,
2671
+
.nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
2672
+
},
2673
+
};
2674
+
2675
+
static struct spear_modemux ssp1_48_51_modemux[] = {
2676
+
{
2677
+
.modes = EXTENDED_MODE,
2678
+
.muxregs = ssp1_ext_48_51_muxreg,
2679
+
.nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
2680
+
},
2681
+
};
2682
+
static struct spear_modemux ssp1_65_68_modemux[] = {
2683
+
{
2684
+
.modes = EXTENDED_MODE,
2685
+
.muxregs = ssp1_ext_65_68_muxreg,
2686
+
.nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
2687
+
},
2688
+
};
2689
+
2690
+
static struct spear_modemux ssp1_94_97_modemux[] = {
2691
+
{
2692
+
.modes = EXTENDED_MODE,
2693
+
.muxregs = ssp1_ext_94_97_muxreg,
2694
+
.nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
2695
+
},
2696
+
};
2697
+
2698
+
static struct spear_pingroup ssp1_pingroup[] = {
2699
+
{
2700
+
.name = "ssp1_17_20_grp",
2701
+
.pins = ssp1_pins[0],
2702
+
.npins = ARRAY_SIZE(ssp1_pins[0]),
2703
+
.modemuxs = ssp1_17_20_modemux,
2704
+
.nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
2705
+
}, {
2706
+
.name = "ssp1_36_39_grp",
2707
+
.pins = ssp1_pins[1],
2708
+
.npins = ARRAY_SIZE(ssp1_pins[1]),
2709
+
.modemuxs = ssp1_36_39_modemux,
2710
+
.nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
2711
+
}, {
2712
+
.name = "ssp1_48_51_grp",
2713
+
.pins = ssp1_pins[2],
2714
+
.npins = ARRAY_SIZE(ssp1_pins[2]),
2715
+
.modemuxs = ssp1_48_51_modemux,
2716
+
.nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
2717
+
}, {
2718
+
.name = "ssp1_65_68_grp",
2719
+
.pins = ssp1_pins[3],
2720
+
.npins = ARRAY_SIZE(ssp1_pins[3]),
2721
+
.modemuxs = ssp1_65_68_modemux,
2722
+
.nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
2723
+
}, {
2724
+
.name = "ssp1_94_97_grp",
2725
+
.pins = ssp1_pins[4],
2726
+
.npins = ARRAY_SIZE(ssp1_pins[4]),
2727
+
.modemuxs = ssp1_94_97_modemux,
2728
+
.nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
2729
+
},
2730
+
};
2731
+
2732
+
static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
2733
+
"ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
2734
+
};
2735
+
static struct spear_function ssp1_function = {
2736
+
.name = "ssp1",
2737
+
.groups = ssp1_grps,
2738
+
.ngroups = ARRAY_SIZE(ssp1_grps),
2739
+
};
2740
+
2741
+
/* Pad multiplexing for SSP2 device */
2742
+
static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
2743
+
{ 61, 64 }, { 90, 93 } };
2744
+
static struct spear_muxreg ssp2_muxreg[] = {
2745
+
{
2746
+
.reg = PMX_CONFIG_REG,
2747
+
.mask = PMX_MII_MASK,
2748
+
.val = 0,
2749
+
},
2750
+
};
2751
+
2752
+
static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
2753
+
{
2754
+
.reg = IP_SEL_PAD_10_19_REG,
2755
+
.mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
2756
+
.val = PMX_SSP2_PL_13_14_15_16_VAL,
2757
+
}, {
2758
+
.reg = IP_SEL_MIX_PAD_REG,
2759
+
.mask = PMX_SSP2_PORT_SEL_MASK,
2760
+
.val = PMX_SSP2_PORT_13_TO_16_VAL,
2761
+
},
2762
+
};
2763
+
2764
+
static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
2765
+
{
2766
+
.reg = PMX_CONFIG_REG,
2767
+
.mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
2768
+
PMX_GPIO_PIN5_MASK,
2769
+
.val = 0,
2770
+
}, {
2771
+
.reg = IP_SEL_PAD_30_39_REG,
2772
+
.mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
2773
+
.val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
2774
+
PMX_SSP2_PL_35_VAL,
2775
+
}, {
2776
+
.reg = IP_SEL_MIX_PAD_REG,
2777
+
.mask = PMX_SSP2_PORT_SEL_MASK,
2778
+
.val = PMX_SSP2_PORT_32_TO_35_VAL,
2779
+
},
2780
+
};
2781
+
2782
+
static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
2783
+
{
2784
+
.reg = PMX_CONFIG_REG,
2785
+
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2786
+
.val = 0,
2787
+
}, {
2788
+
.reg = IP_SEL_PAD_40_49_REG,
2789
+
.mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
2790
+
.val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
2791
+
}, {
2792
+
.reg = IP_SEL_MIX_PAD_REG,
2793
+
.mask = PMX_SSP2_PORT_SEL_MASK,
2794
+
.val = PMX_SSP2_PORT_44_TO_47_VAL,
2795
+
},
2796
+
};
2797
+
2798
+
static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
2799
+
{
2800
+
.reg = IP_SEL_PAD_60_69_REG,
2801
+
.mask = PMX_PL_61_TO_64_MASK,
2802
+
.val = PMX_SSP2_PL_61_TO_64_VAL,
2803
+
}, {
2804
+
.reg = IP_SEL_MIX_PAD_REG,
2805
+
.mask = PMX_SSP2_PORT_SEL_MASK,
2806
+
.val = PMX_SSP2_PORT_61_TO_64_VAL,
2807
+
},
2808
+
};
2809
+
2810
+
static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
2811
+
{
2812
+
.reg = IP_SEL_PAD_90_99_REG,
2813
+
.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
2814
+
.val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
2815
+
}, {
2816
+
.reg = IP_SEL_MIX_PAD_REG,
2817
+
.mask = PMX_SSP2_PORT_SEL_MASK,
2818
+
.val = PMX_SSP2_PORT_90_TO_93_VAL,
2819
+
},
2820
+
};
2821
+
2822
+
static struct spear_modemux ssp2_13_16_modemux[] = {
2823
+
{
2824
+
.modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
2825
+
.muxregs = ssp2_muxreg,
2826
+
.nmuxregs = ARRAY_SIZE(ssp2_muxreg),
2827
+
}, {
2828
+
.modes = EXTENDED_MODE,
2829
+
.muxregs = ssp2_ext_13_16_muxreg,
2830
+
.nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
2831
+
},
2832
+
};
2833
+
2834
+
static struct spear_modemux ssp2_32_35_modemux[] = {
2835
+
{
2836
+
.modes = EXTENDED_MODE,
2837
+
.muxregs = ssp2_ext_32_35_muxreg,
2838
+
.nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
2839
+
},
2840
+
};
2841
+
2842
+
static struct spear_modemux ssp2_44_47_modemux[] = {
2843
+
{
2844
+
.modes = EXTENDED_MODE,
2845
+
.muxregs = ssp2_ext_44_47_muxreg,
2846
+
.nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
2847
+
},
2848
+
};
2849
+
2850
+
static struct spear_modemux ssp2_61_64_modemux[] = {
2851
+
{
2852
+
.modes = EXTENDED_MODE,
2853
+
.muxregs = ssp2_ext_61_64_muxreg,
2854
+
.nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
2855
+
},
2856
+
};
2857
+
2858
+
static struct spear_modemux ssp2_90_93_modemux[] = {
2859
+
{
2860
+
.modes = EXTENDED_MODE,
2861
+
.muxregs = ssp2_ext_90_93_muxreg,
2862
+
.nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
2863
+
},
2864
+
};
2865
+
2866
+
static struct spear_pingroup ssp2_pingroup[] = {
2867
+
{
2868
+
.name = "ssp2_13_16_grp",
2869
+
.pins = ssp2_pins[0],
2870
+
.npins = ARRAY_SIZE(ssp2_pins[0]),
2871
+
.modemuxs = ssp2_13_16_modemux,
2872
+
.nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
2873
+
}, {
2874
+
.name = "ssp2_32_35_grp",
2875
+
.pins = ssp2_pins[1],
2876
+
.npins = ARRAY_SIZE(ssp2_pins[1]),
2877
+
.modemuxs = ssp2_32_35_modemux,
2878
+
.nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
2879
+
}, {
2880
+
.name = "ssp2_44_47_grp",
2881
+
.pins = ssp2_pins[2],
2882
+
.npins = ARRAY_SIZE(ssp2_pins[2]),
2883
+
.modemuxs = ssp2_44_47_modemux,
2884
+
.nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
2885
+
}, {
2886
+
.name = "ssp2_61_64_grp",
2887
+
.pins = ssp2_pins[3],
2888
+
.npins = ARRAY_SIZE(ssp2_pins[3]),
2889
+
.modemuxs = ssp2_61_64_modemux,
2890
+
.nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
2891
+
}, {
2892
+
.name = "ssp2_90_93_grp",
2893
+
.pins = ssp2_pins[4],
2894
+
.npins = ARRAY_SIZE(ssp2_pins[4]),
2895
+
.modemuxs = ssp2_90_93_modemux,
2896
+
.nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
2897
+
},
2898
+
};
2899
+
2900
+
static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
2901
+
"ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
2902
+
static struct spear_function ssp2_function = {
2903
+
.name = "ssp2",
2904
+
.groups = ssp2_grps,
2905
+
.ngroups = ARRAY_SIZE(ssp2_grps),
2906
+
};
2907
+
2908
+
/* Pad multiplexing for cadence mii2 as mii device */
2909
+
static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
2910
+
90, 91, 92, 93, 94, 95, 96, 97 };
2911
+
static struct spear_muxreg mii2_muxreg[] = {
2912
+
{
2913
+
.reg = IP_SEL_PAD_80_89_REG,
2914
+
.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
2915
+
PMX_PL_88_89_MASK,
2916
+
.val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
2917
+
PMX_MII2_PL_88_89_VAL,
2918
+
}, {
2919
+
.reg = IP_SEL_PAD_90_99_REG,
2920
+
.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
2921
+
PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2922
+
.val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
2923
+
PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
2924
+
}, {
2925
+
.reg = EXT_CTRL_REG,
2926
+
.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2927
+
(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2928
+
MII_MDIO_MASK,
2929
+
.val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
2930
+
(MAC_MODE_MII << MAC1_MODE_SHIFT) |
2931
+
MII_MDIO_81_VAL,
2932
+
},
2933
+
};
2934
+
2935
+
static struct spear_modemux mii2_modemux[] = {
2936
+
{
2937
+
.modes = EXTENDED_MODE,
2938
+
.muxregs = mii2_muxreg,
2939
+
.nmuxregs = ARRAY_SIZE(mii2_muxreg),
2940
+
},
2941
+
};
2942
+
2943
+
static struct spear_pingroup mii2_pingroup = {
2944
+
.name = "mii2_grp",
2945
+
.pins = mii2_pins,
2946
+
.npins = ARRAY_SIZE(mii2_pins),
2947
+
.modemuxs = mii2_modemux,
2948
+
.nmodemuxs = ARRAY_SIZE(mii2_modemux),
2949
+
};
2950
+
2951
+
static const char *const mii2_grps[] = { "mii2_grp" };
2952
+
static struct spear_function mii2_function = {
2953
+
.name = "mii2",
2954
+
.groups = mii2_grps,
2955
+
.ngroups = ARRAY_SIZE(mii2_grps),
2956
+
};
2957
+
2958
+
/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
2959
+
static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
2960
+
21, 22, 23, 24, 25, 26, 27 };
2961
+
static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
2962
+
static struct spear_muxreg mii0_1_muxreg[] = {
2963
+
{
2964
+
.reg = PMX_CONFIG_REG,
2965
+
.mask = PMX_MII_MASK,
2966
+
.val = 0,
2967
+
},
2968
+
};
2969
+
2970
+
static struct spear_muxreg smii0_1_ext_muxreg[] = {
2971
+
{
2972
+
.reg = IP_SEL_PAD_10_19_REG,
2973
+
.mask = PMX_PL_10_11_MASK,
2974
+
.val = PMX_SMII_PL_10_11_VAL,
2975
+
}, {
2976
+
.reg = IP_SEL_PAD_20_29_REG,
2977
+
.mask = PMX_PL_21_TO_27_MASK,
2978
+
.val = PMX_SMII_PL_21_TO_27_VAL,
2979
+
}, {
2980
+
.reg = EXT_CTRL_REG,
2981
+
.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2982
+
(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2983
+
MII_MDIO_MASK,
2984
+
.val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
2985
+
| (MAC_MODE_SMII << MAC1_MODE_SHIFT)
2986
+
| MII_MDIO_10_11_VAL,
2987
+
},
2988
+
};
2989
+
2990
+
static struct spear_muxreg rmii0_1_ext_muxreg[] = {
2991
+
{
2992
+
.reg = IP_SEL_PAD_10_19_REG,
2993
+
.mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
2994
+
PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2995
+
.val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
2996
+
PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
2997
+
PMX_RMII_PL_19_VAL,
2998
+
}, {
2999
+
.reg = IP_SEL_PAD_20_29_REG,
3000
+
.mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
3001
+
.val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
3002
+
}, {
3003
+
.reg = EXT_CTRL_REG,
3004
+
.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
3005
+
(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
3006
+
MII_MDIO_MASK,
3007
+
.val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
3008
+
| (MAC_MODE_RMII << MAC1_MODE_SHIFT)
3009
+
| MII_MDIO_10_11_VAL,
3010
+
},
3011
+
};
3012
+
3013
+
static struct spear_modemux mii0_1_modemux[][2] = {
3014
+
{
3015
+
/* configure as smii */
3016
+
{
3017
+
.modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3018
+
SMALL_PRINTERS_MODE | EXTENDED_MODE,
3019
+
.muxregs = mii0_1_muxreg,
3020
+
.nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3021
+
}, {
3022
+
.modes = EXTENDED_MODE,
3023
+
.muxregs = smii0_1_ext_muxreg,
3024
+
.nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
3025
+
},
3026
+
}, {
3027
+
/* configure as rmii */
3028
+
{
3029
+
.modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3030
+
SMALL_PRINTERS_MODE | EXTENDED_MODE,
3031
+
.muxregs = mii0_1_muxreg,
3032
+
.nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3033
+
}, {
3034
+
.modes = EXTENDED_MODE,
3035
+
.muxregs = rmii0_1_ext_muxreg,
3036
+
.nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
3037
+
},
3038
+
},
3039
+
};
3040
+
3041
+
static struct spear_pingroup mii0_1_pingroup[] = {
3042
+
{
3043
+
.name = "smii0_1_grp",
3044
+
.pins = smii0_1_pins,
3045
+
.npins = ARRAY_SIZE(smii0_1_pins),
3046
+
.modemuxs = mii0_1_modemux[0],
3047
+
.nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
3048
+
}, {
3049
+
.name = "rmii0_1_grp",
3050
+
.pins = rmii0_1_pins,
3051
+
.npins = ARRAY_SIZE(rmii0_1_pins),
3052
+
.modemuxs = mii0_1_modemux[1],
3053
+
.nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
3054
+
},
3055
+
};
3056
+
3057
+
static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
3058
+
static struct spear_function mii0_1_function = {
3059
+
.name = "mii0_1",
3060
+
.groups = mii0_1_grps,
3061
+
.ngroups = ARRAY_SIZE(mii0_1_grps),
3062
+
};
3063
+
3064
+
/* Pad multiplexing for i2c1 device */
3065
+
static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
3066
+
static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
3067
+
{
3068
+
.reg = PMX_CONFIG_REG,
3069
+
.mask = PMX_SSP_CS_MASK,
3070
+
.val = 0,
3071
+
}, {
3072
+
.reg = IP_SEL_PAD_0_9_REG,
3073
+
.mask = PMX_PL_8_9_MASK,
3074
+
.val = PMX_I2C1_PL_8_9_VAL,
3075
+
}, {
3076
+
.reg = IP_SEL_MIX_PAD_REG,
3077
+
.mask = PMX_I2C1_PORT_SEL_MASK,
3078
+
.val = PMX_I2C1_PORT_8_9_VAL,
3079
+
},
3080
+
};
3081
+
3082
+
static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
3083
+
{
3084
+
.reg = IP_SEL_PAD_90_99_REG,
3085
+
.mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
3086
+
.val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
3087
+
}, {
3088
+
.reg = IP_SEL_MIX_PAD_REG,
3089
+
.mask = PMX_I2C1_PORT_SEL_MASK,
3090
+
.val = PMX_I2C1_PORT_98_99_VAL,
3091
+
},
3092
+
};
3093
+
3094
+
static struct spear_modemux i2c1_modemux[][1] = {
3095
+
{
3096
+
/* Select signals on pins 8-9 */
3097
+
{
3098
+
.modes = EXTENDED_MODE,
3099
+
.muxregs = i2c1_ext_8_9_muxreg,
3100
+
.nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
3101
+
},
3102
+
}, {
3103
+
/* Select signals on pins 98-99 */
3104
+
{
3105
+
.modes = EXTENDED_MODE,
3106
+
.muxregs = i2c1_ext_98_99_muxreg,
3107
+
.nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
3108
+
},
3109
+
},
3110
+
};
3111
+
3112
+
static struct spear_pingroup i2c1_pingroup[] = {
3113
+
{
3114
+
.name = "i2c1_8_9_grp",
3115
+
.pins = i2c1_pins[0],
3116
+
.npins = ARRAY_SIZE(i2c1_pins[0]),
3117
+
.modemuxs = i2c1_modemux[0],
3118
+
.nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
3119
+
}, {
3120
+
.name = "i2c1_98_99_grp",
3121
+
.pins = i2c1_pins[1],
3122
+
.npins = ARRAY_SIZE(i2c1_pins[1]),
3123
+
.modemuxs = i2c1_modemux[1],
3124
+
.nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
3125
+
},
3126
+
};
3127
+
3128
+
static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
3129
+
static struct spear_function i2c1_function = {
3130
+
.name = "i2c1",
3131
+
.groups = i2c1_grps,
3132
+
.ngroups = ARRAY_SIZE(i2c1_grps),
3133
+
};
3134
+
3135
+
/* Pad multiplexing for i2c2 device */
3136
+
static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
3137
+
{ 75, 76 }, { 96, 97 } };
3138
+
static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
3139
+
{
3140
+
.reg = PMX_CONFIG_REG,
3141
+
.mask = PMX_FIRDA_MASK,
3142
+
.val = 0,
3143
+
}, {
3144
+
.reg = IP_SEL_PAD_0_9_REG,
3145
+
.mask = PMX_PL_0_1_MASK,
3146
+
.val = PMX_I2C2_PL_0_1_VAL,
3147
+
}, {
3148
+
.reg = IP_SEL_MIX_PAD_REG,
3149
+
.mask = PMX_I2C2_PORT_SEL_MASK,
3150
+
.val = PMX_I2C2_PORT_0_1_VAL,
3151
+
},
3152
+
};
3153
+
3154
+
static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
3155
+
{
3156
+
.reg = PMX_CONFIG_REG,
3157
+
.mask = PMX_UART0_MASK,
3158
+
.val = 0,
3159
+
}, {
3160
+
.reg = IP_SEL_PAD_0_9_REG,
3161
+
.mask = PMX_PL_2_3_MASK,
3162
+
.val = PMX_I2C2_PL_2_3_VAL,
3163
+
}, {
3164
+
.reg = IP_SEL_MIX_PAD_REG,
3165
+
.mask = PMX_I2C2_PORT_SEL_MASK,
3166
+
.val = PMX_I2C2_PORT_2_3_VAL,
3167
+
},
3168
+
};
3169
+
3170
+
static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
3171
+
{
3172
+
.reg = PMX_CONFIG_REG,
3173
+
.mask = PMX_MII_MASK,
3174
+
.val = 0,
3175
+
}, {
3176
+
.reg = IP_SEL_PAD_10_19_REG,
3177
+
.mask = PMX_PL_19_MASK,
3178
+
.val = PMX_I2C2_PL_19_VAL,
3179
+
}, {
3180
+
.reg = IP_SEL_PAD_20_29_REG,
3181
+
.mask = PMX_PL_20_MASK,
3182
+
.val = PMX_I2C2_PL_20_VAL,
3183
+
}, {
3184
+
.reg = IP_SEL_MIX_PAD_REG,
3185
+
.mask = PMX_I2C2_PORT_SEL_MASK,
3186
+
.val = PMX_I2C2_PORT_19_20_VAL,
3187
+
},
3188
+
};
3189
+
3190
+
static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
3191
+
{
3192
+
.reg = IP_SEL_PAD_70_79_REG,
3193
+
.mask = PMX_PL_75_76_MASK,
3194
+
.val = PMX_I2C2_PL_75_76_VAL,
3195
+
}, {
3196
+
.reg = IP_SEL_MIX_PAD_REG,
3197
+
.mask = PMX_I2C2_PORT_SEL_MASK,
3198
+
.val = PMX_I2C2_PORT_75_76_VAL,
3199
+
},
3200
+
};
3201
+
3202
+
static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
3203
+
{
3204
+
.reg = IP_SEL_PAD_90_99_REG,
3205
+
.mask = PMX_PL_96_97_MASK,
3206
+
.val = PMX_I2C2_PL_96_97_VAL,
3207
+
}, {
3208
+
.reg = IP_SEL_MIX_PAD_REG,
3209
+
.mask = PMX_I2C2_PORT_SEL_MASK,
3210
+
.val = PMX_I2C2_PORT_96_97_VAL,
3211
+
},
3212
+
};
3213
+
3214
+
static struct spear_modemux i2c2_modemux[][1] = {
3215
+
{
3216
+
/* Select signals on pins 0_1 */
3217
+
{
3218
+
.modes = EXTENDED_MODE,
3219
+
.muxregs = i2c2_ext_0_1_muxreg,
3220
+
.nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
3221
+
},
3222
+
}, {
3223
+
/* Select signals on pins 2_3 */
3224
+
{
3225
+
.modes = EXTENDED_MODE,
3226
+
.muxregs = i2c2_ext_2_3_muxreg,
3227
+
.nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
3228
+
},
3229
+
}, {
3230
+
/* Select signals on pins 19_20 */
3231
+
{
3232
+
.modes = EXTENDED_MODE,
3233
+
.muxregs = i2c2_ext_19_20_muxreg,
3234
+
.nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
3235
+
},
3236
+
}, {
3237
+
/* Select signals on pins 75_76 */
3238
+
{
3239
+
.modes = EXTENDED_MODE,
3240
+
.muxregs = i2c2_ext_75_76_muxreg,
3241
+
.nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
3242
+
},
3243
+
}, {
3244
+
/* Select signals on pins 96_97 */
3245
+
{
3246
+
.modes = EXTENDED_MODE,
3247
+
.muxregs = i2c2_ext_96_97_muxreg,
3248
+
.nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
3249
+
},
3250
+
},
3251
+
};
3252
+
3253
+
static struct spear_pingroup i2c2_pingroup[] = {
3254
+
{
3255
+
.name = "i2c2_0_1_grp",
3256
+
.pins = i2c2_pins[0],
3257
+
.npins = ARRAY_SIZE(i2c2_pins[0]),
3258
+
.modemuxs = i2c2_modemux[0],
3259
+
.nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
3260
+
}, {
3261
+
.name = "i2c2_2_3_grp",
3262
+
.pins = i2c2_pins[1],
3263
+
.npins = ARRAY_SIZE(i2c2_pins[1]),
3264
+
.modemuxs = i2c2_modemux[1],
3265
+
.nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
3266
+
}, {
3267
+
.name = "i2c2_19_20_grp",
3268
+
.pins = i2c2_pins[2],
3269
+
.npins = ARRAY_SIZE(i2c2_pins[2]),
3270
+
.modemuxs = i2c2_modemux[2],
3271
+
.nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
3272
+
}, {
3273
+
.name = "i2c2_75_76_grp",
3274
+
.pins = i2c2_pins[3],
3275
+
.npins = ARRAY_SIZE(i2c2_pins[3]),
3276
+
.modemuxs = i2c2_modemux[3],
3277
+
.nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
3278
+
}, {
3279
+
.name = "i2c2_96_97_grp",
3280
+
.pins = i2c2_pins[4],
3281
+
.npins = ARRAY_SIZE(i2c2_pins[4]),
3282
+
.modemuxs = i2c2_modemux[4],
3283
+
.nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
3284
+
},
3285
+
};
3286
+
3287
+
static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
3288
+
"i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
3289
+
static struct spear_function i2c2_function = {
3290
+
.name = "i2c2",
3291
+
.groups = i2c2_grps,
3292
+
.ngroups = ARRAY_SIZE(i2c2_grps),
3293
+
};
3294
+
3295
+
/* pingroups */
3296
+
static struct spear_pingroup *spear320_pingroups[] = {
3297
+
SPEAR3XX_COMMON_PINGROUPS,
3298
+
&clcd_pingroup,
3299
+
&emi_pingroup,
3300
+
&fsmc_8bit_pingroup,
3301
+
&fsmc_16bit_pingroup,
3302
+
&spp_pingroup,
3303
+
&sdhci_led_pingroup,
3304
+
&sdhci_pingroup[0],
3305
+
&sdhci_pingroup[1],
3306
+
&i2s_pingroup,
3307
+
&uart1_pingroup,
3308
+
&uart1_modem_pingroup[0],
3309
+
&uart1_modem_pingroup[1],
3310
+
&uart1_modem_pingroup[2],
3311
+
&uart1_modem_pingroup[3],
3312
+
&uart2_pingroup,
3313
+
&uart3_pingroup[0],
3314
+
&uart3_pingroup[1],
3315
+
&uart3_pingroup[2],
3316
+
&uart3_pingroup[3],
3317
+
&uart3_pingroup[4],
3318
+
&uart3_pingroup[5],
3319
+
&uart3_pingroup[6],
3320
+
&uart4_pingroup[0],
3321
+
&uart4_pingroup[1],
3322
+
&uart4_pingroup[2],
3323
+
&uart4_pingroup[3],
3324
+
&uart4_pingroup[4],
3325
+
&uart4_pingroup[5],
3326
+
&uart5_pingroup[0],
3327
+
&uart5_pingroup[1],
3328
+
&uart5_pingroup[2],
3329
+
&uart5_pingroup[3],
3330
+
&uart6_pingroup[0],
3331
+
&uart6_pingroup[1],
3332
+
&rs485_pingroup,
3333
+
&touchscreen_pingroup,
3334
+
&can0_pingroup,
3335
+
&can1_pingroup,
3336
+
&pwm0_1_pingroup[0],
3337
+
&pwm0_1_pingroup[1],
3338
+
&pwm0_1_pingroup[2],
3339
+
&pwm0_1_pingroup[3],
3340
+
&pwm0_1_pingroup[4],
3341
+
&pwm0_1_pingroup[5],
3342
+
&pwm0_1_pingroup[6],
3343
+
&pwm2_pingroup[0],
3344
+
&pwm2_pingroup[1],
3345
+
&pwm2_pingroup[2],
3346
+
&pwm2_pingroup[3],
3347
+
&pwm2_pingroup[4],
3348
+
&pwm2_pingroup[5],
3349
+
&pwm2_pingroup[6],
3350
+
&pwm3_pingroup[0],
3351
+
&pwm3_pingroup[1],
3352
+
&pwm3_pingroup[2],
3353
+
&pwm3_pingroup[3],
3354
+
&pwm3_pingroup[4],
3355
+
&pwm3_pingroup[5],
3356
+
&ssp1_pingroup[0],
3357
+
&ssp1_pingroup[1],
3358
+
&ssp1_pingroup[2],
3359
+
&ssp1_pingroup[3],
3360
+
&ssp1_pingroup[4],
3361
+
&ssp2_pingroup[0],
3362
+
&ssp2_pingroup[1],
3363
+
&ssp2_pingroup[2],
3364
+
&ssp2_pingroup[3],
3365
+
&ssp2_pingroup[4],
3366
+
&mii2_pingroup,
3367
+
&mii0_1_pingroup[0],
3368
+
&mii0_1_pingroup[1],
3369
+
&i2c1_pingroup[0],
3370
+
&i2c1_pingroup[1],
3371
+
&i2c2_pingroup[0],
3372
+
&i2c2_pingroup[1],
3373
+
&i2c2_pingroup[2],
3374
+
&i2c2_pingroup[3],
3375
+
&i2c2_pingroup[4],
3376
+
};
3377
+
3378
+
/* functions */
3379
+
static struct spear_function *spear320_functions[] = {
3380
+
SPEAR3XX_COMMON_FUNCTIONS,
3381
+
&clcd_function,
3382
+
&emi_function,
3383
+
&fsmc_function,
3384
+
&spp_function,
3385
+
&sdhci_function,
3386
+
&i2s_function,
3387
+
&uart1_function,
3388
+
&uart1_modem_function,
3389
+
&uart2_function,
3390
+
&uart3_function,
3391
+
&uart4_function,
3392
+
&uart5_function,
3393
+
&uart6_function,
3394
+
&rs485_function,
3395
+
&touchscreen_function,
3396
+
&can0_function,
3397
+
&can1_function,
3398
+
&pwm0_1_function,
3399
+
&pwm2_function,
3400
+
&pwm3_function,
3401
+
&ssp1_function,
3402
+
&ssp2_function,
3403
+
&mii2_function,
3404
+
&mii0_1_function,
3405
+
&i2c1_function,
3406
+
&i2c2_function,
3407
+
};
3408
+
3409
+
static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = {
3410
+
{
3411
+
.compatible = "st,spear320-pinmux",
3412
+
},
3413
+
{},
3414
+
};
3415
+
3416
+
static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
3417
+
{
3418
+
int ret;
3419
+
3420
+
spear3xx_machdata.groups = spear320_pingroups;
3421
+
spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
3422
+
spear3xx_machdata.functions = spear320_functions;
3423
+
spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
3424
+
3425
+
spear3xx_machdata.modes_supported = true;
3426
+
spear3xx_machdata.pmx_modes = spear320_pmx_modes;
3427
+
spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
3428
+
3429
+
pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
3430
+
3431
+
ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
3432
+
if (ret)
3433
+
return ret;
3434
+
3435
+
return 0;
3436
+
}
3437
+
3438
+
static int __devexit spear320_pinctrl_remove(struct platform_device *pdev)
3439
+
{
3440
+
return spear_pinctrl_remove(pdev);
3441
+
}
3442
+
3443
+
static struct platform_driver spear320_pinctrl_driver = {
3444
+
.driver = {
3445
+
.name = DRIVER_NAME,
3446
+
.owner = THIS_MODULE,
3447
+
.of_match_table = spear320_pinctrl_of_match,
3448
+
},
3449
+
.probe = spear320_pinctrl_probe,
3450
+
.remove = __devexit_p(spear320_pinctrl_remove),
3451
+
};
3452
+
3453
+
static int __init spear320_pinctrl_init(void)
3454
+
{
3455
+
return platform_driver_register(&spear320_pinctrl_driver);
3456
+
}
3457
+
arch_initcall(spear320_pinctrl_init);
3458
+
3459
+
static void __exit spear320_pinctrl_exit(void)
3460
+
{
3461
+
platform_driver_unregister(&spear320_pinctrl_driver);
3462
+
}
3463
+
module_exit(spear320_pinctrl_exit);
3464
+
3465
+
MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
3466
+
MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
3467
+
MODULE_LICENSE("GPL v2");
3468
+
MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);
+588
drivers/pinctrl/spear/pinctrl-spear3xx.c
+588
drivers/pinctrl/spear/pinctrl-spear3xx.c
···
1
+
/*
2
+
* Driver for the ST Microelectronics SPEAr3xx pinmux
3
+
*
4
+
* Copyright (C) 2012 ST Microelectronics
5
+
* Viresh Kumar <viresh.kumar@st.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#include <linux/pinctrl/pinctrl.h>
13
+
14
+
#include "pinctrl-spear3xx.h"
15
+
16
+
/* pins */
17
+
static const struct pinctrl_pin_desc spear3xx_pins[] = {
18
+
PINCTRL_PIN(0, "PLGPIO0"),
19
+
PINCTRL_PIN(1, "PLGPIO1"),
20
+
PINCTRL_PIN(2, "PLGPIO2"),
21
+
PINCTRL_PIN(3, "PLGPIO3"),
22
+
PINCTRL_PIN(4, "PLGPIO4"),
23
+
PINCTRL_PIN(5, "PLGPIO5"),
24
+
PINCTRL_PIN(6, "PLGPIO6"),
25
+
PINCTRL_PIN(7, "PLGPIO7"),
26
+
PINCTRL_PIN(8, "PLGPIO8"),
27
+
PINCTRL_PIN(9, "PLGPIO9"),
28
+
PINCTRL_PIN(10, "PLGPIO10"),
29
+
PINCTRL_PIN(11, "PLGPIO11"),
30
+
PINCTRL_PIN(12, "PLGPIO12"),
31
+
PINCTRL_PIN(13, "PLGPIO13"),
32
+
PINCTRL_PIN(14, "PLGPIO14"),
33
+
PINCTRL_PIN(15, "PLGPIO15"),
34
+
PINCTRL_PIN(16, "PLGPIO16"),
35
+
PINCTRL_PIN(17, "PLGPIO17"),
36
+
PINCTRL_PIN(18, "PLGPIO18"),
37
+
PINCTRL_PIN(19, "PLGPIO19"),
38
+
PINCTRL_PIN(20, "PLGPIO20"),
39
+
PINCTRL_PIN(21, "PLGPIO21"),
40
+
PINCTRL_PIN(22, "PLGPIO22"),
41
+
PINCTRL_PIN(23, "PLGPIO23"),
42
+
PINCTRL_PIN(24, "PLGPIO24"),
43
+
PINCTRL_PIN(25, "PLGPIO25"),
44
+
PINCTRL_PIN(26, "PLGPIO26"),
45
+
PINCTRL_PIN(27, "PLGPIO27"),
46
+
PINCTRL_PIN(28, "PLGPIO28"),
47
+
PINCTRL_PIN(29, "PLGPIO29"),
48
+
PINCTRL_PIN(30, "PLGPIO30"),
49
+
PINCTRL_PIN(31, "PLGPIO31"),
50
+
PINCTRL_PIN(32, "PLGPIO32"),
51
+
PINCTRL_PIN(33, "PLGPIO33"),
52
+
PINCTRL_PIN(34, "PLGPIO34"),
53
+
PINCTRL_PIN(35, "PLGPIO35"),
54
+
PINCTRL_PIN(36, "PLGPIO36"),
55
+
PINCTRL_PIN(37, "PLGPIO37"),
56
+
PINCTRL_PIN(38, "PLGPIO38"),
57
+
PINCTRL_PIN(39, "PLGPIO39"),
58
+
PINCTRL_PIN(40, "PLGPIO40"),
59
+
PINCTRL_PIN(41, "PLGPIO41"),
60
+
PINCTRL_PIN(42, "PLGPIO42"),
61
+
PINCTRL_PIN(43, "PLGPIO43"),
62
+
PINCTRL_PIN(44, "PLGPIO44"),
63
+
PINCTRL_PIN(45, "PLGPIO45"),
64
+
PINCTRL_PIN(46, "PLGPIO46"),
65
+
PINCTRL_PIN(47, "PLGPIO47"),
66
+
PINCTRL_PIN(48, "PLGPIO48"),
67
+
PINCTRL_PIN(49, "PLGPIO49"),
68
+
PINCTRL_PIN(50, "PLGPIO50"),
69
+
PINCTRL_PIN(51, "PLGPIO51"),
70
+
PINCTRL_PIN(52, "PLGPIO52"),
71
+
PINCTRL_PIN(53, "PLGPIO53"),
72
+
PINCTRL_PIN(54, "PLGPIO54"),
73
+
PINCTRL_PIN(55, "PLGPIO55"),
74
+
PINCTRL_PIN(56, "PLGPIO56"),
75
+
PINCTRL_PIN(57, "PLGPIO57"),
76
+
PINCTRL_PIN(58, "PLGPIO58"),
77
+
PINCTRL_PIN(59, "PLGPIO59"),
78
+
PINCTRL_PIN(60, "PLGPIO60"),
79
+
PINCTRL_PIN(61, "PLGPIO61"),
80
+
PINCTRL_PIN(62, "PLGPIO62"),
81
+
PINCTRL_PIN(63, "PLGPIO63"),
82
+
PINCTRL_PIN(64, "PLGPIO64"),
83
+
PINCTRL_PIN(65, "PLGPIO65"),
84
+
PINCTRL_PIN(66, "PLGPIO66"),
85
+
PINCTRL_PIN(67, "PLGPIO67"),
86
+
PINCTRL_PIN(68, "PLGPIO68"),
87
+
PINCTRL_PIN(69, "PLGPIO69"),
88
+
PINCTRL_PIN(70, "PLGPIO70"),
89
+
PINCTRL_PIN(71, "PLGPIO71"),
90
+
PINCTRL_PIN(72, "PLGPIO72"),
91
+
PINCTRL_PIN(73, "PLGPIO73"),
92
+
PINCTRL_PIN(74, "PLGPIO74"),
93
+
PINCTRL_PIN(75, "PLGPIO75"),
94
+
PINCTRL_PIN(76, "PLGPIO76"),
95
+
PINCTRL_PIN(77, "PLGPIO77"),
96
+
PINCTRL_PIN(78, "PLGPIO78"),
97
+
PINCTRL_PIN(79, "PLGPIO79"),
98
+
PINCTRL_PIN(80, "PLGPIO80"),
99
+
PINCTRL_PIN(81, "PLGPIO81"),
100
+
PINCTRL_PIN(82, "PLGPIO82"),
101
+
PINCTRL_PIN(83, "PLGPIO83"),
102
+
PINCTRL_PIN(84, "PLGPIO84"),
103
+
PINCTRL_PIN(85, "PLGPIO85"),
104
+
PINCTRL_PIN(86, "PLGPIO86"),
105
+
PINCTRL_PIN(87, "PLGPIO87"),
106
+
PINCTRL_PIN(88, "PLGPIO88"),
107
+
PINCTRL_PIN(89, "PLGPIO89"),
108
+
PINCTRL_PIN(90, "PLGPIO90"),
109
+
PINCTRL_PIN(91, "PLGPIO91"),
110
+
PINCTRL_PIN(92, "PLGPIO92"),
111
+
PINCTRL_PIN(93, "PLGPIO93"),
112
+
PINCTRL_PIN(94, "PLGPIO94"),
113
+
PINCTRL_PIN(95, "PLGPIO95"),
114
+
PINCTRL_PIN(96, "PLGPIO96"),
115
+
PINCTRL_PIN(97, "PLGPIO97"),
116
+
PINCTRL_PIN(98, "PLGPIO98"),
117
+
PINCTRL_PIN(99, "PLGPIO99"),
118
+
PINCTRL_PIN(100, "PLGPIO100"),
119
+
PINCTRL_PIN(101, "PLGPIO101"),
120
+
};
121
+
122
+
/* firda_pins */
123
+
static const unsigned firda_pins[] = { 0, 1 };
124
+
static struct spear_muxreg firda_muxreg[] = {
125
+
{
126
+
.reg = -1,
127
+
.mask = PMX_FIRDA_MASK,
128
+
.val = PMX_FIRDA_MASK,
129
+
},
130
+
};
131
+
132
+
static struct spear_modemux firda_modemux[] = {
133
+
{
134
+
.modes = ~0,
135
+
.muxregs = firda_muxreg,
136
+
.nmuxregs = ARRAY_SIZE(firda_muxreg),
137
+
},
138
+
};
139
+
140
+
struct spear_pingroup spear3xx_firda_pingroup = {
141
+
.name = "firda_grp",
142
+
.pins = firda_pins,
143
+
.npins = ARRAY_SIZE(firda_pins),
144
+
.modemuxs = firda_modemux,
145
+
.nmodemuxs = ARRAY_SIZE(firda_modemux),
146
+
};
147
+
148
+
static const char *const firda_grps[] = { "firda_grp" };
149
+
struct spear_function spear3xx_firda_function = {
150
+
.name = "firda",
151
+
.groups = firda_grps,
152
+
.ngroups = ARRAY_SIZE(firda_grps),
153
+
};
154
+
155
+
/* i2c_pins */
156
+
static const unsigned i2c_pins[] = { 4, 5 };
157
+
static struct spear_muxreg i2c_muxreg[] = {
158
+
{
159
+
.reg = -1,
160
+
.mask = PMX_I2C_MASK,
161
+
.val = PMX_I2C_MASK,
162
+
},
163
+
};
164
+
165
+
static struct spear_modemux i2c_modemux[] = {
166
+
{
167
+
.modes = ~0,
168
+
.muxregs = i2c_muxreg,
169
+
.nmuxregs = ARRAY_SIZE(i2c_muxreg),
170
+
},
171
+
};
172
+
173
+
struct spear_pingroup spear3xx_i2c_pingroup = {
174
+
.name = "i2c0_grp",
175
+
.pins = i2c_pins,
176
+
.npins = ARRAY_SIZE(i2c_pins),
177
+
.modemuxs = i2c_modemux,
178
+
.nmodemuxs = ARRAY_SIZE(i2c_modemux),
179
+
};
180
+
181
+
static const char *const i2c_grps[] = { "i2c0_grp" };
182
+
struct spear_function spear3xx_i2c_function = {
183
+
.name = "i2c0",
184
+
.groups = i2c_grps,
185
+
.ngroups = ARRAY_SIZE(i2c_grps),
186
+
};
187
+
188
+
/* ssp_cs_pins */
189
+
static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
190
+
static struct spear_muxreg ssp_cs_muxreg[] = {
191
+
{
192
+
.reg = -1,
193
+
.mask = PMX_SSP_CS_MASK,
194
+
.val = PMX_SSP_CS_MASK,
195
+
},
196
+
};
197
+
198
+
static struct spear_modemux ssp_cs_modemux[] = {
199
+
{
200
+
.modes = ~0,
201
+
.muxregs = ssp_cs_muxreg,
202
+
.nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
203
+
},
204
+
};
205
+
206
+
struct spear_pingroup spear3xx_ssp_cs_pingroup = {
207
+
.name = "ssp_cs_grp",
208
+
.pins = ssp_cs_pins,
209
+
.npins = ARRAY_SIZE(ssp_cs_pins),
210
+
.modemuxs = ssp_cs_modemux,
211
+
.nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
212
+
};
213
+
214
+
static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
215
+
struct spear_function spear3xx_ssp_cs_function = {
216
+
.name = "ssp_cs",
217
+
.groups = ssp_cs_grps,
218
+
.ngroups = ARRAY_SIZE(ssp_cs_grps),
219
+
};
220
+
221
+
/* ssp_pins */
222
+
static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
223
+
static struct spear_muxreg ssp_muxreg[] = {
224
+
{
225
+
.reg = -1,
226
+
.mask = PMX_SSP_MASK,
227
+
.val = PMX_SSP_MASK,
228
+
},
229
+
};
230
+
231
+
static struct spear_modemux ssp_modemux[] = {
232
+
{
233
+
.modes = ~0,
234
+
.muxregs = ssp_muxreg,
235
+
.nmuxregs = ARRAY_SIZE(ssp_muxreg),
236
+
},
237
+
};
238
+
239
+
struct spear_pingroup spear3xx_ssp_pingroup = {
240
+
.name = "ssp0_grp",
241
+
.pins = ssp_pins,
242
+
.npins = ARRAY_SIZE(ssp_pins),
243
+
.modemuxs = ssp_modemux,
244
+
.nmodemuxs = ARRAY_SIZE(ssp_modemux),
245
+
};
246
+
247
+
static const char *const ssp_grps[] = { "ssp0_grp" };
248
+
struct spear_function spear3xx_ssp_function = {
249
+
.name = "ssp0",
250
+
.groups = ssp_grps,
251
+
.ngroups = ARRAY_SIZE(ssp_grps),
252
+
};
253
+
254
+
/* mii_pins */
255
+
static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
256
+
21, 22, 23, 24, 25, 26, 27 };
257
+
static struct spear_muxreg mii_muxreg[] = {
258
+
{
259
+
.reg = -1,
260
+
.mask = PMX_MII_MASK,
261
+
.val = PMX_MII_MASK,
262
+
},
263
+
};
264
+
265
+
static struct spear_modemux mii_modemux[] = {
266
+
{
267
+
.modes = ~0,
268
+
.muxregs = mii_muxreg,
269
+
.nmuxregs = ARRAY_SIZE(mii_muxreg),
270
+
},
271
+
};
272
+
273
+
struct spear_pingroup spear3xx_mii_pingroup = {
274
+
.name = "mii0_grp",
275
+
.pins = mii_pins,
276
+
.npins = ARRAY_SIZE(mii_pins),
277
+
.modemuxs = mii_modemux,
278
+
.nmodemuxs = ARRAY_SIZE(mii_modemux),
279
+
};
280
+
281
+
static const char *const mii_grps[] = { "mii0_grp" };
282
+
struct spear_function spear3xx_mii_function = {
283
+
.name = "mii0",
284
+
.groups = mii_grps,
285
+
.ngroups = ARRAY_SIZE(mii_grps),
286
+
};
287
+
288
+
/* gpio0_pin0_pins */
289
+
static const unsigned gpio0_pin0_pins[] = { 28 };
290
+
static struct spear_muxreg gpio0_pin0_muxreg[] = {
291
+
{
292
+
.reg = -1,
293
+
.mask = PMX_GPIO_PIN0_MASK,
294
+
.val = PMX_GPIO_PIN0_MASK,
295
+
},
296
+
};
297
+
298
+
static struct spear_modemux gpio0_pin0_modemux[] = {
299
+
{
300
+
.modes = ~0,
301
+
.muxregs = gpio0_pin0_muxreg,
302
+
.nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
303
+
},
304
+
};
305
+
306
+
struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
307
+
.name = "gpio0_pin0_grp",
308
+
.pins = gpio0_pin0_pins,
309
+
.npins = ARRAY_SIZE(gpio0_pin0_pins),
310
+
.modemuxs = gpio0_pin0_modemux,
311
+
.nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
312
+
};
313
+
314
+
/* gpio0_pin1_pins */
315
+
static const unsigned gpio0_pin1_pins[] = { 29 };
316
+
static struct spear_muxreg gpio0_pin1_muxreg[] = {
317
+
{
318
+
.reg = -1,
319
+
.mask = PMX_GPIO_PIN1_MASK,
320
+
.val = PMX_GPIO_PIN1_MASK,
321
+
},
322
+
};
323
+
324
+
static struct spear_modemux gpio0_pin1_modemux[] = {
325
+
{
326
+
.modes = ~0,
327
+
.muxregs = gpio0_pin1_muxreg,
328
+
.nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
329
+
},
330
+
};
331
+
332
+
struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
333
+
.name = "gpio0_pin1_grp",
334
+
.pins = gpio0_pin1_pins,
335
+
.npins = ARRAY_SIZE(gpio0_pin1_pins),
336
+
.modemuxs = gpio0_pin1_modemux,
337
+
.nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
338
+
};
339
+
340
+
/* gpio0_pin2_pins */
341
+
static const unsigned gpio0_pin2_pins[] = { 30 };
342
+
static struct spear_muxreg gpio0_pin2_muxreg[] = {
343
+
{
344
+
.reg = -1,
345
+
.mask = PMX_GPIO_PIN2_MASK,
346
+
.val = PMX_GPIO_PIN2_MASK,
347
+
},
348
+
};
349
+
350
+
static struct spear_modemux gpio0_pin2_modemux[] = {
351
+
{
352
+
.modes = ~0,
353
+
.muxregs = gpio0_pin2_muxreg,
354
+
.nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
355
+
},
356
+
};
357
+
358
+
struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
359
+
.name = "gpio0_pin2_grp",
360
+
.pins = gpio0_pin2_pins,
361
+
.npins = ARRAY_SIZE(gpio0_pin2_pins),
362
+
.modemuxs = gpio0_pin2_modemux,
363
+
.nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
364
+
};
365
+
366
+
/* gpio0_pin3_pins */
367
+
static const unsigned gpio0_pin3_pins[] = { 31 };
368
+
static struct spear_muxreg gpio0_pin3_muxreg[] = {
369
+
{
370
+
.reg = -1,
371
+
.mask = PMX_GPIO_PIN3_MASK,
372
+
.val = PMX_GPIO_PIN3_MASK,
373
+
},
374
+
};
375
+
376
+
static struct spear_modemux gpio0_pin3_modemux[] = {
377
+
{
378
+
.modes = ~0,
379
+
.muxregs = gpio0_pin3_muxreg,
380
+
.nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
381
+
},
382
+
};
383
+
384
+
struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
385
+
.name = "gpio0_pin3_grp",
386
+
.pins = gpio0_pin3_pins,
387
+
.npins = ARRAY_SIZE(gpio0_pin3_pins),
388
+
.modemuxs = gpio0_pin3_modemux,
389
+
.nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
390
+
};
391
+
392
+
/* gpio0_pin4_pins */
393
+
static const unsigned gpio0_pin4_pins[] = { 32 };
394
+
static struct spear_muxreg gpio0_pin4_muxreg[] = {
395
+
{
396
+
.reg = -1,
397
+
.mask = PMX_GPIO_PIN4_MASK,
398
+
.val = PMX_GPIO_PIN4_MASK,
399
+
},
400
+
};
401
+
402
+
static struct spear_modemux gpio0_pin4_modemux[] = {
403
+
{
404
+
.modes = ~0,
405
+
.muxregs = gpio0_pin4_muxreg,
406
+
.nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
407
+
},
408
+
};
409
+
410
+
struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
411
+
.name = "gpio0_pin4_grp",
412
+
.pins = gpio0_pin4_pins,
413
+
.npins = ARRAY_SIZE(gpio0_pin4_pins),
414
+
.modemuxs = gpio0_pin4_modemux,
415
+
.nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
416
+
};
417
+
418
+
/* gpio0_pin5_pins */
419
+
static const unsigned gpio0_pin5_pins[] = { 33 };
420
+
static struct spear_muxreg gpio0_pin5_muxreg[] = {
421
+
{
422
+
.reg = -1,
423
+
.mask = PMX_GPIO_PIN5_MASK,
424
+
.val = PMX_GPIO_PIN5_MASK,
425
+
},
426
+
};
427
+
428
+
static struct spear_modemux gpio0_pin5_modemux[] = {
429
+
{
430
+
.modes = ~0,
431
+
.muxregs = gpio0_pin5_muxreg,
432
+
.nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
433
+
},
434
+
};
435
+
436
+
struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
437
+
.name = "gpio0_pin5_grp",
438
+
.pins = gpio0_pin5_pins,
439
+
.npins = ARRAY_SIZE(gpio0_pin5_pins),
440
+
.modemuxs = gpio0_pin5_modemux,
441
+
.nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
442
+
};
443
+
444
+
static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
445
+
"gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
446
+
};
447
+
struct spear_function spear3xx_gpio0_function = {
448
+
.name = "gpio0",
449
+
.groups = gpio0_grps,
450
+
.ngroups = ARRAY_SIZE(gpio0_grps),
451
+
};
452
+
453
+
/* uart0_ext_pins */
454
+
static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
455
+
static struct spear_muxreg uart0_ext_muxreg[] = {
456
+
{
457
+
.reg = -1,
458
+
.mask = PMX_UART0_MODEM_MASK,
459
+
.val = PMX_UART0_MODEM_MASK,
460
+
},
461
+
};
462
+
463
+
static struct spear_modemux uart0_ext_modemux[] = {
464
+
{
465
+
.modes = ~0,
466
+
.muxregs = uart0_ext_muxreg,
467
+
.nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
468
+
},
469
+
};
470
+
471
+
struct spear_pingroup spear3xx_uart0_ext_pingroup = {
472
+
.name = "uart0_ext_grp",
473
+
.pins = uart0_ext_pins,
474
+
.npins = ARRAY_SIZE(uart0_ext_pins),
475
+
.modemuxs = uart0_ext_modemux,
476
+
.nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
477
+
};
478
+
479
+
static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
480
+
struct spear_function spear3xx_uart0_ext_function = {
481
+
.name = "uart0_ext",
482
+
.groups = uart0_ext_grps,
483
+
.ngroups = ARRAY_SIZE(uart0_ext_grps),
484
+
};
485
+
486
+
/* uart0_pins */
487
+
static const unsigned uart0_pins[] = { 2, 3 };
488
+
static struct spear_muxreg uart0_muxreg[] = {
489
+
{
490
+
.reg = -1,
491
+
.mask = PMX_UART0_MASK,
492
+
.val = PMX_UART0_MASK,
493
+
},
494
+
};
495
+
496
+
static struct spear_modemux uart0_modemux[] = {
497
+
{
498
+
.modes = ~0,
499
+
.muxregs = uart0_muxreg,
500
+
.nmuxregs = ARRAY_SIZE(uart0_muxreg),
501
+
},
502
+
};
503
+
504
+
struct spear_pingroup spear3xx_uart0_pingroup = {
505
+
.name = "uart0_grp",
506
+
.pins = uart0_pins,
507
+
.npins = ARRAY_SIZE(uart0_pins),
508
+
.modemuxs = uart0_modemux,
509
+
.nmodemuxs = ARRAY_SIZE(uart0_modemux),
510
+
};
511
+
512
+
static const char *const uart0_grps[] = { "uart0_grp" };
513
+
struct spear_function spear3xx_uart0_function = {
514
+
.name = "uart0",
515
+
.groups = uart0_grps,
516
+
.ngroups = ARRAY_SIZE(uart0_grps),
517
+
};
518
+
519
+
/* timer_0_1_pins */
520
+
static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
521
+
static struct spear_muxreg timer_0_1_muxreg[] = {
522
+
{
523
+
.reg = -1,
524
+
.mask = PMX_TIMER_0_1_MASK,
525
+
.val = PMX_TIMER_0_1_MASK,
526
+
},
527
+
};
528
+
529
+
static struct spear_modemux timer_0_1_modemux[] = {
530
+
{
531
+
.modes = ~0,
532
+
.muxregs = timer_0_1_muxreg,
533
+
.nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
534
+
},
535
+
};
536
+
537
+
struct spear_pingroup spear3xx_timer_0_1_pingroup = {
538
+
.name = "timer_0_1_grp",
539
+
.pins = timer_0_1_pins,
540
+
.npins = ARRAY_SIZE(timer_0_1_pins),
541
+
.modemuxs = timer_0_1_modemux,
542
+
.nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
543
+
};
544
+
545
+
static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
546
+
struct spear_function spear3xx_timer_0_1_function = {
547
+
.name = "timer_0_1",
548
+
.groups = timer_0_1_grps,
549
+
.ngroups = ARRAY_SIZE(timer_0_1_grps),
550
+
};
551
+
552
+
/* timer_2_3_pins */
553
+
static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
554
+
static struct spear_muxreg timer_2_3_muxreg[] = {
555
+
{
556
+
.reg = -1,
557
+
.mask = PMX_TIMER_2_3_MASK,
558
+
.val = PMX_TIMER_2_3_MASK,
559
+
},
560
+
};
561
+
562
+
static struct spear_modemux timer_2_3_modemux[] = {
563
+
{
564
+
.modes = ~0,
565
+
.muxregs = timer_2_3_muxreg,
566
+
.nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
567
+
},
568
+
};
569
+
570
+
struct spear_pingroup spear3xx_timer_2_3_pingroup = {
571
+
.name = "timer_2_3_grp",
572
+
.pins = timer_2_3_pins,
573
+
.npins = ARRAY_SIZE(timer_2_3_pins),
574
+
.modemuxs = timer_2_3_modemux,
575
+
.nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
576
+
};
577
+
578
+
static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
579
+
struct spear_function spear3xx_timer_2_3_function = {
580
+
.name = "timer_2_3",
581
+
.groups = timer_2_3_grps,
582
+
.ngroups = ARRAY_SIZE(timer_2_3_grps),
583
+
};
584
+
585
+
struct spear_pinctrl_machdata spear3xx_machdata = {
586
+
.pins = spear3xx_pins,
587
+
.npins = ARRAY_SIZE(spear3xx_pins),
588
+
};
+92
drivers/pinctrl/spear/pinctrl-spear3xx.h
+92
drivers/pinctrl/spear/pinctrl-spear3xx.h
···
1
+
/*
2
+
* Header file for the ST Microelectronics SPEAr3xx pinmux
3
+
*
4
+
* Copyright (C) 2012 ST Microelectronics
5
+
* Viresh Kumar <viresh.kumar@st.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#ifndef __PINMUX_SPEAR3XX_H__
13
+
#define __PINMUX_SPEAR3XX_H__
14
+
15
+
#include "pinctrl-spear.h"
16
+
17
+
/* pad mux declarations */
18
+
#define PMX_FIRDA_MASK (1 << 14)
19
+
#define PMX_I2C_MASK (1 << 13)
20
+
#define PMX_SSP_CS_MASK (1 << 12)
21
+
#define PMX_SSP_MASK (1 << 11)
22
+
#define PMX_MII_MASK (1 << 10)
23
+
#define PMX_GPIO_PIN0_MASK (1 << 9)
24
+
#define PMX_GPIO_PIN1_MASK (1 << 8)
25
+
#define PMX_GPIO_PIN2_MASK (1 << 7)
26
+
#define PMX_GPIO_PIN3_MASK (1 << 6)
27
+
#define PMX_GPIO_PIN4_MASK (1 << 5)
28
+
#define PMX_GPIO_PIN5_MASK (1 << 4)
29
+
#define PMX_UART0_MODEM_MASK (1 << 3)
30
+
#define PMX_UART0_MASK (1 << 2)
31
+
#define PMX_TIMER_2_3_MASK (1 << 1)
32
+
#define PMX_TIMER_0_1_MASK (1 << 0)
33
+
34
+
extern struct spear_pingroup spear3xx_firda_pingroup;
35
+
extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup;
36
+
extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup;
37
+
extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup;
38
+
extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup;
39
+
extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup;
40
+
extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup;
41
+
extern struct spear_pingroup spear3xx_i2c_pingroup;
42
+
extern struct spear_pingroup spear3xx_mii_pingroup;
43
+
extern struct spear_pingroup spear3xx_ssp_cs_pingroup;
44
+
extern struct spear_pingroup spear3xx_ssp_pingroup;
45
+
extern struct spear_pingroup spear3xx_timer_0_1_pingroup;
46
+
extern struct spear_pingroup spear3xx_timer_2_3_pingroup;
47
+
extern struct spear_pingroup spear3xx_uart0_ext_pingroup;
48
+
extern struct spear_pingroup spear3xx_uart0_pingroup;
49
+
50
+
#define SPEAR3XX_COMMON_PINGROUPS \
51
+
&spear3xx_firda_pingroup, \
52
+
&spear3xx_gpio0_pin0_pingroup, \
53
+
&spear3xx_gpio0_pin1_pingroup, \
54
+
&spear3xx_gpio0_pin2_pingroup, \
55
+
&spear3xx_gpio0_pin3_pingroup, \
56
+
&spear3xx_gpio0_pin4_pingroup, \
57
+
&spear3xx_gpio0_pin5_pingroup, \
58
+
&spear3xx_i2c_pingroup, \
59
+
&spear3xx_mii_pingroup, \
60
+
&spear3xx_ssp_cs_pingroup, \
61
+
&spear3xx_ssp_pingroup, \
62
+
&spear3xx_timer_0_1_pingroup, \
63
+
&spear3xx_timer_2_3_pingroup, \
64
+
&spear3xx_uart0_ext_pingroup, \
65
+
&spear3xx_uart0_pingroup
66
+
67
+
extern struct spear_function spear3xx_firda_function;
68
+
extern struct spear_function spear3xx_gpio0_function;
69
+
extern struct spear_function spear3xx_i2c_function;
70
+
extern struct spear_function spear3xx_mii_function;
71
+
extern struct spear_function spear3xx_ssp_cs_function;
72
+
extern struct spear_function spear3xx_ssp_function;
73
+
extern struct spear_function spear3xx_timer_0_1_function;
74
+
extern struct spear_function spear3xx_timer_2_3_function;
75
+
extern struct spear_function spear3xx_uart0_ext_function;
76
+
extern struct spear_function spear3xx_uart0_function;
77
+
78
+
#define SPEAR3XX_COMMON_FUNCTIONS \
79
+
&spear3xx_firda_function, \
80
+
&spear3xx_gpio0_function, \
81
+
&spear3xx_i2c_function, \
82
+
&spear3xx_mii_function, \
83
+
&spear3xx_ssp_cs_function, \
84
+
&spear3xx_ssp_function, \
85
+
&spear3xx_timer_0_1_function, \
86
+
&spear3xx_timer_2_3_function, \
87
+
&spear3xx_uart0_ext_function, \
88
+
&spear3xx_uart0_function
89
+
90
+
extern struct spear_pinctrl_machdata spear3xx_machdata;
91
+
92
+
#endif /* __PINMUX_SPEAR3XX_H__ */
+8
drivers/spi/spi-imx.c
+8
drivers/spi/spi-imx.c
···
37
37
#include <linux/of.h>
38
38
#include <linux/of_device.h>
39
39
#include <linux/of_gpio.h>
40
+
#include <linux/pinctrl/consumer.h>
40
41
41
42
#include <mach/spi.h>
42
43
···
760
759
struct spi_master *master;
761
760
struct spi_imx_data *spi_imx;
762
761
struct resource *res;
762
+
struct pinctrl *pinctrl;
763
763
int i, ret, num_cs;
764
764
765
765
if (!np && !mxc_platform_info) {
···
846
844
if (ret) {
847
845
dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
848
846
goto out_iounmap;
847
+
}
848
+
849
+
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
850
+
if (IS_ERR(pinctrl)) {
851
+
ret = PTR_ERR(pinctrl);
852
+
goto out_free_irq;
849
853
}
850
854
851
855
spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+8
drivers/tty/serial/amba-pl011.c
+8
drivers/tty/serial/amba-pl011.c
···
52
52
#include <linux/scatterlist.h>
53
53
#include <linux/delay.h>
54
54
#include <linux/types.h>
55
+
#include <linux/pinctrl/consumer.h>
55
56
56
57
#include <asm/io.h>
57
58
#include <asm/sizes.h>
···
1917
1916
{
1918
1917
struct uart_amba_port *uap;
1919
1918
struct vendor_data *vendor = id->data;
1919
+
struct pinctrl *pinctrl;
1920
1920
void __iomem *base;
1921
1921
int i, ret;
1922
1922
···
1940
1938
if (!base) {
1941
1939
ret = -ENOMEM;
1942
1940
goto free;
1941
+
}
1942
+
1943
+
pinctrl = devm_pinctrl_get_select_default(&dev->dev);
1944
+
if (IS_ERR(pinctrl)) {
1945
+
ret = PTR_ERR(pinctrl);
1946
+
goto unmap;
1943
1947
}
1944
1948
1945
1949
uap->clk = clk_get(&dev->dev, NULL);
+8
drivers/tty/serial/imx.c
+8
drivers/tty/serial/imx.c
···
47
47
#include <linux/slab.h>
48
48
#include <linux/of.h>
49
49
#include <linux/of_device.h>
50
+
#include <linux/pinctrl/consumer.h>
50
51
51
52
#include <asm/io.h>
52
53
#include <asm/irq.h>
···
1466
1465
void __iomem *base;
1467
1466
int ret = 0;
1468
1467
struct resource *res;
1468
+
struct pinctrl *pinctrl;
1469
1469
1470
1470
sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1471
1471
if (!sport)
···
1505
1503
init_timer(&sport->timer);
1506
1504
sport->timer.function = imx_timeout;
1507
1505
sport->timer.data = (unsigned long)sport;
1506
+
1507
+
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1508
+
if (IS_ERR(pinctrl)) {
1509
+
ret = PTR_ERR(pinctrl);
1510
+
goto unmap;
1511
+
}
1508
1512
1509
1513
sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1510
1514
if (IS_ERR(sport->clk_ipg)) {
+8
drivers/tty/serial/mxs-auart.c
+8
drivers/tty/serial/mxs-auart.c
···
32
32
#include <linux/clk.h>
33
33
#include <linux/delay.h>
34
34
#include <linux/io.h>
35
+
#include <linux/pinctrl/consumer.h>
35
36
36
37
#include <asm/cacheflush.h>
37
38
···
679
678
u32 version;
680
679
int ret = 0;
681
680
struct resource *r;
681
+
struct pinctrl *pinctrl;
682
682
683
683
s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
684
684
if (!s) {
685
685
ret = -ENOMEM;
686
686
goto out;
687
+
}
688
+
689
+
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
690
+
if (IS_ERR(pinctrl)) {
691
+
ret = PTR_ERR(pinctrl);
692
+
goto out_free;
687
693
}
688
694
689
695
s->clk = clk_get(&pdev->dev, NULL);
+9
drivers/video/mxsfb.c
+9
drivers/video/mxsfb.c
···
45
45
#include <linux/clk.h>
46
46
#include <linux/dma-mapping.h>
47
47
#include <linux/io.h>
48
+
#include <linux/pinctrl/consumer.h>
48
49
#include <mach/mxsfb.h>
49
50
50
51
#define REG_SET 4
···
757
756
struct mxsfb_info *host;
758
757
struct fb_info *fb_info;
759
758
struct fb_modelist *modelist;
759
+
struct pinctrl *pinctrl;
760
760
int i, ret;
761
761
762
762
if (!pdata) {
···
794
792
platform_set_drvdata(pdev, host);
795
793
796
794
host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
795
+
796
+
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
797
+
if (IS_ERR(pinctrl)) {
798
+
ret = PTR_ERR(pinctrl);
799
+
goto error_getpin;
800
+
}
797
801
798
802
host->clk = clk_get(&host->pdev->dev, NULL);
799
803
if (IS_ERR(host->clk)) {
···
856
848
error_pseudo_pallette:
857
849
clk_put(host->clk);
858
850
error_getclock:
851
+
error_getpin:
859
852
iounmap(host->base);
860
853
error_ioremap:
861
854
framebuffer_release(fb_info);
+51
include/linux/of.h
+51
include/linux/of.h
···
193
193
for (child = of_get_next_child(parent, NULL); child != NULL; \
194
194
child = of_get_next_child(parent, child))
195
195
196
+
static inline int of_get_child_count(const struct device_node *np)
197
+
{
198
+
struct device_node *child;
199
+
int num = 0;
200
+
201
+
for_each_child_of_node(np, child)
202
+
num++;
203
+
204
+
return num;
205
+
}
206
+
196
207
extern struct device_node *of_find_node_with_property(
197
208
struct device_node *from, const char *prop_name);
198
209
#define for_each_node_with_property(dn, prop_name) \
···
270
259
#endif
271
260
272
261
#define of_match_ptr(_ptr) (_ptr)
262
+
263
+
/*
264
+
* struct property *prop;
265
+
* const __be32 *p;
266
+
* u32 u;
267
+
*
268
+
* of_property_for_each_u32(np, "propname", prop, p, u)
269
+
* printk("U32 value: %x\n", u);
270
+
*/
271
+
const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
272
+
u32 *pu);
273
+
#define of_property_for_each_u32(np, propname, prop, p, u) \
274
+
for (prop = of_find_property(np, propname, NULL), \
275
+
p = of_prop_next_u32(prop, NULL, &u); \
276
+
p; \
277
+
p = of_prop_next_u32(prop, p, &u))
278
+
279
+
/*
280
+
* struct property *prop;
281
+
* const char *s;
282
+
*
283
+
* of_property_for_each_string(np, "propname", prop, s)
284
+
* printk("String value: %s\n", s);
285
+
*/
286
+
const char *of_prop_next_string(struct property *prop, const char *cur);
287
+
#define of_property_for_each_string(np, propname, prop, s) \
288
+
for (prop = of_find_property(np, propname, NULL), \
289
+
s = of_prop_next_string(prop, NULL); \
290
+
s; \
291
+
s = of_prop_next_string(prop, s))
292
+
273
293
#else /* CONFIG_OF */
274
294
275
295
static inline bool of_have_populated_dt(void)
···
310
268
311
269
#define for_each_child_of_node(parent, child) \
312
270
while (0)
271
+
272
+
static inline int of_get_child_count(const struct device_node *np)
273
+
{
274
+
return 0;
275
+
}
313
276
314
277
static inline int of_device_is_compatible(const struct device_node *device,
315
278
const char *name)
···
396
349
397
350
#define of_match_ptr(_ptr) NULL
398
351
#define of_match_node(_matches, _node) NULL
352
+
#define of_property_for_each_u32(np, propname, prop, p, u) \
353
+
while (0)
354
+
#define of_property_for_each_string(np, propname, prop, s) \
355
+
while (0)
399
356
#endif /* CONFIG_OF */
400
357
401
358
/**
+44
include/linux/pinctrl/consumer.h
+44
include/linux/pinctrl/consumer.h
···
36
36
const char *name);
37
37
extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s);
38
38
39
+
extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev);
40
+
extern void devm_pinctrl_put(struct pinctrl *p);
41
+
39
42
#else /* !CONFIG_PINCTRL */
40
43
41
44
static inline int pinctrl_request_gpio(unsigned gpio)
···
82
79
return 0;
83
80
}
84
81
82
+
static inline struct pinctrl * __must_check devm_pinctrl_get(struct device *dev)
83
+
{
84
+
return NULL;
85
+
}
86
+
87
+
static inline void devm_pinctrl_put(struct pinctrl *p)
88
+
{
89
+
}
90
+
85
91
#endif /* CONFIG_PINCTRL */
86
92
87
93
static inline struct pinctrl * __must_check pinctrl_get_select(
···
123
111
struct device *dev)
124
112
{
125
113
return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
114
+
}
115
+
116
+
static inline struct pinctrl * __must_check devm_pinctrl_get_select(
117
+
struct device *dev, const char *name)
118
+
{
119
+
struct pinctrl *p;
120
+
struct pinctrl_state *s;
121
+
int ret;
122
+
123
+
p = devm_pinctrl_get(dev);
124
+
if (IS_ERR(p))
125
+
return p;
126
+
127
+
s = pinctrl_lookup_state(p, name);
128
+
if (IS_ERR(s)) {
129
+
devm_pinctrl_put(p);
130
+
return ERR_PTR(PTR_ERR(s));
131
+
}
132
+
133
+
ret = pinctrl_select_state(p, s);
134
+
if (ret < 0) {
135
+
devm_pinctrl_put(p);
136
+
return ERR_PTR(ret);
137
+
}
138
+
139
+
return p;
140
+
}
141
+
142
+
static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(
143
+
struct device *dev)
144
+
{
145
+
return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
126
146
}
127
147
128
148
#ifdef CONFIG_PINCONF
+5
-2
include/linux/pinctrl/machine.h
+5
-2
include/linux/pinctrl/machine.h
···
154
154
155
155
extern int pinctrl_register_mappings(struct pinctrl_map const *map,
156
156
unsigned num_maps);
157
-
157
+
extern void pinctrl_provide_dummies(void);
158
158
#else
159
159
160
160
static inline int pinctrl_register_mappings(struct pinctrl_map const *map,
···
163
163
return 0;
164
164
}
165
165
166
-
#endif /* !CONFIG_PINMUX */
166
+
static inline void pinctrl_provide_dummies(void)
167
+
{
168
+
}
169
+
#endif /* !CONFIG_PINCTRL */
167
170
#endif
+5
-1
include/linux/pinctrl/pinconf.h
+5
-1
include/linux/pinctrl/pinconf.h
···
25
25
* @pin_config_get: get the config of a certain pin, if the requested config
26
26
* is not available on this controller this should return -ENOTSUPP
27
27
* and if it is available but disabled it should return -EINVAL
28
-
* @pin_config_get: get the config of a certain pin
29
28
* @pin_config_set: configure an individual pin
30
29
* @pin_config_group_get: get configurations for an entire pin group
31
30
* @pin_config_group_set: configure all pins in a group
···
32
33
* per-device info for a certain pin in debugfs
33
34
* @pin_config_group_dbg_show: optional debugfs display hook that will provide
34
35
* per-device info for a certain group in debugfs
36
+
* @pin_config_config_dbg_show: optional debugfs display hook that will decode
37
+
* and display a driver's pin configuration parameter
35
38
*/
36
39
struct pinconf_ops {
37
40
#ifdef CONFIG_GENERIC_PINCONF
···
57
56
void (*pin_config_group_dbg_show) (struct pinctrl_dev *pctldev,
58
57
struct seq_file *s,
59
58
unsigned selector);
59
+
void (*pin_config_config_dbg_show) (struct pinctrl_dev *pctldev,
60
+
struct seq_file *s,
61
+
unsigned long config);
60
62
};
61
63
62
64
#endif
+18
-4
include/linux/pinctrl/pinctrl.h
+18
-4
include/linux/pinctrl/pinctrl.h
···
21
21
22
22
struct device;
23
23
struct pinctrl_dev;
24
+
struct pinctrl_map;
24
25
struct pinmux_ops;
25
26
struct pinconf_ops;
26
27
struct gpio_chip;
28
+
struct device_node;
27
29
28
30
/**
29
31
* struct pinctrl_pin_desc - boards/machines provide information on their
···
66
64
/**
67
65
* struct pinctrl_ops - global pin control operations, to be implemented by
68
66
* pin controller drivers.
69
-
* @list_groups: list the number of selectable named groups available
70
-
* in this pinmux driver, the core will begin on 0 and call this
71
-
* repeatedly as long as it returns >= 0 to enumerate the groups
67
+
* @get_groups_count: Returns the count of total number of groups registered.
72
68
* @get_group_name: return the group name of the pin group
73
69
* @get_group_pins: return an array of pins corresponding to a certain
74
70
* group selector @pins, and the size of the array in @num_pins
75
71
* @pin_dbg_show: optional debugfs display hook that will provide per-device
76
72
* info for a certain pin in debugfs
73
+
* @dt_node_to_map: parse a device tree "pin configuration node", and create
74
+
* mapping table entries for it. These are returned through the @map and
75
+
* @num_maps output parameters. This function is optional, and may be
76
+
* omitted for pinctrl drivers that do not support device tree.
77
+
* @dt_free_map: free mapping table entries created via @dt_node_to_map. The
78
+
* top-level @map pointer must be freed, along with any dynamically
79
+
* allocated members of the mapping table entries themselves. This
80
+
* function is optional, and may be omitted for pinctrl drivers that do
81
+
* not support device tree.
77
82
*/
78
83
struct pinctrl_ops {
79
-
int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector);
84
+
int (*get_groups_count) (struct pinctrl_dev *pctldev);
80
85
const char *(*get_group_name) (struct pinctrl_dev *pctldev,
81
86
unsigned selector);
82
87
int (*get_group_pins) (struct pinctrl_dev *pctldev,
···
92
83
unsigned *num_pins);
93
84
void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s,
94
85
unsigned offset);
86
+
int (*dt_node_to_map) (struct pinctrl_dev *pctldev,
87
+
struct device_node *np_config,
88
+
struct pinctrl_map **map, unsigned *num_maps);
89
+
void (*dt_free_map) (struct pinctrl_dev *pctldev,
90
+
struct pinctrl_map *map, unsigned num_maps);
95
91
};
96
92
97
93
/**
+4
-5
include/linux/pinctrl/pinmux.h
+4
-5
include/linux/pinctrl/pinmux.h
···
23
23
/**
24
24
* struct pinmux_ops - pinmux operations, to be implemented by pin controller
25
25
* drivers that support pinmuxing
26
-
* @request: called by the core to see if a certain pin can be made available
26
+
* @request: called by the core to see if a certain pin can be made
27
27
* available for muxing. This is called by the core to acquire the pins
28
28
* before selecting any actual mux setting across a function. The driver
29
29
* is allowed to answer "no" by returning a negative error code
30
30
* @free: the reverse function of the request() callback, frees a pin after
31
31
* being requested
32
-
* @list_functions: list the number of selectable named functions available
33
-
* in this pinmux driver, the core will begin on 0 and call this
34
-
* repeatedly as long as it returns >= 0 to enumerate mux settings
32
+
* @get_functions_count: returns number of selectable named functions available
33
+
* in this pinmux driver
35
34
* @get_function_name: return the function name of the muxing selector,
36
35
* called by the core to figure out which mux setting it shall map a
37
36
* certain device to
···
61
62
struct pinmux_ops {
62
63
int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
63
64
int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
64
-
int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector);
65
+
int (*get_functions_count) (struct pinctrl_dev *pctldev);
65
66
const char *(*get_function_name) (struct pinctrl_dev *pctldev,
66
67
unsigned selector);
67
68
int (*get_function_groups) (struct pinctrl_dev *pctldev,
+8
sound/soc/mxs/mxs-saif.c
+8
sound/soc/mxs/mxs-saif.c
···
25
25
#include <linux/delay.h>
26
26
#include <linux/time.h>
27
27
#include <linux/fsl/mxs-dma.h>
28
+
#include <linux/pinctrl/consumer.h>
28
29
#include <sound/core.h>
29
30
#include <sound/pcm.h>
30
31
#include <sound/pcm_params.h>
···
626
625
struct resource *iores, *dmares;
627
626
struct mxs_saif *saif;
628
627
struct mxs_saif_platform_data *pdata;
628
+
struct pinctrl *pinctrl;
629
629
int ret = 0;
630
630
631
631
if (pdev->id >= ARRAY_SIZE(mxs_saif))
···
650
648
}
651
649
} else {
652
650
saif->master_id = saif->id;
651
+
}
652
+
653
+
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
654
+
if (IS_ERR(pinctrl)) {
655
+
ret = PTR_ERR(pinctrl);
656
+
return ret;
653
657
}
654
658
655
659
saif->clk = clk_get(&pdev->dev, NULL);