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dt-bindings: spi: Fix spi-bcm-qspi compatible ordering

The binding is currently incorrectly defining the compatible strings
from least specifice to most specific instead of the converse. Re-order
them from most specific (left) to least specific (right) and fix the
examples as well.

Fixes: 5fc78f4c842a ("spi: Broadcom BRCMSTB, NSP, NS2 SoC bindings")
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

+8 -8
+8 -8
Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
··· 23 23 24 24 - compatible: 25 25 Must be one of : 26 - "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs 27 - "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 26 + "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs 27 + "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI 28 28 BRCMSTB SoCs 29 29 "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 30 30 BRCMSTB SoCs ··· 36 36 BRCMSTB SoCs 37 37 "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI 38 38 BRCMSTB SoCs 39 - "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP 40 - "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs 39 + "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on Cygnus, NSP 40 + "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi" : NS2 SoCs 41 41 42 42 - reg: 43 43 Define the bases and ranges of the associated I/O address spaces. ··· 86 86 spi@f03e3400 { 87 87 #address-cells = <0x1>; 88 88 #size-cells = <0x0>; 89 - compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi"; 89 + compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi"; 90 90 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; 91 91 reg-names = "cs_reg", "mspi", "bspi"; 92 92 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; ··· 149 149 #address-cells = <1>; 150 150 #size-cells = <0>; 151 151 clocks = <&upg_fixed>; 152 - compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi"; 152 + compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi"; 153 153 reg = <0xf0416000 0x180>; 154 154 reg-names = "mspi"; 155 155 interrupts = <0x14>; ··· 160 160 iProc SoC Example: 161 161 162 162 qspi: spi@18027200 { 163 - compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; 163 + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; 164 164 reg = <0x18027200 0x184>, 165 165 <0x18027000 0x124>, 166 166 <0x1811c408 0x004>, ··· 191 191 NS2 SoC Example: 192 192 193 193 qspi: spi@66470200 { 194 - compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; 194 + compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; 195 195 reg = <0x66470200 0x184>, 196 196 <0x66470000 0x124>, 197 197 <0x67017408 0x004>,