tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

MIPS: TXX9: Remove TX4939 SoC support

After removal of RBTX4939 board support remove code for the TX4939 SoC.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>

Thomas Bogendoerfer fc5bb239 5a8df928

+1 -1596
-524
arch/mips/include/asm/txx9/tx4939.h
··· 1 - /* 2 - * Definitions for TX4939 3 - * 4 - * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation 5 - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the 6 - * terms of the GNU General Public License version 2. This program is 7 - * licensed "as is" without any warranty of any kind, whether express 8 - * or implied. 9 - */ 10 - #ifndef __ASM_TXX9_TX4939_H 11 - #define __ASM_TXX9_TX4939_H 12 - 13 - /* some controllers are compatible with 4927/4938 */ 14 - #include <asm/txx9/tx4938.h> 15 - 16 - #ifdef CONFIG_64BIT 17 - #define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */ 18 - #else 19 - #define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */ 20 - #endif 21 - #define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */ 22 - 23 - #define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000) 24 - #define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000) 25 - #define TX4939_SRAMC_REG (TX4939_REG_BASE + 0x6000) 26 - #define TX4939_CRYPTO_REG (TX4939_REG_BASE + 0x6800) 27 - #define TX4939_PCIC1_REG (TX4939_REG_BASE + 0x7000) 28 - #define TX4939_DDRC_REG (TX4939_REG_BASE + 0x8000) 29 - #define TX4939_EBUSC_REG (TX4939_REG_BASE + 0x9000) 30 - #define TX4939_VPC_REG (TX4939_REG_BASE + 0xa000) 31 - #define TX4939_DMA_REG(ch) (TX4939_REG_BASE + 0xb000 + (ch) * 0x800) 32 - #define TX4939_PCIC_REG (TX4939_REG_BASE + 0xd000) 33 - #define TX4939_CCFG_REG (TX4939_REG_BASE + 0xe000) 34 - #define TX4939_IRC_REG (TX4939_REG_BASE + 0xe800) 35 - #define TX4939_NR_TMR 6 /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */ 36 - #define TX4939_TMR_REG(ch) \ 37 - (TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100) 38 - #define TX4939_NR_SIO 4 /* 0xf300, 0xf400, 0xf380, 0xf480 */ 39 - #define TX4939_SIO_REG(ch) \ 40 - (TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6)) 41 - #define TX4939_ACLC_REG (TX4939_REG_BASE + 0xf700) 42 - #define TX4939_SPI_REG (TX4939_REG_BASE + 0xf800) 43 - #define TX4939_I2C_REG (TX4939_REG_BASE + 0xf900) 44 - #define TX4939_I2S_REG (TX4939_REG_BASE + 0xfa00) 45 - #define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00) 46 - #define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00) 47 - 48 - #define TX4939_RNG_REG (TX4939_CRYPTO_REG + 0xb0) 49 - 50 - struct tx4939_le_reg { 51 - __u32 r; 52 - __u32 unused; 53 - }; 54 - 55 - struct tx4939_ddrc_reg { 56 - struct tx4939_le_reg ctl[47]; 57 - __u64 unused0[17]; 58 - __u64 winen; 59 - __u64 win[4]; 60 - }; 61 - 62 - struct tx4939_ccfg_reg { 63 - __u64 ccfg; 64 - __u64 crir; 65 - __u64 pcfg; 66 - __u64 toea; 67 - __u64 clkctr; 68 - __u64 unused0; 69 - __u64 garbc; 70 - __u64 unused1[2]; 71 - __u64 ramp; 72 - __u64 unused2[2]; 73 - __u64 dskwctrl; 74 - __u64 mclkosc; 75 - __u64 mclkctl; 76 - __u64 unused3[17]; 77 - struct { 78 - __u64 mr; 79 - __u64 dr; 80 - } gpio[2]; 81 - }; 82 - 83 - struct tx4939_irc_reg { 84 - struct tx4939_le_reg den; 85 - struct tx4939_le_reg scipb; 86 - struct tx4939_le_reg dm[2]; 87 - struct tx4939_le_reg lvl[16]; 88 - struct tx4939_le_reg msk; 89 - struct tx4939_le_reg edc; 90 - struct tx4939_le_reg pnd0; 91 - struct tx4939_le_reg cs; 92 - struct tx4939_le_reg pnd1; 93 - struct tx4939_le_reg dm2[2]; 94 - struct tx4939_le_reg dbr[2]; 95 - struct tx4939_le_reg dben; 96 - struct tx4939_le_reg unused0[2]; 97 - struct tx4939_le_reg flag[2]; 98 - struct tx4939_le_reg pol; 99 - struct tx4939_le_reg cnt; 100 - struct tx4939_le_reg maskint; 101 - struct tx4939_le_reg maskext; 102 - }; 103 - 104 - struct tx4939_crypto_reg { 105 - struct tx4939_le_reg csr; 106 - struct tx4939_le_reg idesptr; 107 - struct tx4939_le_reg cdesptr; 108 - struct tx4939_le_reg buserr; 109 - struct tx4939_le_reg cip_tout; 110 - struct tx4939_le_reg cir; 111 - union { 112 - struct { 113 - struct tx4939_le_reg data[8]; 114 - struct tx4939_le_reg ctrl; 115 - } gen; 116 - struct { 117 - struct { 118 - struct tx4939_le_reg l; 119 - struct tx4939_le_reg u; 120 - } key[3], ini; 121 - struct tx4939_le_reg ctrl; 122 - } des; 123 - struct { 124 - struct tx4939_le_reg key[4]; 125 - struct tx4939_le_reg ini[4]; 126 - struct tx4939_le_reg ctrl; 127 - } aes; 128 - struct { 129 - struct { 130 - struct tx4939_le_reg l; 131 - struct tx4939_le_reg u; 132 - } cnt; 133 - struct tx4939_le_reg ini[5]; 134 - struct tx4939_le_reg unused; 135 - struct tx4939_le_reg ctrl; 136 - } hash; 137 - } cdr; 138 - struct tx4939_le_reg unused0[7]; 139 - struct tx4939_le_reg rcsr; 140 - struct tx4939_le_reg rpr; 141 - __u64 rdr; 142 - __u64 ror[3]; 143 - struct tx4939_le_reg unused1[2]; 144 - struct tx4939_le_reg xorslr; 145 - struct tx4939_le_reg xorsur; 146 - }; 147 - 148 - struct tx4939_crypto_desc { 149 - __u32 src; 150 - __u32 dst; 151 - __u32 next; 152 - __u32 ctrl; 153 - __u32 index; 154 - __u32 xor; 155 - }; 156 - 157 - struct tx4939_vpc_reg { 158 - struct tx4939_le_reg csr; 159 - struct { 160 - struct tx4939_le_reg ctrlA; 161 - struct tx4939_le_reg ctrlB; 162 - struct tx4939_le_reg idesptr; 163 - struct tx4939_le_reg cdesptr; 164 - } port[3]; 165 - struct tx4939_le_reg buserr; 166 - }; 167 - 168 - struct tx4939_vpc_desc { 169 - __u32 src; 170 - __u32 next; 171 - __u32 ctrl1; 172 - __u32 ctrl2; 173 - }; 174 - 175 - /* 176 - * IRC 177 - */ 178 - #define TX4939_IR_NONE 0 179 - #define TX4939_IR_DDR 1 180 - #define TX4939_IR_WTOERR 2 181 - #define TX4939_NUM_IR_INT 3 182 - #define TX4939_IR_INT(n) (3 + (n)) 183 - #define TX4939_NUM_IR_ETH 2 184 - #define TX4939_IR_ETH(n) ((n) ? 43 : 6) 185 - #define TX4939_IR_VIDEO 7 186 - #define TX4939_IR_CIR 8 187 - #define TX4939_NUM_IR_SIO 4 188 - #define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */ 189 - #define TX4939_NUM_IR_DMA 4 190 - #define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */ 191 - #define TX4939_IR_IRC 14 192 - #define TX4939_IR_PDMAC 15 193 - #define TX4939_NUM_IR_TMR 6 194 - #define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */ 195 - #define TX4939_NUM_IR_ATA 2 196 - #define TX4939_IR_ATA(n) (19 + (n)) 197 - #define TX4939_IR_ACLC 21 198 - #define TX4939_IR_CIPHER 26 199 - #define TX4939_IR_INTA 27 200 - #define TX4939_IR_INTB 28 201 - #define TX4939_IR_INTC 29 202 - #define TX4939_IR_INTD 30 203 - #define TX4939_IR_I2C 33 204 - #define TX4939_IR_SPI 34 205 - #define TX4939_IR_PCIC 35 206 - #define TX4939_IR_PCIC1 36 207 - #define TX4939_IR_PCIERR 37 208 - #define TX4939_IR_PCIPME 38 209 - #define TX4939_IR_NDFMC 39 210 - #define TX4939_IR_ACLCPME 40 211 - #define TX4939_IR_RTC 41 212 - #define TX4939_IR_RND 42 213 - #define TX4939_IR_I2S 47 214 - #define TX4939_NUM_IR 64 215 - 216 - #define TX4939_IRC_INT 2 /* IP[2] in Status register */ 217 - 218 - /* 219 - * CCFG 220 - */ 221 - /* CCFG : Chip Configuration */ 222 - #define TX4939_CCFG_PCIBOOT 0x0000040000000000ULL 223 - #define TX4939_CCFG_WDRST 0x0000020000000000ULL 224 - #define TX4939_CCFG_WDREXEN 0x0000010000000000ULL 225 - #define TX4939_CCFG_BCFG_MASK 0x000000ff00000000ULL 226 - #define TX4939_CCFG_GTOT_MASK 0x06000000 227 - #define TX4939_CCFG_GTOT_4096 0x06000000 228 - #define TX4939_CCFG_GTOT_2048 0x04000000 229 - #define TX4939_CCFG_GTOT_1024 0x02000000 230 - #define TX4939_CCFG_GTOT_512 0x00000000 231 - #define TX4939_CCFG_TINTDIS 0x01000000 232 - #define TX4939_CCFG_PCI66 0x00800000 233 - #define TX4939_CCFG_PCIMODE 0x00400000 234 - #define TX4939_CCFG_SSCG 0x00100000 235 - #define TX4939_CCFG_MULCLK_MASK 0x000e0000 236 - #define TX4939_CCFG_MULCLK_8 (0x7 << 17) 237 - #define TX4939_CCFG_MULCLK_9 (0x0 << 17) 238 - #define TX4939_CCFG_MULCLK_10 (0x1 << 17) 239 - #define TX4939_CCFG_MULCLK_11 (0x2 << 17) 240 - #define TX4939_CCFG_MULCLK_12 (0x3 << 17) 241 - #define TX4939_CCFG_MULCLK_13 (0x4 << 17) 242 - #define TX4939_CCFG_MULCLK_14 (0x5 << 17) 243 - #define TX4939_CCFG_MULCLK_15 (0x6 << 17) 244 - #define TX4939_CCFG_BEOW 0x00010000 245 - #define TX4939_CCFG_WR 0x00008000 246 - #define TX4939_CCFG_TOE 0x00004000 247 - #define TX4939_CCFG_PCIARB 0x00002000 248 - #define TX4939_CCFG_YDIVMODE_MASK 0x00001c00 249 - #define TX4939_CCFG_YDIVMODE_2 (0x0 << 10) 250 - #define TX4939_CCFG_YDIVMODE_3 (0x1 << 10) 251 - #define TX4939_CCFG_YDIVMODE_5 (0x6 << 10) 252 - #define TX4939_CCFG_YDIVMODE_6 (0x7 << 10) 253 - #define TX4939_CCFG_PTSEL 0x00000200 254 - #define TX4939_CCFG_BESEL 0x00000100 255 - #define TX4939_CCFG_SYSSP_MASK 0x000000c0 256 - #define TX4939_CCFG_ACKSEL 0x00000020 257 - #define TX4939_CCFG_ROMW 0x00000010 258 - #define TX4939_CCFG_ENDIAN 0x00000004 259 - #define TX4939_CCFG_ARMODE 0x00000002 260 - #define TX4939_CCFG_ACEHOLD 0x00000001 261 - 262 - /* PCFG : Pin Configuration */ 263 - #define TX4939_PCFG_SIO2MODE_MASK 0xc000000000000000ULL 264 - #define TX4939_PCFG_SIO2MODE_GPIO 0x8000000000000000ULL 265 - #define TX4939_PCFG_SIO2MODE_SIO2 0x4000000000000000ULL 266 - #define TX4939_PCFG_SIO2MODE_SIO0 0x0000000000000000ULL 267 - #define TX4939_PCFG_SPIMODE 0x2000000000000000ULL 268 - #define TX4939_PCFG_I2CMODE 0x1000000000000000ULL 269 - #define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL 270 - #define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL 271 - #define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL 272 - #define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL 273 - #define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL 274 - #define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL 275 - #define TX4939_PCFG_DMASEL3 0x0004000000000000ULL 276 - #define TX4939_PCFG_DMASEL3_SIO0 0x0004000000000000ULL 277 - #define TX4939_PCFG_DMASEL3_NDFC 0x0000000000000000ULL 278 - #define TX4939_PCFG_VSSMODE 0x0000200000000000ULL 279 - #define TX4939_PCFG_VPSMODE 0x0000100000000000ULL 280 - #define TX4939_PCFG_ET1MODE 0x0000080000000000ULL 281 - #define TX4939_PCFG_ET0MODE 0x0000040000000000ULL 282 - #define TX4939_PCFG_ATA1MODE 0x0000020000000000ULL 283 - #define TX4939_PCFG_ATA0MODE 0x0000010000000000ULL 284 - #define TX4939_PCFG_BP_PLL 0x0000000100000000ULL 285 - 286 - #define TX4939_PCFG_SYSCLKEN 0x08000000 287 - #define TX4939_PCFG_PCICLKEN_ALL 0x000f0000 288 - #define TX4939_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) 289 - #define TX4939_PCFG_SPEED1 0x00002000 290 - #define TX4939_PCFG_SPEED0 0x00001000 291 - #define TX4939_PCFG_ITMODE 0x00000300 292 - #define TX4939_PCFG_DMASEL_ALL (0x00000007 | TX4939_PCFG_DMASEL3) 293 - #define TX4939_PCFG_DMASEL2 0x00000004 294 - #define TX4939_PCFG_DMASEL2_DRQ2 0x00000000 295 - #define TX4939_PCFG_DMASEL2_SIO0 0x00000004 296 - #define TX4939_PCFG_DMASEL1 0x00000002 297 - #define TX4939_PCFG_DMASEL1_DRQ1 0x00000000 298 - #define TX4939_PCFG_DMASEL0 0x00000001 299 - #define TX4939_PCFG_DMASEL0_DRQ0 0x00000000 300 - 301 - /* CLKCTR : Clock Control */ 302 - #define TX4939_CLKCTR_IOSCKD 0x8000000000000000ULL 303 - #define TX4939_CLKCTR_SYSCKD 0x4000000000000000ULL 304 - #define TX4939_CLKCTR_TM5CKD 0x2000000000000000ULL 305 - #define TX4939_CLKCTR_TM4CKD 0x1000000000000000ULL 306 - #define TX4939_CLKCTR_TM3CKD 0x0800000000000000ULL 307 - #define TX4939_CLKCTR_CIRCKD 0x0400000000000000ULL 308 - #define TX4939_CLKCTR_SIO3CKD 0x0200000000000000ULL 309 - #define TX4939_CLKCTR_SIO2CKD 0x0100000000000000ULL 310 - #define TX4939_CLKCTR_SIO1CKD 0x0080000000000000ULL 311 - #define TX4939_CLKCTR_VPCCKD 0x0040000000000000ULL 312 - #define TX4939_CLKCTR_EPCICKD 0x0020000000000000ULL 313 - #define TX4939_CLKCTR_ETH1CKD 0x0008000000000000ULL 314 - #define TX4939_CLKCTR_ATA1CKD 0x0004000000000000ULL 315 - #define TX4939_CLKCTR_BROMCKD 0x0002000000000000ULL 316 - #define TX4939_CLKCTR_NDCCKD 0x0001000000000000ULL 317 - #define TX4939_CLKCTR_I2CCKD 0x0000800000000000ULL 318 - #define TX4939_CLKCTR_ETH0CKD 0x0000400000000000ULL 319 - #define TX4939_CLKCTR_SPICKD 0x0000200000000000ULL 320 - #define TX4939_CLKCTR_SRAMCKD 0x0000100000000000ULL 321 - #define TX4939_CLKCTR_PCI1CKD 0x0000080000000000ULL 322 - #define TX4939_CLKCTR_DMA1CKD 0x0000040000000000ULL 323 - #define TX4939_CLKCTR_ACLCKD 0x0000020000000000ULL 324 - #define TX4939_CLKCTR_ATA0CKD 0x0000010000000000ULL 325 - #define TX4939_CLKCTR_DMA0CKD 0x0000008000000000ULL 326 - #define TX4939_CLKCTR_PCICCKD 0x0000004000000000ULL 327 - #define TX4939_CLKCTR_I2SCKD 0x0000002000000000ULL 328 - #define TX4939_CLKCTR_TM0CKD 0x0000001000000000ULL 329 - #define TX4939_CLKCTR_TM1CKD 0x0000000800000000ULL 330 - #define TX4939_CLKCTR_TM2CKD 0x0000000400000000ULL 331 - #define TX4939_CLKCTR_SIO0CKD 0x0000000200000000ULL 332 - #define TX4939_CLKCTR_CYPCKD 0x0000000100000000ULL 333 - #define TX4939_CLKCTR_IOSRST 0x80000000 334 - #define TX4939_CLKCTR_SYSRST 0x40000000 335 - #define TX4939_CLKCTR_TM5RST 0x20000000 336 - #define TX4939_CLKCTR_TM4RST 0x10000000 337 - #define TX4939_CLKCTR_TM3RST 0x08000000 338 - #define TX4939_CLKCTR_CIRRST 0x04000000 339 - #define TX4939_CLKCTR_SIO3RST 0x02000000 340 - #define TX4939_CLKCTR_SIO2RST 0x01000000 341 - #define TX4939_CLKCTR_SIO1RST 0x00800000 342 - #define TX4939_CLKCTR_VPCRST 0x00400000 343 - #define TX4939_CLKCTR_EPCIRST 0x00200000 344 - #define TX4939_CLKCTR_ETH1RST 0x00080000 345 - #define TX4939_CLKCTR_ATA1RST 0x00040000 346 - #define TX4939_CLKCTR_BROMRST 0x00020000 347 - #define TX4939_CLKCTR_NDCRST 0x00010000 348 - #define TX4939_CLKCTR_I2CRST 0x00008000 349 - #define TX4939_CLKCTR_ETH0RST 0x00004000 350 - #define TX4939_CLKCTR_SPIRST 0x00002000 351 - #define TX4939_CLKCTR_SRAMRST 0x00001000 352 - #define TX4939_CLKCTR_PCI1RST 0x00000800 353 - #define TX4939_CLKCTR_DMA1RST 0x00000400 354 - #define TX4939_CLKCTR_ACLRST 0x00000200 355 - #define TX4939_CLKCTR_ATA0RST 0x00000100 356 - #define TX4939_CLKCTR_DMA0RST 0x00000080 357 - #define TX4939_CLKCTR_PCICRST 0x00000040 358 - #define TX4939_CLKCTR_I2SRST 0x00000020 359 - #define TX4939_CLKCTR_TM0RST 0x00000010 360 - #define TX4939_CLKCTR_TM1RST 0x00000008 361 - #define TX4939_CLKCTR_TM2RST 0x00000004 362 - #define TX4939_CLKCTR_SIO0RST 0x00000002 363 - #define TX4939_CLKCTR_CYPRST 0x00000001 364 - 365 - /* 366 - * CRYPTO 367 - */ 368 - #define TX4939_CRYPTO_CSR_SAESO 0x08000000 369 - #define TX4939_CRYPTO_CSR_SAESI 0x04000000 370 - #define TX4939_CRYPTO_CSR_SDESO 0x02000000 371 - #define TX4939_CRYPTO_CSR_SDESI 0x01000000 372 - #define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000 373 - #define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20) 374 - #define TX4939_CRYPTO_CSR_TOINT 0x00080000 375 - #define TX4939_CRYPTO_CSR_DCINT 0x00040000 376 - #define TX4939_CRYPTO_CSR_GBINT 0x00010000 377 - #define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000 378 - #define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13) 379 - #define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800 380 - #define TX4939_CRYPTO_CSR_CSWAP_NONE 0x00000000 381 - #define TX4939_CRYPTO_CSR_CSWAP_IN 0x00000800 382 - #define TX4939_CRYPTO_CSR_CSWAP_OUT 0x00001000 383 - #define TX4939_CRYPTO_CSR_CSWAP_BOTH 0x00001800 384 - #define TX4939_CRYPTO_CSR_CDIV_MASK 0x00000600 385 - #define TX4939_CRYPTO_CSR_CDIV_DIV2 0x00000000 386 - #define TX4939_CRYPTO_CSR_CDIV_DIV1 0x00000200 387 - #define TX4939_CRYPTO_CSR_CDIV_DIV2ALT 0x00000400 388 - #define TX4939_CRYPTO_CSR_CDIV_DIV1ALT 0x00000600 389 - #define TX4939_CRYPTO_CSR_PDINT_MASK 0x000000c0 390 - #define TX4939_CRYPTO_CSR_PDINT_ALL 0x00000000 391 - #define TX4939_CRYPTO_CSR_PDINT_END 0x00000040 392 - #define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080 393 - #define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0 394 - #define TX4939_CRYPTO_CSR_GINTE 0x00000008 395 - #define TX4939_CRYPTO_CSR_RSTD 0x00000004 396 - #define TX4939_CRYPTO_CSR_RSTC 0x00000002 397 - #define TX4939_CRYPTO_CSR_ENCR 0x00000001 398 - 399 - /* bits for tx4939_crypto_reg.cdr.gen.ctrl */ 400 - #define TX4939_CRYPTO_CTX_ENGINE_MASK 0x00000003 401 - #define TX4939_CRYPTO_CTX_ENGINE_DES 0x00000000 402 - #define TX4939_CRYPTO_CTX_ENGINE_AES 0x00000001 403 - #define TX4939_CRYPTO_CTX_ENGINE_MD5 0x00000002 404 - #define TX4939_CRYPTO_CTX_ENGINE_SHA1 0x00000003 405 - #define TX4939_CRYPTO_CTX_TDMS 0x00000010 406 - #define TX4939_CRYPTO_CTX_CMS 0x00000020 407 - #define TX4939_CRYPTO_CTX_DMS 0x00000040 408 - #define TX4939_CRYPTO_CTX_UPDATE 0x00000080 409 - 410 - /* bits for tx4939_crypto_desc.ctrl */ 411 - #define TX4939_CRYPTO_DESC_OB_CNT_MASK 0xffe00000 412 - #define TX4939_CRYPTO_DESC_OB_CNT(cnt) ((cnt) << 21) 413 - #define TX4939_CRYPTO_DESC_IB_CNT_MASK 0x001ffc00 414 - #define TX4939_CRYPTO_DESC_IB_CNT(cnt) ((cnt) << 10) 415 - #define TX4939_CRYPTO_DESC_START 0x00000200 416 - #define TX4939_CRYPTO_DESC_END 0x00000100 417 - #define TX4939_CRYPTO_DESC_XOR 0x00000010 418 - #define TX4939_CRYPTO_DESC_LAST 0x00000008 419 - #define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006 420 - #define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000 421 - #define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002 422 - #define TX4939_CRYPTO_DESC_ERR_DIGEST 0x00000004 423 - #define TX4939_CRYPTO_DESC_OWN 0x00000001 424 - 425 - /* bits for tx4939_crypto_desc.index */ 426 - #define TX4939_CRYPTO_DESC_HASH_IDX_MASK 0x00000070 427 - #define TX4939_CRYPTO_DESC_HASH_IDX(idx) ((idx) << 4) 428 - #define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK 0x00000007 429 - #define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx) ((idx) << 0) 430 - 431 - #define TX4939_CRYPTO_NR_SET 6 432 - 433 - #define TX4939_CRYPTO_RCSR_INTE 0x00000008 434 - #define TX4939_CRYPTO_RCSR_RST 0x00000004 435 - #define TX4939_CRYPTO_RCSR_FIN 0x00000002 436 - #define TX4939_CRYPTO_RCSR_ST 0x00000001 437 - 438 - /* 439 - * VPC 440 - */ 441 - #define TX4939_VPC_CSR_GBINT 0x00010000 442 - #define TX4939_VPC_CSR_SWAPO 0x00000020 443 - #define TX4939_VPC_CSR_SWAPI 0x00000010 444 - #define TX4939_VPC_CSR_GINTE 0x00000008 445 - #define TX4939_VPC_CSR_RSTD 0x00000004 446 - #define TX4939_VPC_CSR_RSTVPC 0x00000002 447 - 448 - #define TX4939_VPC_CTRLA_VDPSN 0x00000200 449 - #define TX4939_VPC_CTRLA_PBUSY 0x00000100 450 - #define TX4939_VPC_CTRLA_DCINT 0x00000080 451 - #define TX4939_VPC_CTRLA_UOINT 0x00000040 452 - #define TX4939_VPC_CTRLA_PDINT_MASK 0x00000030 453 - #define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000 454 - #define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010 455 - #define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030 456 - #define TX4939_VPC_CTRLA_VDVLDP 0x00000008 457 - #define TX4939_VPC_CTRLA_VDMODE 0x00000004 458 - #define TX4939_VPC_CTRLA_VDFOR 0x00000002 459 - #define TX4939_VPC_CTRLA_ENVPC 0x00000001 460 - 461 - /* bits for tx4939_vpc_desc.ctrl1 */ 462 - #define TX4939_VPC_DESC_CTRL1_ERR_MASK 0x00000006 463 - #define TX4939_VPC_DESC_CTRL1_OWN 0x00000001 464 - 465 - #define tx4939_ddrcptr ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG) 466 - #define tx4939_ebuscptr tx4938_ebuscptr 467 - #define tx4939_ircptr \ 468 - ((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG) 469 - #define tx4939_pcicptr tx4938_pcicptr 470 - #define tx4939_pcic1ptr tx4938_pcic1ptr 471 - #define tx4939_ccfgptr \ 472 - ((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG) 473 - #define tx4939_sramcptr tx4938_sramcptr 474 - #define tx4939_cryptoptr \ 475 - ((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG) 476 - #define tx4939_vpcptr ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG) 477 - 478 - #define TX4939_REV_MAJ_MIN() \ 479 - ((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff) 480 - #define TX4939_REV_PCODE() \ 481 - ((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16) 482 - #define TX4939_CCFG_BCFG() \ 483 - ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \ 484 - >> 32)) 485 - 486 - #define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits) 487 - #define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits) 488 - #define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new) 489 - 490 - #define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch) 491 - #define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch) 492 - #define TX4939_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) 493 - #define TX4939_EBUSC_WIDTH(ch) \ 494 - (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1)) 495 - 496 - /* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */ 497 - #define TX4939_SCLK0(mst) \ 498 - ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2) 499 - 500 - void tx4939_wdt_init(void); 501 - void tx4939_setup(void); 502 - void tx4939_time_init(unsigned int tmrnr); 503 - void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask); 504 - void tx4939_spi_init(int busid); 505 - void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1); 506 - int tx4939_report_pciclk(void); 507 - void tx4939_report_pci1clk(void); 508 - struct pci_dev; 509 - int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot); 510 - int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); 511 - void tx4939_setup_pcierr_irq(void); 512 - void tx4939_irq_init(void); 513 - int tx4939_irq(void); 514 - void tx4939_mtd_init(int ch); 515 - void tx4939_ata_init(void); 516 - void tx4939_rtc_init(void); 517 - void tx4939_ndfmc_init(unsigned int hold, unsigned int spw, 518 - unsigned char ch_mask, unsigned char wide_mask); 519 - void tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1); 520 - void tx4939_aclc_init(void); 521 - void tx4939_sramc_init(void); 522 - void tx4939_rng_init(void); 523 - 524 - #endif /* __ASM_TXX9_TX4939_H */
-1
arch/mips/pci/Makefile
··· 49 49 obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o 50 50 obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o 51 51 obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o 52 - obj-$(CONFIG_SOC_TX4939) += pci-tx4939.o 53 52 obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o 54 53 obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 55 54 obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
-107
arch/mips/pci/pci-tx4939.c
··· 1 - /* 2 - * Based on linux/arch/mips/txx9/rbtx4939/setup.c, 3 - * and RBTX49xx patch from CELF patch archive. 4 - * 5 - * Copyright 2001, 2003-2005 MontaVista Software Inc. 6 - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 7 - * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 8 - * 9 - * This file is subject to the terms and conditions of the GNU General Public 10 - * License. See the file "COPYING" in the main directory of this archive 11 - * for more details. 12 - */ 13 - #include <linux/init.h> 14 - #include <linux/pci.h> 15 - #include <linux/kernel.h> 16 - #include <linux/interrupt.h> 17 - #include <asm/txx9/generic.h> 18 - #include <asm/txx9/tx4939.h> 19 - 20 - int __init tx4939_report_pciclk(void) 21 - { 22 - int pciclk = 0; 23 - 24 - pr_info("PCIC --%s PCICLK:", 25 - (__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66) ? 26 - " PCI66" : ""); 27 - if (__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_PCICLKEN_ALL) { 28 - pciclk = txx9_master_clock * 20 / 6; 29 - if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66)) 30 - pciclk /= 2; 31 - pr_cont("Internal(%u.%uMHz)", 32 - (pciclk + 50000) / 1000000, 33 - ((pciclk + 50000) / 100000) % 10); 34 - } else { 35 - pr_cont("External"); 36 - pciclk = -1; 37 - } 38 - pr_cont("\n"); 39 - return pciclk; 40 - } 41 - 42 - void __init tx4939_report_pci1clk(void) 43 - { 44 - unsigned int pciclk = txx9_master_clock * 20 / 6; 45 - 46 - pr_info("PCIC1 -- PCICLK:%u.%uMHz\n", 47 - (pciclk + 50000) / 1000000, 48 - ((pciclk + 50000) / 100000) % 10); 49 - } 50 - 51 - int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot) 52 - { 53 - if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) { 54 - switch (slot) { 55 - case TX4927_PCIC_IDSEL_AD_TO_SLOT(31): 56 - if (__raw_readq(&tx4939_ccfgptr->pcfg) & 57 - TX4939_PCFG_ET0MODE) 58 - return TXX9_IRQ_BASE + TX4939_IR_ETH(0); 59 - break; 60 - case TX4927_PCIC_IDSEL_AD_TO_SLOT(30): 61 - if (__raw_readq(&tx4939_ccfgptr->pcfg) & 62 - TX4939_PCFG_ET1MODE) 63 - return TXX9_IRQ_BASE + TX4939_IR_ETH(1); 64 - break; 65 - } 66 - return 0; 67 - } 68 - return -1; 69 - } 70 - 71 - int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 72 - { 73 - int irq = tx4939_pcic1_map_irq(dev, slot); 74 - 75 - if (irq >= 0) 76 - return irq; 77 - irq = pin; 78 - /* IRQ rotation */ 79 - irq--; /* 0-3 */ 80 - irq = (irq + 33 - slot) % 4; 81 - irq++; /* 1-4 */ 82 - 83 - switch (irq) { 84 - case 1: 85 - irq = TXX9_IRQ_BASE + TX4939_IR_INTA; 86 - break; 87 - case 2: 88 - irq = TXX9_IRQ_BASE + TX4939_IR_INTB; 89 - break; 90 - case 3: 91 - irq = TXX9_IRQ_BASE + TX4939_IR_INTC; 92 - break; 93 - case 4: 94 - irq = TXX9_IRQ_BASE + TX4939_IR_INTD; 95 - break; 96 - } 97 - return irq; 98 - } 99 - 100 - void __init tx4939_setup_pcierr_irq(void) 101 - { 102 - if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR, 103 - tx4927_pcierr_interrupt, 104 - 0, "PCI error", 105 - (void *)TX4939_PCIC_REG)) 106 - pr_warn("Failed to request irq for PCIERR\n"); 107 - }
-7
arch/mips/txx9/Kconfig
··· 65 65 select PCI_TX4927 66 66 select GPIO_TXX9 67 67 68 - config SOC_TX4939 69 - bool 70 - select CEVT_TXX9 71 - imply HAS_TXX9_SERIAL 72 - select HAVE_PCI 73 - select PCI_TX4927 74 - 75 68 config TOSHIBA_FPCIB0 76 69 bool "FPCIB0 Backplane Support" 77 70 depends on PCI && MACH_TXX9
-1
arch/mips/txx9/generic/Makefile
··· 8 8 obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o 9 9 obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o 10 10 obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o 11 - obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o 12 11 obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
-216
arch/mips/txx9/generic/irq_tx4939.c
··· 1 - /* 2 - * TX4939 irq routines 3 - * Based on linux/arch/mips/kernel/irq_txx9.c, 4 - * and RBTX49xx patch from CELF patch archive. 5 - * 6 - * Copyright 2001, 2003-2005 MontaVista Software Inc. 7 - * Author: MontaVista Software, Inc. 8 - * ahennessy@mvista.com 9 - * source@mvista.com 10 - * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation 11 - * 12 - * This file is subject to the terms and conditions of the GNU General Public 13 - * License. See the file "COPYING" in the main directory of this archive 14 - * for more details. 15 - */ 16 - /* 17 - * TX4939 defines 64 IRQs. 18 - * Similer to irq_txx9.c but different register layouts. 19 - */ 20 - #include <linux/init.h> 21 - #include <linux/interrupt.h> 22 - #include <linux/irq.h> 23 - #include <linux/types.h> 24 - #include <asm/irq_cpu.h> 25 - #include <asm/txx9irq.h> 26 - #include <asm/txx9/tx4939.h> 27 - 28 - /* IRCER : Int. Control Enable */ 29 - #define TXx9_IRCER_ICE 0x00000001 30 - 31 - /* IRCR : Int. Control */ 32 - #define TXx9_IRCR_LOW 0x00000000 33 - #define TXx9_IRCR_HIGH 0x00000001 34 - #define TXx9_IRCR_DOWN 0x00000002 35 - #define TXx9_IRCR_UP 0x00000003 36 - #define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002) 37 - 38 - /* IRSCR : Int. Status Control */ 39 - #define TXx9_IRSCR_EIClrE 0x00000100 40 - #define TXx9_IRSCR_EIClr_MASK 0x0000000f 41 - 42 - /* IRCSR : Int. Current Status */ 43 - #define TXx9_IRCSR_IF 0x00010000 44 - 45 - #define irc_dlevel 0 46 - #define irc_elevel 1 47 - 48 - static struct { 49 - unsigned char level; 50 - unsigned char mode; 51 - } tx4939irq[TX4939_NUM_IR] __read_mostly; 52 - 53 - static void tx4939_irq_unmask(struct irq_data *d) 54 - { 55 - unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; 56 - u32 __iomem *lvlp; 57 - int ofs; 58 - if (irq_nr < 32) { 59 - irq_nr--; 60 - lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r; 61 - } else { 62 - irq_nr -= 32; 63 - lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r; 64 - } 65 - ofs = (irq_nr & 16) + (irq_nr & 1) * 8; 66 - __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) 67 - | (tx4939irq[irq_nr].level << ofs), 68 - lvlp); 69 - } 70 - 71 - static inline void tx4939_irq_mask(struct irq_data *d) 72 - { 73 - unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; 74 - u32 __iomem *lvlp; 75 - int ofs; 76 - if (irq_nr < 32) { 77 - irq_nr--; 78 - lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r; 79 - } else { 80 - irq_nr -= 32; 81 - lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r; 82 - } 83 - ofs = (irq_nr & 16) + (irq_nr & 1) * 8; 84 - __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) 85 - | (irc_dlevel << ofs), 86 - lvlp); 87 - mmiowb(); 88 - } 89 - 90 - static void tx4939_irq_mask_ack(struct irq_data *d) 91 - { 92 - unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; 93 - 94 - tx4939_irq_mask(d); 95 - if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) { 96 - irq_nr--; 97 - /* clear edge detection */ 98 - __raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf)) 99 - << (irq_nr & 0x10), 100 - &tx4939_ircptr->edc.r); 101 - } 102 - } 103 - 104 - static int tx4939_irq_set_type(struct irq_data *d, unsigned int flow_type) 105 - { 106 - unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; 107 - u32 cr; 108 - u32 __iomem *crp; 109 - int ofs; 110 - int mode; 111 - 112 - if (flow_type & IRQF_TRIGGER_PROBE) 113 - return 0; 114 - switch (flow_type & IRQF_TRIGGER_MASK) { 115 - case IRQF_TRIGGER_RISING: 116 - mode = TXx9_IRCR_UP; 117 - break; 118 - case IRQF_TRIGGER_FALLING: 119 - mode = TXx9_IRCR_DOWN; 120 - break; 121 - case IRQF_TRIGGER_HIGH: 122 - mode = TXx9_IRCR_HIGH; 123 - break; 124 - case IRQF_TRIGGER_LOW: 125 - mode = TXx9_IRCR_LOW; 126 - break; 127 - default: 128 - return -EINVAL; 129 - } 130 - if (irq_nr < 32) { 131 - irq_nr--; 132 - crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r; 133 - } else { 134 - irq_nr -= 32; 135 - crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r; 136 - } 137 - ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2; 138 - cr = __raw_readl(crp); 139 - cr &= ~(0x3 << ofs); 140 - cr |= (mode & 0x3) << ofs; 141 - __raw_writel(cr, crp); 142 - tx4939irq[irq_nr].mode = mode; 143 - return 0; 144 - } 145 - 146 - static struct irq_chip tx4939_irq_chip = { 147 - .name = "TX4939", 148 - .irq_ack = tx4939_irq_mask_ack, 149 - .irq_mask = tx4939_irq_mask, 150 - .irq_mask_ack = tx4939_irq_mask_ack, 151 - .irq_unmask = tx4939_irq_unmask, 152 - .irq_set_type = tx4939_irq_set_type, 153 - }; 154 - 155 - static int tx4939_irq_set_pri(int irc_irq, int new_pri) 156 - { 157 - int old_pri; 158 - 159 - if ((unsigned int)irc_irq >= TX4939_NUM_IR) 160 - return 0; 161 - old_pri = tx4939irq[irc_irq].level; 162 - tx4939irq[irc_irq].level = new_pri; 163 - return old_pri; 164 - } 165 - 166 - void __init tx4939_irq_init(void) 167 - { 168 - int i; 169 - 170 - mips_cpu_irq_init(); 171 - /* disable interrupt control */ 172 - __raw_writel(0, &tx4939_ircptr->den.r); 173 - __raw_writel(0, &tx4939_ircptr->maskint.r); 174 - __raw_writel(0, &tx4939_ircptr->maskext.r); 175 - /* irq_base + 0 is not used */ 176 - for (i = 1; i < TX4939_NUM_IR; i++) { 177 - tx4939irq[i].level = 4; /* middle level */ 178 - tx4939irq[i].mode = TXx9_IRCR_LOW; 179 - irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip, 180 - handle_level_irq); 181 - } 182 - 183 - /* mask all IRC interrupts */ 184 - __raw_writel(0, &tx4939_ircptr->msk.r); 185 - for (i = 0; i < 16; i++) 186 - __raw_writel(0, &tx4939_ircptr->lvl[i].r); 187 - /* setup IRC interrupt mode (Low Active) */ 188 - for (i = 0; i < 2; i++) 189 - __raw_writel(0, &tx4939_ircptr->dm[i].r); 190 - for (i = 0; i < 2; i++) 191 - __raw_writel(0, &tx4939_ircptr->dm2[i].r); 192 - /* enable interrupt control */ 193 - __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r); 194 - __raw_writel(irc_elevel, &tx4939_ircptr->msk.r); 195 - 196 - irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, 197 - handle_simple_irq); 198 - 199 - /* raise priority for errors, timers, sio */ 200 - tx4939_irq_set_pri(TX4939_IR_WTOERR, 7); 201 - tx4939_irq_set_pri(TX4939_IR_PCIERR, 7); 202 - tx4939_irq_set_pri(TX4939_IR_PCIPME, 7); 203 - for (i = 0; i < TX4939_NUM_IR_TMR; i++) 204 - tx4939_irq_set_pri(TX4939_IR_TMR(i), 6); 205 - for (i = 0; i < TX4939_NUM_IR_SIO; i++) 206 - tx4939_irq_set_pri(TX4939_IR_SIO(i), 5); 207 - } 208 - 209 - int tx4939_irq(void) 210 - { 211 - u32 csr = __raw_readl(&tx4939_ircptr->cs.r); 212 - 213 - if (likely(!(csr & TXx9_IRCSR_IF))) 214 - return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1)); 215 - return -1; 216 - }
-568
arch/mips/txx9/generic/setup_tx4939.c
··· 1 - /* 2 - * TX4939 setup routines 3 - * Based on linux/arch/mips/txx9/generic/setup_tx4938.c, 4 - * and RBTX49xx patch from CELF patch archive. 5 - * 6 - * 2003-2005 (c) MontaVista Software, Inc. 7 - * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 8 - * 9 - * This file is subject to the terms and conditions of the GNU General Public 10 - * License. See the file "COPYING" in the main directory of this archive 11 - * for more details. 12 - */ 13 - #include <linux/init.h> 14 - #include <linux/ioport.h> 15 - #include <linux/delay.h> 16 - #include <linux/netdevice.h> 17 - #include <linux/notifier.h> 18 - #include <linux/device.h> 19 - #include <linux/ethtool.h> 20 - #include <linux/param.h> 21 - #include <linux/ptrace.h> 22 - #include <linux/mtd/physmap.h> 23 - #include <linux/platform_device.h> 24 - #include <linux/platform_data/txx9/ndfmc.h> 25 - #include <asm/reboot.h> 26 - #include <asm/traps.h> 27 - #include <asm/txx9irq.h> 28 - #include <asm/txx9tmr.h> 29 - #include <asm/txx9/generic.h> 30 - #include <asm/txx9/dmac.h> 31 - #include <asm/txx9/tx4939.h> 32 - 33 - static void __init tx4939_wdr_init(void) 34 - { 35 - /* report watchdog reset status */ 36 - if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST) 37 - pr_warn("Watchdog reset detected at 0x%lx\n", 38 - read_c0_errorepc()); 39 - /* clear WatchDogReset (W1C) */ 40 - tx4939_ccfg_set(TX4939_CCFG_WDRST); 41 - /* do reset on watchdog */ 42 - tx4939_ccfg_set(TX4939_CCFG_WR); 43 - } 44 - 45 - void __init tx4939_wdt_init(void) 46 - { 47 - txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL); 48 - } 49 - 50 - static void tx4939_machine_restart(char *command) 51 - { 52 - local_irq_disable(); 53 - pr_emerg("Rebooting (with %s watchdog reset)...\n", 54 - (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ? 55 - "external" : "internal"); 56 - /* clear watchdog status */ 57 - tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */ 58 - txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL); 59 - while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)) 60 - ; 61 - mdelay(10); 62 - if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) { 63 - pr_emerg("Rebooting (with internal watchdog reset)...\n"); 64 - /* External WDRST failed. Do internal watchdog reset */ 65 - tx4939_ccfg_clear(TX4939_CCFG_WDREXEN); 66 - } 67 - /* fallback */ 68 - (*_machine_halt)(); 69 - } 70 - 71 - void show_registers(struct pt_regs *regs); 72 - static int tx4939_be_handler(struct pt_regs *regs, int is_fixup) 73 - { 74 - int data = regs->cp0_cause & 4; 75 - console_verbose(); 76 - pr_err("%cBE exception at %#lx\n", 77 - data ? 'D' : 'I', regs->cp0_epc); 78 - pr_err("ccfg:%llx, toea:%llx\n", 79 - (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg), 80 - (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea)); 81 - #ifdef CONFIG_PCI 82 - tx4927_report_pcic_status(); 83 - #endif 84 - show_registers(regs); 85 - panic("BusError!"); 86 - } 87 - static void __init tx4939_be_init(void) 88 - { 89 - mips_set_be_handler(tx4939_be_handler); 90 - } 91 - 92 - static struct resource tx4939_sdram_resource[4]; 93 - static struct resource tx4939_sram_resource; 94 - #define TX4939_SRAM_SIZE 0x800 95 - 96 - void __init tx4939_setup(void) 97 - { 98 - int i; 99 - __u32 divmode; 100 - __u64 pcfg; 101 - unsigned int cpuclk = 0; 102 - 103 - txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE, 104 - TX4939_REG_SIZE); 105 - set_c0_config(TX49_CONF_CWFON); 106 - 107 - /* SDRAMC,EBUSC are configured by PROM */ 108 - for (i = 0; i < 4; i++) { 109 - if (!(TX4939_EBUSC_CR(i) & 0x8)) 110 - continue; /* disabled */ 111 - txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i); 112 - txx9_ce_res[i].end = 113 - txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1; 114 - request_resource(&iomem_resource, &txx9_ce_res[i]); 115 - } 116 - 117 - /* clocks */ 118 - if (txx9_master_clock) { 119 - /* calculate cpu_clock from master_clock */ 120 - divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) & 121 - TX4939_CCFG_MULCLK_MASK; 122 - cpuclk = txx9_master_clock * 20 / 2; 123 - switch (divmode) { 124 - case TX4939_CCFG_MULCLK_8: 125 - cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break; 126 - case TX4939_CCFG_MULCLK_9: 127 - cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break; 128 - case TX4939_CCFG_MULCLK_10: 129 - cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break; 130 - case TX4939_CCFG_MULCLK_11: 131 - cpuclk = cpuclk / 6 * 11; break; 132 - case TX4939_CCFG_MULCLK_12: 133 - cpuclk = cpuclk * 2 /* / 6 * 12 */; break; 134 - case TX4939_CCFG_MULCLK_13: 135 - cpuclk = cpuclk / 6 * 13; break; 136 - case TX4939_CCFG_MULCLK_14: 137 - cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break; 138 - case TX4939_CCFG_MULCLK_15: 139 - cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break; 140 - } 141 - txx9_cpu_clock = cpuclk; 142 - } else { 143 - if (txx9_cpu_clock == 0) 144 - txx9_cpu_clock = 400000000; /* 400MHz */ 145 - /* calculate master_clock from cpu_clock */ 146 - cpuclk = txx9_cpu_clock; 147 - divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) & 148 - TX4939_CCFG_MULCLK_MASK; 149 - switch (divmode) { 150 - case TX4939_CCFG_MULCLK_8: 151 - txx9_master_clock = cpuclk * 6 / 8; break; 152 - case TX4939_CCFG_MULCLK_9: 153 - txx9_master_clock = cpuclk * 6 / 9; break; 154 - case TX4939_CCFG_MULCLK_10: 155 - txx9_master_clock = cpuclk * 6 / 10; break; 156 - case TX4939_CCFG_MULCLK_11: 157 - txx9_master_clock = cpuclk * 6 / 11; break; 158 - case TX4939_CCFG_MULCLK_12: 159 - txx9_master_clock = cpuclk * 6 / 12; break; 160 - case TX4939_CCFG_MULCLK_13: 161 - txx9_master_clock = cpuclk * 6 / 13; break; 162 - case TX4939_CCFG_MULCLK_14: 163 - txx9_master_clock = cpuclk * 6 / 14; break; 164 - case TX4939_CCFG_MULCLK_15: 165 - txx9_master_clock = cpuclk * 6 / 15; break; 166 - } 167 - txx9_master_clock /= 10; /* * 2 / 20 */ 168 - } 169 - /* calculate gbus_clock from cpu_clock */ 170 - divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) & 171 - TX4939_CCFG_YDIVMODE_MASK; 172 - txx9_gbus_clock = txx9_cpu_clock; 173 - switch (divmode) { 174 - case TX4939_CCFG_YDIVMODE_2: 175 - txx9_gbus_clock /= 2; break; 176 - case TX4939_CCFG_YDIVMODE_3: 177 - txx9_gbus_clock /= 3; break; 178 - case TX4939_CCFG_YDIVMODE_5: 179 - txx9_gbus_clock /= 5; break; 180 - case TX4939_CCFG_YDIVMODE_6: 181 - txx9_gbus_clock /= 6; break; 182 - } 183 - /* change default value to udelay/mdelay take reasonable time */ 184 - loops_per_jiffy = txx9_cpu_clock / HZ / 2; 185 - 186 - /* CCFG */ 187 - tx4939_wdr_init(); 188 - /* clear BusErrorOnWrite flag (W1C) */ 189 - tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW); 190 - /* enable Timeout BusError */ 191 - if (txx9_ccfg_toeon) 192 - tx4939_ccfg_set(TX4939_CCFG_TOE); 193 - 194 - /* DMA selection */ 195 - txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL); 196 - 197 - /* Use external clock for external arbiter */ 198 - if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB)) 199 - txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL); 200 - 201 - pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", 202 - txx9_pcode_str, 203 - (cpuclk + 500000) / 1000000, 204 - (txx9_master_clock + 500000) / 1000000, 205 - (txx9_gbus_clock + 500000) / 1000000, 206 - (__u32)____raw_readq(&tx4939_ccfgptr->crir), 207 - ____raw_readq(&tx4939_ccfgptr->ccfg), 208 - ____raw_readq(&tx4939_ccfgptr->pcfg)); 209 - 210 - pr_info("%s DDRC -- EN:%08x", txx9_pcode_str, 211 - (__u32)____raw_readq(&tx4939_ddrcptr->winen)); 212 - for (i = 0; i < 4; i++) { 213 - __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]); 214 - if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i))) 215 - continue; /* disabled */ 216 - pr_cont(" #%d:%016llx", i, win); 217 - tx4939_sdram_resource[i].name = "DDR SDRAM"; 218 - tx4939_sdram_resource[i].start = 219 - (unsigned long)(win >> 48) << 20; 220 - tx4939_sdram_resource[i].end = 221 - ((((unsigned long)(win >> 32) & 0xffff) + 1) << 222 - 20) - 1; 223 - tx4939_sdram_resource[i].flags = IORESOURCE_MEM; 224 - request_resource(&iomem_resource, &tx4939_sdram_resource[i]); 225 - } 226 - pr_cont("\n"); 227 - 228 - /* SRAM */ 229 - if (____raw_readq(&tx4939_sramcptr->cr) & 1) { 230 - unsigned int size = TX4939_SRAM_SIZE; 231 - tx4939_sram_resource.name = "SRAM"; 232 - tx4939_sram_resource.start = 233 - (____raw_readq(&tx4939_sramcptr->cr) >> (39-11)) 234 - & ~(size - 1); 235 - tx4939_sram_resource.end = 236 - tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1; 237 - tx4939_sram_resource.flags = IORESOURCE_MEM; 238 - request_resource(&iomem_resource, &tx4939_sram_resource); 239 - } 240 - 241 - /* TMR */ 242 - /* disable all timers */ 243 - for (i = 0; i < TX4939_NR_TMR; i++) 244 - txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL); 245 - 246 - /* set PCIC1 reset (required to prevent hangup on BIST) */ 247 - txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST); 248 - pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg); 249 - if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) { 250 - mdelay(1); /* at least 128 cpu clock */ 251 - /* clear PCIC1 reset */ 252 - txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST); 253 - } else { 254 - pr_info("%s: stop PCIC1\n", txx9_pcode_str); 255 - /* stop PCIC1 */ 256 - txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD); 257 - } 258 - if (!(pcfg & TX4939_PCFG_ET0MODE)) { 259 - pr_info("%s: stop ETH0\n", txx9_pcode_str); 260 - txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST); 261 - txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD); 262 - } 263 - if (!(pcfg & TX4939_PCFG_ET1MODE)) { 264 - pr_info("%s: stop ETH1\n", txx9_pcode_str); 265 - txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST); 266 - txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD); 267 - } 268 - 269 - _machine_restart = tx4939_machine_restart; 270 - board_be_init = tx4939_be_init; 271 - } 272 - 273 - void __init tx4939_time_init(unsigned int tmrnr) 274 - { 275 - if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS) 276 - txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL, 277 - TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr), 278 - TXX9_IMCLK); 279 - } 280 - 281 - void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask) 282 - { 283 - int i; 284 - unsigned int ch_mask = 0; 285 - __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg); 286 - 287 - cts_mask |= ~1; /* only SIO0 have RTS/CTS */ 288 - if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0) 289 - cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */ 290 - if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) 291 - ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */ 292 - if (pcfg & TX4939_PCFG_SIO3MODE) 293 - ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */ 294 - for (i = 0; i < 4; i++) { 295 - if ((1 << i) & ch_mask) 296 - continue; 297 - txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL, 298 - TXX9_IRQ_BASE + TX4939_IR_SIO(i), 299 - i, sclk, (1 << i) & cts_mask); 300 - } 301 - } 302 - 303 - #if IS_ENABLED(CONFIG_TC35815) 304 - static u32 tx4939_get_eth_speed(struct net_device *dev) 305 - { 306 - struct ethtool_link_ksettings cmd; 307 - 308 - if (__ethtool_get_link_ksettings(dev, &cmd)) 309 - return 100; /* default 100Mbps */ 310 - 311 - return cmd.base.speed; 312 - } 313 - 314 - static int tx4939_netdev_event(struct notifier_block *this, 315 - unsigned long event, 316 - void *ptr) 317 - { 318 - struct net_device *dev = netdev_notifier_info_to_dev(ptr); 319 - 320 - if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) { 321 - __u64 bit = 0; 322 - if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0)) 323 - bit = TX4939_PCFG_SPEED0; 324 - else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1)) 325 - bit = TX4939_PCFG_SPEED1; 326 - if (bit) { 327 - if (tx4939_get_eth_speed(dev) == 100) 328 - txx9_set64(&tx4939_ccfgptr->pcfg, bit); 329 - else 330 - txx9_clear64(&tx4939_ccfgptr->pcfg, bit); 331 - } 332 - } 333 - return NOTIFY_DONE; 334 - } 335 - 336 - static struct notifier_block tx4939_netdev_notifier = { 337 - .notifier_call = tx4939_netdev_event, 338 - .priority = 1, 339 - }; 340 - 341 - void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1) 342 - { 343 - u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg); 344 - 345 - if (addr0 && (pcfg & TX4939_PCFG_ET0MODE)) 346 - txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0); 347 - if (addr1 && (pcfg & TX4939_PCFG_ET1MODE)) 348 - txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1); 349 - register_netdevice_notifier(&tx4939_netdev_notifier); 350 - } 351 - #else 352 - void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1) 353 - { 354 - } 355 - #endif 356 - 357 - void __init tx4939_mtd_init(int ch) 358 - { 359 - struct physmap_flash_data pdata = { 360 - .width = TX4939_EBUSC_WIDTH(ch) / 8, 361 - }; 362 - unsigned long start = txx9_ce_res[ch].start; 363 - unsigned long size = txx9_ce_res[ch].end - start + 1; 364 - 365 - if (!(TX4939_EBUSC_CR(ch) & 0x8)) 366 - return; /* disabled */ 367 - txx9_physmap_flash_init(ch, start, size, &pdata); 368 - } 369 - 370 - #define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL) 371 - void __init tx4939_ata_init(void) 372 - { 373 - static struct resource ata0_res[] = { 374 - { 375 - .start = TX4939_ATA_REG_PHYS(0), 376 - .end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1, 377 - .flags = IORESOURCE_MEM, 378 - }, { 379 - .start = TXX9_IRQ_BASE + TX4939_IR_ATA(0), 380 - .flags = IORESOURCE_IRQ, 381 - }, 382 - }; 383 - static struct resource ata1_res[] = { 384 - { 385 - .start = TX4939_ATA_REG_PHYS(1), 386 - .end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1, 387 - .flags = IORESOURCE_MEM, 388 - }, { 389 - .start = TXX9_IRQ_BASE + TX4939_IR_ATA(1), 390 - .flags = IORESOURCE_IRQ, 391 - }, 392 - }; 393 - static struct platform_device ata0_dev = { 394 - .name = "tx4939ide", 395 - .id = 0, 396 - .num_resources = ARRAY_SIZE(ata0_res), 397 - .resource = ata0_res, 398 - }; 399 - static struct platform_device ata1_dev = { 400 - .name = "tx4939ide", 401 - .id = 1, 402 - .num_resources = ARRAY_SIZE(ata1_res), 403 - .resource = ata1_res, 404 - }; 405 - __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg); 406 - 407 - if (pcfg & TX4939_PCFG_ATA0MODE) 408 - platform_device_register(&ata0_dev); 409 - if ((pcfg & (TX4939_PCFG_ATA1MODE | 410 - TX4939_PCFG_ET1MODE | 411 - TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE) 412 - platform_device_register(&ata1_dev); 413 - } 414 - 415 - void __init tx4939_rtc_init(void) 416 - { 417 - static struct resource res[] = { 418 - { 419 - .start = TX4939_RTC_REG & 0xfffffffffULL, 420 - .end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1, 421 - .flags = IORESOURCE_MEM, 422 - }, { 423 - .start = TXX9_IRQ_BASE + TX4939_IR_RTC, 424 - .flags = IORESOURCE_IRQ, 425 - }, 426 - }; 427 - static struct platform_device rtc_dev = { 428 - .name = "tx4939rtc", 429 - .id = -1, 430 - .num_resources = ARRAY_SIZE(res), 431 - .resource = res, 432 - }; 433 - 434 - platform_device_register(&rtc_dev); 435 - } 436 - 437 - void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw, 438 - unsigned char ch_mask, unsigned char wide_mask) 439 - { 440 - struct txx9ndfmc_platform_data plat_data = { 441 - .shift = 1, 442 - .gbus_clock = txx9_gbus_clock, 443 - .hold = hold, 444 - .spw = spw, 445 - .flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD | 446 - NDFMC_PLAT_FLAG_DUMMYWRITE, 447 - .ch_mask = ch_mask, 448 - .wide_mask = wide_mask, 449 - }; 450 - txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data); 451 - } 452 - 453 - void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1) 454 - { 455 - struct txx9dmac_platform_data plat_data = { 456 - .have_64bit_regs = true, 457 - }; 458 - int i; 459 - 460 - for (i = 0; i < 2; i++) { 461 - plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0; 462 - txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL, 463 - TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0), 464 - &plat_data); 465 - } 466 - } 467 - 468 - void __init tx4939_aclc_init(void) 469 - { 470 - u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg); 471 - 472 - if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC) 473 - txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL, 474 - TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1); 475 - } 476 - 477 - void __init tx4939_sramc_init(void) 478 - { 479 - if (tx4939_sram_resource.start) 480 - txx9_sramc_init(&tx4939_sram_resource); 481 - } 482 - 483 - void __init tx4939_rng_init(void) 484 - { 485 - static struct resource res = { 486 - .start = TX4939_RNG_REG & 0xfffffffffULL, 487 - .end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1, 488 - .flags = IORESOURCE_MEM, 489 - }; 490 - static struct platform_device pdev = { 491 - .name = "tx4939-rng", 492 - .id = -1, 493 - .num_resources = 1, 494 - .resource = &res, 495 - }; 496 - 497 - platform_device_register(&pdev); 498 - } 499 - 500 - static void __init tx4939_stop_unused_modules(void) 501 - { 502 - __u64 pcfg, rst = 0, ckd = 0; 503 - char buf[128]; 504 - 505 - buf[0] = '\0'; 506 - local_irq_disable(); 507 - pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg); 508 - if ((pcfg & TX4939_PCFG_I2SMODE_MASK) != 509 - TX4939_PCFG_I2SMODE_ACLC) { 510 - rst |= TX4939_CLKCTR_ACLRST; 511 - ckd |= TX4939_CLKCTR_ACLCKD; 512 - strcat(buf, " ACLC"); 513 - } 514 - if ((pcfg & TX4939_PCFG_I2SMODE_MASK) != 515 - TX4939_PCFG_I2SMODE_I2S && 516 - (pcfg & TX4939_PCFG_I2SMODE_MASK) != 517 - TX4939_PCFG_I2SMODE_I2S_ALT) { 518 - rst |= TX4939_CLKCTR_I2SRST; 519 - ckd |= TX4939_CLKCTR_I2SCKD; 520 - strcat(buf, " I2S"); 521 - } 522 - if (!(pcfg & TX4939_PCFG_ATA0MODE)) { 523 - rst |= TX4939_CLKCTR_ATA0RST; 524 - ckd |= TX4939_CLKCTR_ATA0CKD; 525 - strcat(buf, " ATA0"); 526 - } 527 - if (!(pcfg & TX4939_PCFG_ATA1MODE)) { 528 - rst |= TX4939_CLKCTR_ATA1RST; 529 - ckd |= TX4939_CLKCTR_ATA1CKD; 530 - strcat(buf, " ATA1"); 531 - } 532 - if (pcfg & TX4939_PCFG_SPIMODE) { 533 - rst |= TX4939_CLKCTR_SPIRST; 534 - ckd |= TX4939_CLKCTR_SPICKD; 535 - strcat(buf, " SPI"); 536 - } 537 - if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) { 538 - rst |= TX4939_CLKCTR_VPCRST; 539 - ckd |= TX4939_CLKCTR_VPCCKD; 540 - strcat(buf, " VPC"); 541 - } 542 - if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) { 543 - rst |= TX4939_CLKCTR_SIO2RST; 544 - ckd |= TX4939_CLKCTR_SIO2CKD; 545 - strcat(buf, " SIO2"); 546 - } 547 - if (pcfg & TX4939_PCFG_SIO3MODE) { 548 - rst |= TX4939_CLKCTR_SIO3RST; 549 - ckd |= TX4939_CLKCTR_SIO3CKD; 550 - strcat(buf, " SIO3"); 551 - } 552 - if (rst | ckd) { 553 - txx9_set64(&tx4939_ccfgptr->clkctr, rst); 554 - txx9_set64(&tx4939_ccfgptr->clkctr, ckd); 555 - } 556 - local_irq_enable(); 557 - if (buf[0]) 558 - pr_info("%s: stop%s\n", txx9_pcode_str, buf); 559 - } 560 - 561 - static int __init tx4939_late_init(void) 562 - { 563 - if (txx9_pcode != 0x4939) 564 - return -ENODEV; 565 - tx4939_stop_unused_modules(); 566 - return 0; 567 - } 568 - late_initcall(tx4939_late_init);
-13
drivers/char/hw_random/Kconfig
··· 226 226 To compile this driver as a module, choose M here: the 227 227 module will be called virtio-rng. If unsure, say N. 228 228 229 - config HW_RANDOM_TX4939 230 - tristate "TX4939 Random Number Generator support" 231 - depends on SOC_TX4939 232 - default HW_RANDOM 233 - help 234 - This driver provides kernel-side support for the Random Number 235 - Generator hardware found on TX4939 SoC. 236 - 237 - To compile this driver as a module, choose M here: the 238 - module will be called tx4939-rng. 239 - 240 - If unsure, say Y. 241 - 242 229 config HW_RANDOM_MXC_RNGA 243 230 tristate "Freescale i.MX RNGA Random Number Generator" 244 231 depends on SOC_IMX31
-1
drivers/char/hw_random/Makefile
··· 20 20 obj-$(CONFIG_HW_RANDOM_OMAP3_ROM) += omap3-rom-rng.o 21 21 obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o 22 22 obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o 23 - obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o 24 23 obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o 25 24 obj-$(CONFIG_HW_RANDOM_IMX_RNGC) += imx-rngc.o 26 25 obj-$(CONFIG_HW_RANDOM_INGENIC_RNG) += ingenic-rng.o
-157
drivers/char/hw_random/tx4939-rng.c
··· 1 - /* 2 - * RNG driver for TX4939 Random Number Generators (RNG) 3 - * 4 - * Copyright (C) 2009 Atsushi Nemoto <anemo@mba.ocn.ne.jp> 5 - * 6 - * This file is subject to the terms and conditions of the GNU General Public 7 - * License. See the file "COPYING" in the main directory of this archive 8 - * for more details. 9 - */ 10 - #include <linux/err.h> 11 - #include <linux/module.h> 12 - #include <linux/kernel.h> 13 - #include <linux/init.h> 14 - #include <linux/delay.h> 15 - #include <linux/io.h> 16 - #include <linux/platform_device.h> 17 - #include <linux/hw_random.h> 18 - #include <linux/gfp.h> 19 - 20 - #define TX4939_RNG_RCSR 0x00000000 21 - #define TX4939_RNG_ROR(n) (0x00000018 + (n) * 8) 22 - 23 - #define TX4939_RNG_RCSR_INTE 0x00000008 24 - #define TX4939_RNG_RCSR_RST 0x00000004 25 - #define TX4939_RNG_RCSR_FIN 0x00000002 26 - #define TX4939_RNG_RCSR_ST 0x00000001 27 - 28 - struct tx4939_rng { 29 - struct hwrng rng; 30 - void __iomem *base; 31 - u64 databuf[3]; 32 - unsigned int data_avail; 33 - }; 34 - 35 - static void rng_io_start(void) 36 - { 37 - #ifndef CONFIG_64BIT 38 - /* 39 - * readq is reading a 64-bit register using a 64-bit load. On 40 - * a 32-bit kernel however interrupts or any other processor 41 - * exception would clobber the upper 32-bit of the processor 42 - * register so interrupts need to be disabled. 43 - */ 44 - local_irq_disable(); 45 - #endif 46 - } 47 - 48 - static void rng_io_end(void) 49 - { 50 - #ifndef CONFIG_64BIT 51 - local_irq_enable(); 52 - #endif 53 - } 54 - 55 - static u64 read_rng(void __iomem *base, unsigned int offset) 56 - { 57 - return ____raw_readq(base + offset); 58 - } 59 - 60 - static void write_rng(u64 val, void __iomem *base, unsigned int offset) 61 - { 62 - return ____raw_writeq(val, base + offset); 63 - } 64 - 65 - static int tx4939_rng_data_present(struct hwrng *rng, int wait) 66 - { 67 - struct tx4939_rng *rngdev = container_of(rng, struct tx4939_rng, rng); 68 - int i; 69 - 70 - if (rngdev->data_avail) 71 - return rngdev->data_avail; 72 - for (i = 0; i < 20; i++) { 73 - rng_io_start(); 74 - if (!(read_rng(rngdev->base, TX4939_RNG_RCSR) 75 - & TX4939_RNG_RCSR_ST)) { 76 - rngdev->databuf[0] = 77 - read_rng(rngdev->base, TX4939_RNG_ROR(0)); 78 - rngdev->databuf[1] = 79 - read_rng(rngdev->base, TX4939_RNG_ROR(1)); 80 - rngdev->databuf[2] = 81 - read_rng(rngdev->base, TX4939_RNG_ROR(2)); 82 - rngdev->data_avail = 83 - sizeof(rngdev->databuf) / sizeof(u32); 84 - /* Start RNG */ 85 - write_rng(TX4939_RNG_RCSR_ST, 86 - rngdev->base, TX4939_RNG_RCSR); 87 - wait = 0; 88 - } 89 - rng_io_end(); 90 - if (!wait) 91 - break; 92 - /* 90 bus clock cycles by default for generation */ 93 - ndelay(90 * 5); 94 - } 95 - return rngdev->data_avail; 96 - } 97 - 98 - static int tx4939_rng_data_read(struct hwrng *rng, u32 *buffer) 99 - { 100 - struct tx4939_rng *rngdev = container_of(rng, struct tx4939_rng, rng); 101 - 102 - rngdev->data_avail--; 103 - *buffer = *((u32 *)&rngdev->databuf + rngdev->data_avail); 104 - return sizeof(u32); 105 - } 106 - 107 - static int __init tx4939_rng_probe(struct platform_device *dev) 108 - { 109 - struct tx4939_rng *rngdev; 110 - int i; 111 - 112 - rngdev = devm_kzalloc(&dev->dev, sizeof(*rngdev), GFP_KERNEL); 113 - if (!rngdev) 114 - return -ENOMEM; 115 - rngdev->base = devm_platform_ioremap_resource(dev, 0); 116 - if (IS_ERR(rngdev->base)) 117 - return PTR_ERR(rngdev->base); 118 - 119 - rngdev->rng.name = dev_name(&dev->dev); 120 - rngdev->rng.data_present = tx4939_rng_data_present; 121 - rngdev->rng.data_read = tx4939_rng_data_read; 122 - 123 - rng_io_start(); 124 - /* Reset RNG */ 125 - write_rng(TX4939_RNG_RCSR_RST, rngdev->base, TX4939_RNG_RCSR); 126 - write_rng(0, rngdev->base, TX4939_RNG_RCSR); 127 - /* Start RNG */ 128 - write_rng(TX4939_RNG_RCSR_ST, rngdev->base, TX4939_RNG_RCSR); 129 - rng_io_end(); 130 - /* 131 - * Drop first two results. From the datasheet: 132 - * The quality of the random numbers generated immediately 133 - * after reset can be insufficient. Therefore, do not use 134 - * random numbers obtained from the first and second 135 - * generations; use the ones from the third or subsequent 136 - * generation. 137 - */ 138 - for (i = 0; i < 2; i++) { 139 - rngdev->data_avail = 0; 140 - if (!tx4939_rng_data_present(&rngdev->rng, 1)) 141 - return -EIO; 142 - } 143 - 144 - platform_set_drvdata(dev, rngdev); 145 - return devm_hwrng_register(&dev->dev, &rngdev->rng); 146 - } 147 - 148 - static struct platform_driver tx4939_rng_driver = { 149 - .driver = { 150 - .name = "tx4939-rng", 151 - }, 152 - }; 153 - 154 - module_platform_driver_probe(tx4939_rng_driver, tx4939_rng_probe); 155 - 156 - MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver for TX4939"); 157 - MODULE_LICENSE("GPL");
+1 -1
drivers/mtd/nand/raw/Kconfig
··· 308 308 309 309 config MTD_NAND_TXX9NDFMC 310 310 tristate "TXx9 NAND controller" 311 - depends on SOC_TX4938 || SOC_TX4939 || COMPILE_TEST 311 + depends on SOC_TX4938 || COMPILE_TEST 312 312 depends on HAS_IOMEM 313 313 help 314 314 This enables the NAND flash controller on the TXx9 SoCs.