tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amdgpu/gfx12: don't read registers in mqd init

Just use the default values. There's not need to
get the value from hardware and it could cause problems
if we do that at runtime and gfxoff is active.

Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher fc3c139c e27b36ea

+33 -15
+33 -15
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
··· 50 50 51 51 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 52 52 53 + #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 54 + #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 55 + #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 56 + #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 57 + #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 58 + #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 59 + #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 60 + 61 + #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 62 + #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 63 + #define regCP_MQD_CONTROL_DEFAULT 0x00000100 64 + #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 65 + #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 66 + #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 67 + #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 68 + #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 69 + 70 + 53 71 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 54 72 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 55 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); ··· 2909 2891 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2910 2892 2911 2893 /* set up mqd control */ 2912 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 2894 + tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2913 2895 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2914 2896 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2915 2897 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2916 2898 mqd->cp_gfx_mqd_control = tmp; 2917 2899 2918 2900 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2919 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 2901 + tmp = regCP_GFX_HQD_VMID_DEFAULT; 2920 2902 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2921 2903 mqd->cp_gfx_hqd_vmid = 0; 2922 2904 2923 2905 /* set up default queue priority level 2924 2906 * 0x0 = low priority, 0x1 = high priority */ 2925 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 2907 + tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2926 2908 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2927 2909 mqd->cp_gfx_hqd_queue_priority = tmp; 2928 2910 2929 2911 /* set up time quantum */ 2930 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 2912 + tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 2931 2913 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2932 2914 mqd->cp_gfx_hqd_quantum = tmp; 2933 2915 ··· 2949 2931 2950 2932 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2951 2933 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2952 - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 2934 + tmp = regCP_GFX_HQD_CNTL_DEFAULT; 2953 2935 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2954 2936 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2955 2937 #ifdef __BIG_ENDIAN ··· 2958 2940 mqd->cp_gfx_hqd_cntl = tmp; 2959 2941 2960 2942 /* set up cp_doorbell_control */ 2961 - tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2943 + tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 2962 2944 if (prop->use_doorbell) { 2963 2945 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2964 2946 DOORBELL_OFFSET, prop->doorbell_index); ··· 2970 2952 mqd->cp_rb_doorbell_control = tmp; 2971 2953 2972 2954 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2973 - mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 2955 + mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 2974 2956 2975 2957 /* active the queue */ 2976 2958 mqd->cp_gfx_hqd_active = 1; ··· 3065 3047 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3066 3048 3067 3049 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3068 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3050 + tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3069 3051 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3070 3052 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3071 3053 3072 3054 mqd->cp_hqd_eop_control = tmp; 3073 3055 3074 3056 /* enable doorbell? */ 3075 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3057 + tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3076 3058 3077 3059 if (prop->use_doorbell) { 3078 3060 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, ··· 3101 3083 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3102 3084 3103 3085 /* set MQD vmid to 0 */ 3104 - tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3086 + tmp = regCP_MQD_CONTROL_DEFAULT; 3105 3087 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3106 3088 mqd->cp_mqd_control = tmp; 3107 3089 ··· 3111 3093 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3112 3094 3113 3095 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3114 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3096 + tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3115 3097 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3116 3098 (order_base_2(prop->queue_size / 4) - 1)); 3117 3099 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, ··· 3136 3118 tmp = 0; 3137 3119 /* enable the doorbell if requested */ 3138 3120 if (prop->use_doorbell) { 3139 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3121 + tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3140 3122 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3141 3123 DOORBELL_OFFSET, prop->doorbell_index); 3142 3124 ··· 3151 3133 mqd->cp_hqd_pq_doorbell_control = tmp; 3152 3134 3153 3135 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3154 - mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3136 + mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3155 3137 3156 3138 /* set the vmid for the queue */ 3157 3139 mqd->cp_hqd_vmid = 0; 3158 3140 3159 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3141 + tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3160 3142 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3161 3143 mqd->cp_hqd_persistent_state = tmp; 3162 3144 3163 3145 /* set MIN_IB_AVAIL_SIZE */ 3164 - tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3146 + tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3165 3147 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3166 3148 mqd->cp_hqd_ib_control = tmp; 3167 3149