tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: optimize rlcg write for gfx_v10

For gfx10 boards, except for nv12, other boards take mmio write
rather than rlcg write

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Jack Zhang and committed by
Alex Deucher fc30e840 c45fbe1b

+19 -7
+19 -7
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 4710 4710 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 4711 4711 4712 4712 /* csib */ 4713 - WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 4714 - adev->gfx.rlc.clear_state_gpu_addr >> 32); 4715 - WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 4716 - adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 4717 - WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 4718 - 4713 + if (adev->asic_type == CHIP_NAVI12) { 4714 + WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 4715 + adev->gfx.rlc.clear_state_gpu_addr >> 32); 4716 + WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 4717 + adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 4718 + WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 4719 + } else { 4720 + WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 4721 + adev->gfx.rlc.clear_state_gpu_addr >> 32); 4722 + WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 4723 + adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 4724 + WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 4725 + } 4719 4726 return 0; 4720 4727 } 4721 4728 ··· 5330 5323 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5331 5324 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5332 5325 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5333 - WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5326 + 5327 + if (adev->asic_type == CHIP_NAVI12) { 5328 + WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5329 + } else { 5330 + WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5331 + } 5334 5332 5335 5333 for (i = 0; i < adev->usec_timeout; i++) { 5336 5334 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)