Merge branch 'i2c-embedded/for-3.4' of git://git.pengutronix.de/git/wsa/linux

+19

Documentation/devicetree/bindings/i2c/sirf-i2c.txt

··· 1 + I2C for SiRFprimaII platforms 2 + 3 + Required properties : 4 + - compatible : Must be "sirf,prima2-i2c" 5 + - reg: physical base address of the controller and length of memory mapped 6 + region. 7 + - interrupts: interrupt number to the cpu. 8 + 9 + Optional properties: 10 + - clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz. 11 + The absence of the propoerty indicates the default frequency 100 kHz. 12 + 13 + Examples : 14 + 15 + i2c0: i2c@b00e0000 { 16 + compatible = "sirf,prima2-i2c"; 17 + reg = <0xb00e0000 0x10000>; 18 + interrupts = <24>; 19 + };

+32 -12

drivers/i2c/busses/Kconfig

··· 369 369 This driver can also be built as a module. If so, the module 370 370 will be called i2c-designware-pci. 371 371 372 + config I2C_EG20T 373 + tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) I2C" 374 + depends on PCI 375 + help 376 + This driver is for PCH(Platform controller Hub) I2C of EG20T which 377 + is an IOH(Input/Output Hub) for x86 embedded processor. 378 + This driver can access PCH I2C bus device. 379 + 380 + This driver also can be used for LAPIS Semiconductor IOH(Input/ 381 + Output Hub), ML7213, ML7223 and ML7831. 382 + ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is 383 + for MP(Media Phone) use and ML7831 IOH is for general purpose use. 384 + ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. 385 + ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. 386 + 372 387 config I2C_GPIO 373 388 tristate "GPIO-based bitbanging I2C" 374 389 depends on GENERIC_GPIO ··· 645 630 This driver can also be built as a module. If so, the module 646 631 will be called i2c-simtec. 647 632 633 + config I2C_SIRF 634 + tristate "CSR SiRFprimaII I2C interface" 635 + depends on ARCH_PRIMA2 636 + help 637 + If you say yes to this option, support will be included for the 638 + CSR SiRFprimaII I2C interface. 639 + 640 + This driver can also be built as a module. If so, the module 641 + will be called i2c-sirf. 642 + 648 643 config I2C_STU300 649 644 tristate "ST Microelectronics DDC I2C interface" 650 645 depends on MACH_U300 ··· 706 681 This driver can also be built as a module. If so, the module 707 682 will be called xilinx_i2c. 708 683 709 - config I2C_EG20T 710 - tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) I2C" 711 - depends on PCI 684 + config I2C_XLR 685 + tristate "XLR I2C support" 686 + depends on CPU_XLR 712 687 help 713 - This driver is for PCH(Platform controller Hub) I2C of EG20T which 714 - is an IOH(Input/Output Hub) for x86 embedded processor. 715 - This driver can access PCH I2C bus device. 688 + This driver enables support for the on-chip I2C interface of 689 + the Netlogic XLR/XLS MIPS processors. 716 690 717 - This driver also can be used for LAPIS Semiconductor IOH(Input/ 718 - Output Hub), ML7213, ML7223 and ML7831. 719 - ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is 720 - for MP(Media Phone) use and ML7831 IOH is for general purpose use. 721 - ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. 722 - ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. 691 + This driver can also be built as a module. If so, the module 692 + will be called i2c-xlr. 723 693 724 694 comment "External I2C/SMBus adapter drivers" 725 695

+3 -1

drivers/i2c/busses/Makefile

··· 37 37 i2c-designware-platform-objs := i2c-designware-platdrv.o i2c-designware-core.o 38 38 obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o 39 39 i2c-designware-pci-objs := i2c-designware-pcidrv.o i2c-designware-core.o 40 + obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o 40 41 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o 41 42 obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o 42 43 obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o ··· 64 63 obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o 65 64 obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o 66 65 obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o 66 + obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o 67 67 obj-$(CONFIG_I2C_STU300) += i2c-stu300.o 68 68 obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o 69 69 obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o 70 70 obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o 71 71 obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o 72 - obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o 72 + obj-$(CONFIG_I2C_XLR) += i2c-xlr.o 73 73 74 74 # External I2C/SMBus adapter drivers 75 75 obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o

+1 -1

drivers/i2c/busses/i2c-designware-platdrv.c

··· 214 214 { 215 215 return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); 216 216 } 217 - module_init(dw_i2c_init_driver); 217 + subsys_initcall(dw_i2c_init_driver); 218 218 219 219 static void __exit dw_i2c_exit_driver(void) 220 220 {

+21 -23

drivers/i2c/busses/i2c-eg20t.c

··· 271 271 /** 272 272 * pch_i2c_wait_for_bus_idle() - check the status of bus. 273 273 * @adap: Pointer to struct i2c_algo_pch_data. 274 - * @timeout: waiting time counter (us). 274 + * @timeout: waiting time counter (ms). 275 275 */ 276 276 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap, 277 277 s32 timeout) 278 278 { 279 279 void __iomem *p = adap->pch_base_address; 280 - ktime_t ns_val; 280 + int schedule = 0; 281 + unsigned long end = jiffies + msecs_to_jiffies(timeout); 281 282 282 - if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0) 283 - return 0; 283 + while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) { 284 + if (time_after(jiffies, end)) { 285 + pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR)); 286 + pch_err(adap, "%s: Timeout Error.return%d\n", 287 + __func__, -ETIME); 288 + pch_i2c_init(adap); 284 289 285 - /* MAX timeout value is timeout*1000*1000nsec */ 286 - ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000); 287 - do { 288 - msleep(20); 289 - if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0) 290 - return 0; 291 - } while (ktime_lt(ktime_get(), ns_val)); 290 + return -ETIME; 291 + } 292 292 293 - pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR)); 294 - pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME); 295 - pch_i2c_init(adap); 293 + if (!schedule) 294 + /* Retry after some usecs */ 295 + udelay(5); 296 + else 297 + /* Wait a bit more without consuming CPU */ 298 + usleep_range(20, 1000); 296 299 297 - return -ETIME; 300 + schedule = 1; 301 + } 302 + 303 + return 0; 298 304 } 299 305 300 306 /** ··· 784 778 struct i2c_msg *pmsg; 785 779 u32 i = 0; 786 780 u32 status; 787 - u32 msglen; 788 - u32 subaddrlen; 789 781 s32 ret; 790 782 791 783 struct i2c_algo_pch_data *adap = i2c_adap->algo_data; ··· 808 804 status = pmsg->flags; 809 805 pch_dbg(adap, 810 806 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status); 811 - /* calculate sub address length and message length */ 812 - /* these are applicable only for buffer mode */ 813 - subaddrlen = pmsg->buf[0]; 814 - /* calculate actual message length excluding 815 - * the sub address fields */ 816 - msglen = (pmsg->len) - (subaddrlen + 1); 817 807 818 808 if ((status & (I2C_M_RD)) != false) { 819 809 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),

-5

drivers/i2c/busses/i2c-imx.c

··· 149 149 break; 150 150 if (!for_busy && !(temp & I2SR_IBB)) 151 151 break; 152 - if (signal_pending(current)) { 153 - dev_dbg(&i2c_imx->adapter.dev, 154 - "<%s> I2C Interrupted\n", __func__); 155 - return -EINTR; 156 - } 157 152 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 158 153 dev_dbg(&i2c_imx->adapter.dev, 159 154 "<%s> I2C bus is busy\n", __func__);

+49 -14

drivers/i2c/busses/i2c-mpc.c

··· 454 454 } 455 455 456 456 static int mpc_read(struct mpc_i2c *i2c, int target, 457 - u8 *data, int length, int restart) 457 + u8 *data, int length, int restart, bool recv_len) 458 458 { 459 459 unsigned timeout = i2c->adap.timeout; 460 460 int i, result; ··· 470 470 return result; 471 471 472 472 if (length) { 473 - if (length == 1) 473 + if (length == 1 && !recv_len) 474 474 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK); 475 475 else 476 476 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA); ··· 479 479 } 480 480 481 481 for (i = 0; i < length; i++) { 482 + u8 byte; 483 + 482 484 result = i2c_wait(i2c, timeout, 0); 483 485 if (result < 0) 484 486 return result; 485 487 486 - /* Generate txack on next to last byte */ 487 - if (i == length - 2) 488 - writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK); 489 - /* Do not generate stop on last byte */ 490 - if (i == length - 1) 491 - writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX); 492 - data[i] = readb(i2c->base + MPC_I2C_DR); 488 + /* 489 + * For block reads, we have to know the total length (1st byte) 490 + * before we can determine if we are done. 491 + */ 492 + if (i || !recv_len) { 493 + /* Generate txack on next to last byte */ 494 + if (i == length - 2) 495 + writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 496 + | CCR_TXAK); 497 + /* Do not generate stop on last byte */ 498 + if (i == length - 1) 499 + writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 500 + | CCR_MTX); 501 + } 502 + 503 + byte = readb(i2c->base + MPC_I2C_DR); 504 + 505 + /* 506 + * Adjust length if first received byte is length. 507 + * The length is 1 length byte plus actually data length 508 + */ 509 + if (i == 0 && recv_len) { 510 + if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) 511 + return -EPROTO; 512 + length += byte; 513 + /* 514 + * For block reads, generate txack here if data length 515 + * is 1 byte (total length is 2 bytes). 516 + */ 517 + if (length == 2) 518 + writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 519 + | CCR_TXAK); 520 + } 521 + data[i] = byte; 493 522 } 494 523 495 524 return length; ··· 561 532 "Doing %s %d bytes to 0x%02x - %d of %d messages\n", 562 533 pmsg->flags & I2C_M_RD ? "read" : "write", 563 534 pmsg->len, pmsg->addr, i + 1, num); 564 - if (pmsg->flags & I2C_M_RD) 565 - ret = 566 - mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i); 567 - else 535 + if (pmsg->flags & I2C_M_RD) { 536 + bool recv_len = pmsg->flags & I2C_M_RECV_LEN; 537 + 538 + ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i, 539 + recv_len); 540 + if (recv_len && ret > 0) 541 + pmsg->len = ret; 542 + } else { 568 543 ret = 569 544 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i); 545 + } 570 546 } 571 547 mpc_i2c_stop(i2c); 572 548 return (ret < 0) ? ret : num; ··· 579 545 580 546 static u32 mpc_functionality(struct i2c_adapter *adap) 581 547 { 582 - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 548 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 549 + | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL; 583 550 } 584 551 585 552 static const struct i2c_algorithm mpc_algo = {

+11 -3

drivers/i2c/busses/i2c-s3c2410.c

··· 31 31 #include <linux/errno.h> 32 32 #include <linux/err.h> 33 33 #include <linux/platform_device.h> 34 + #include <linux/pm_runtime.h> 34 35 #include <linux/clk.h> 35 36 #include <linux/cpufreq.h> 36 37 #include <linux/slab.h> ··· 565 564 int retry; 566 565 int ret; 567 566 567 + pm_runtime_get_sync(&adap->dev); 568 568 clk_enable(i2c->clk); 569 569 570 570 for (retry = 0; retry < adap->retries; retry++) { ··· 574 572 575 573 if (ret != -EAGAIN) { 576 574 clk_disable(i2c->clk); 575 + pm_runtime_put_sync(&adap->dev); 577 576 return ret; 578 577 } 579 578 ··· 584 581 } 585 582 586 583 clk_disable(i2c->clk); 584 + pm_runtime_put_sync(&adap->dev); 587 585 return -EREMOTEIO; 588 586 } 589 587 ··· 894 890 } 895 891 } 896 892 897 - i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL); 893 + i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); 898 894 if (!i2c) { 899 895 dev_err(&pdev->dev, "no memory for state\n"); 900 896 return -ENOMEM; ··· 1017 1013 of_i2c_register_devices(&i2c->adap); 1018 1014 platform_set_drvdata(pdev, i2c); 1019 1015 1016 + pm_runtime_enable(&pdev->dev); 1017 + pm_runtime_enable(&i2c->adap.dev); 1018 + 1020 1019 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 1021 1020 clk_disable(i2c->clk); 1022 1021 return 0; ··· 1042 1035 clk_put(i2c->clk); 1043 1036 1044 1037 err_noclk: 1045 - kfree(i2c); 1046 1038 return ret; 1047 1039 } 1048 1040 ··· 1053 1047 static int s3c24xx_i2c_remove(struct platform_device *pdev) 1054 1048 { 1055 1049 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1050 + 1051 + pm_runtime_disable(&i2c->adap.dev); 1052 + pm_runtime_disable(&pdev->dev); 1056 1053 1057 1054 s3c24xx_i2c_deregister_cpufreq(i2c); 1058 1055 ··· 1070 1061 release_resource(i2c->ioarea); 1071 1062 s3c24xx_i2c_dt_gpio_free(i2c); 1072 1063 kfree(i2c->ioarea); 1073 - kfree(i2c); 1074 1064 1075 1065 return 0; 1076 1066 }

+459

drivers/i2c/busses/i2c-sirf.c

··· 1 + /* 2 + * I2C bus driver for CSR SiRFprimaII 3 + * 4 + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 5 + * 6 + * Licensed under GPLv2 or later. 7 + */ 8 + 9 + #include <linux/interrupt.h> 10 + #include <linux/kernel.h> 11 + #include <linux/module.h> 12 + #include <linux/slab.h> 13 + #include <linux/platform_device.h> 14 + #include <linux/i2c.h> 15 + #include <linux/clk.h> 16 + #include <linux/err.h> 17 + #include <linux/io.h> 18 + 19 + #define SIRFSOC_I2C_CLK_CTRL 0x00 20 + #define SIRFSOC_I2C_STATUS 0x0C 21 + #define SIRFSOC_I2C_CTRL 0x10 22 + #define SIRFSOC_I2C_IO_CTRL 0x14 23 + #define SIRFSOC_I2C_SDA_DELAY 0x18 24 + #define SIRFSOC_I2C_CMD_START 0x1C 25 + #define SIRFSOC_I2C_CMD_BUF 0x30 26 + #define SIRFSOC_I2C_DATA_BUF 0x80 27 + 28 + #define SIRFSOC_I2C_CMD_BUF_MAX 16 29 + #define SIRFSOC_I2C_DATA_BUF_MAX 16 30 + 31 + #define SIRFSOC_I2C_CMD(x) (SIRFSOC_I2C_CMD_BUF + (x)*0x04) 32 + #define SIRFSOC_I2C_DATA_MASK(x) (0xFF<<(((x)&3)*8)) 33 + #define SIRFSOC_I2C_DATA_SHIFT(x) (((x)&3)*8) 34 + 35 + #define SIRFSOC_I2C_DIV_MASK (0xFFFF) 36 + 37 + /* I2C status flags */ 38 + #define SIRFSOC_I2C_STAT_BUSY BIT(0) 39 + #define SIRFSOC_I2C_STAT_TIP BIT(1) 40 + #define SIRFSOC_I2C_STAT_NACK BIT(2) 41 + #define SIRFSOC_I2C_STAT_TR_INT BIT(4) 42 + #define SIRFSOC_I2C_STAT_STOP BIT(6) 43 + #define SIRFSOC_I2C_STAT_CMD_DONE BIT(8) 44 + #define SIRFSOC_I2C_STAT_ERR BIT(9) 45 + #define SIRFSOC_I2C_CMD_INDEX (0x1F<<16) 46 + 47 + /* I2C control flags */ 48 + #define SIRFSOC_I2C_RESET BIT(0) 49 + #define SIRFSOC_I2C_CORE_EN BIT(1) 50 + #define SIRFSOC_I2C_MASTER_MODE BIT(2) 51 + #define SIRFSOC_I2C_CMD_DONE_EN BIT(11) 52 + #define SIRFSOC_I2C_ERR_INT_EN BIT(12) 53 + 54 + #define SIRFSOC_I2C_SDA_DELAY_MASK (0xFF) 55 + #define SIRFSOC_I2C_SCLF_FILTER (3<<8) 56 + 57 + #define SIRFSOC_I2C_START_CMD BIT(0) 58 + 59 + #define SIRFSOC_I2C_CMD_RP(x) ((x)&0x7) 60 + #define SIRFSOC_I2C_NACK BIT(3) 61 + #define SIRFSOC_I2C_WRITE BIT(4) 62 + #define SIRFSOC_I2C_READ BIT(5) 63 + #define SIRFSOC_I2C_STOP BIT(6) 64 + #define SIRFSOC_I2C_START BIT(7) 65 + 66 + #define SIRFSOC_I2C_DEFAULT_SPEED 100000 67 + 68 + struct sirfsoc_i2c { 69 + void __iomem *base; 70 + struct clk *clk; 71 + u32 cmd_ptr; /* Current position in CMD buffer */ 72 + u8 *buf; /* Buffer passed by user */ 73 + u32 msg_len; /* Message length */ 74 + u32 finished_len; /* number of bytes read/written */ 75 + u32 read_cmd_len; /* number of read cmd sent */ 76 + int msg_read; /* 1 indicates a read message */ 77 + int err_status; /* 1 indicates an error on bus */ 78 + 79 + u32 sda_delay; /* For suspend/resume */ 80 + u32 clk_div; 81 + int last; /* Last message in transfer, STOP cmd can be sent */ 82 + 83 + struct completion done; /* indicates completion of message transfer */ 84 + struct i2c_adapter adapter; 85 + }; 86 + 87 + static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic) 88 + { 89 + u32 data = 0; 90 + int i; 91 + 92 + for (i = 0; i < siic->read_cmd_len; i++) { 93 + if (!(i & 0x3)) 94 + data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i); 95 + siic->buf[siic->finished_len++] = 96 + (u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >> 97 + SIRFSOC_I2C_DATA_SHIFT(i)); 98 + } 99 + } 100 + 101 + static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic) 102 + { 103 + u32 regval; 104 + int i = 0; 105 + 106 + if (siic->msg_read) { 107 + while (((siic->finished_len + i) < siic->msg_len) 108 + && (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) { 109 + regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0); 110 + if (((siic->finished_len + i) == 111 + (siic->msg_len - 1)) && siic->last) 112 + regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK; 113 + writel(regval, 114 + siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); 115 + i++; 116 + } 117 + 118 + siic->read_cmd_len = i; 119 + } else { 120 + while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1) 121 + && (siic->finished_len < siic->msg_len)) { 122 + regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0); 123 + if ((siic->finished_len == (siic->msg_len - 1)) 124 + && siic->last) 125 + regval |= SIRFSOC_I2C_STOP; 126 + writel(regval, 127 + siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); 128 + writel(siic->buf[siic->finished_len++], 129 + siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); 130 + } 131 + } 132 + siic->cmd_ptr = 0; 133 + 134 + /* Trigger the transfer */ 135 + writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START); 136 + } 137 + 138 + static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id) 139 + { 140 + struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id; 141 + u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS); 142 + 143 + if (i2c_stat & SIRFSOC_I2C_STAT_ERR) { 144 + /* Error conditions */ 145 + siic->err_status = 1; 146 + writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS); 147 + 148 + if (i2c_stat & SIRFSOC_I2C_STAT_NACK) 149 + dev_err(&siic->adapter.dev, "ACK not received\n"); 150 + else 151 + dev_err(&siic->adapter.dev, "I2C error\n"); 152 + 153 + complete(&siic->done); 154 + } else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) { 155 + /* CMD buffer execution complete */ 156 + if (siic->msg_read) 157 + i2c_sirfsoc_read_data(siic); 158 + if (siic->finished_len == siic->msg_len) 159 + complete(&siic->done); 160 + else /* Fill a new CMD buffer for left data */ 161 + i2c_sirfsoc_queue_cmd(siic); 162 + 163 + writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS); 164 + } 165 + 166 + return IRQ_HANDLED; 167 + } 168 + 169 + static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic, 170 + struct i2c_msg *msg) 171 + { 172 + unsigned char addr; 173 + u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE; 174 + 175 + /* no data and last message -> add STOP */ 176 + if (siic->last && (msg->len == 0)) 177 + regval |= SIRFSOC_I2C_STOP; 178 + 179 + writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); 180 + 181 + addr = msg->addr << 1; /* Generate address */ 182 + if (msg->flags & I2C_M_RD) 183 + addr |= 1; 184 + 185 + writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); 186 + } 187 + 188 + static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg) 189 + { 190 + u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL); 191 + /* timeout waiting for the xfer to finish or fail */ 192 + int timeout = msecs_to_jiffies((msg->len + 1) * 50); 193 + int ret = 0; 194 + 195 + i2c_sirfsoc_set_address(siic, msg); 196 + 197 + writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN, 198 + siic->base + SIRFSOC_I2C_CTRL); 199 + i2c_sirfsoc_queue_cmd(siic); 200 + 201 + if (wait_for_completion_timeout(&siic->done, timeout) == 0) { 202 + siic->err_status = 1; 203 + dev_err(&siic->adapter.dev, "Transfer timeout\n"); 204 + } 205 + 206 + writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN), 207 + siic->base + SIRFSOC_I2C_CTRL); 208 + writel(0, siic->base + SIRFSOC_I2C_CMD_START); 209 + 210 + if (siic->err_status) { 211 + writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, 212 + siic->base + SIRFSOC_I2C_CTRL); 213 + while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) 214 + cpu_relax(); 215 + 216 + ret = -EIO; 217 + } 218 + 219 + return ret; 220 + } 221 + 222 + static u32 i2c_sirfsoc_func(struct i2c_adapter *adap) 223 + { 224 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 225 + } 226 + 227 + static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 228 + int num) 229 + { 230 + struct sirfsoc_i2c *siic = adap->algo_data; 231 + int i, ret; 232 + 233 + clk_enable(siic->clk); 234 + 235 + for (i = 0; i < num; i++) { 236 + siic->buf = msgs[i].buf; 237 + siic->msg_len = msgs[i].len; 238 + siic->msg_read = !!(msgs[i].flags & I2C_M_RD); 239 + siic->err_status = 0; 240 + siic->cmd_ptr = 0; 241 + siic->finished_len = 0; 242 + siic->last = (i == (num - 1)); 243 + 244 + ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]); 245 + if (ret) { 246 + clk_disable(siic->clk); 247 + return ret; 248 + } 249 + } 250 + 251 + clk_disable(siic->clk); 252 + return num; 253 + } 254 + 255 + /* I2C algorithms associated with this master controller driver */ 256 + static const struct i2c_algorithm i2c_sirfsoc_algo = { 257 + .master_xfer = i2c_sirfsoc_xfer, 258 + .functionality = i2c_sirfsoc_func, 259 + }; 260 + 261 + static int __devinit i2c_sirfsoc_probe(struct platform_device *pdev) 262 + { 263 + struct sirfsoc_i2c *siic; 264 + struct i2c_adapter *adap; 265 + struct resource *mem_res; 266 + struct clk *clk; 267 + int bitrate; 268 + int ctrl_speed; 269 + int irq; 270 + 271 + int err; 272 + u32 regval; 273 + 274 + clk = clk_get(&pdev->dev, NULL); 275 + if (IS_ERR(clk)) { 276 + err = PTR_ERR(clk); 277 + dev_err(&pdev->dev, "Clock get failed\n"); 278 + goto err_get_clk; 279 + } 280 + 281 + err = clk_prepare(clk); 282 + if (err) { 283 + dev_err(&pdev->dev, "Clock prepare failed\n"); 284 + goto err_clk_prep; 285 + } 286 + 287 + err = clk_enable(clk); 288 + if (err) { 289 + dev_err(&pdev->dev, "Clock enable failed\n"); 290 + goto err_clk_en; 291 + } 292 + 293 + ctrl_speed = clk_get_rate(clk); 294 + 295 + siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL); 296 + if (!siic) { 297 + dev_err(&pdev->dev, "Can't allocate driver data\n"); 298 + err = -ENOMEM; 299 + goto out; 300 + } 301 + adap = &siic->adapter; 302 + adap->class = I2C_CLASS_HWMON; 303 + 304 + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 305 + if (mem_res == NULL) { 306 + dev_err(&pdev->dev, "Unable to get MEM resource\n"); 307 + err = -EINVAL; 308 + goto out; 309 + } 310 + 311 + siic->base = devm_request_and_ioremap(&pdev->dev, mem_res); 312 + if (siic->base == NULL) { 313 + dev_err(&pdev->dev, "IO remap failed!\n"); 314 + err = -ENOMEM; 315 + goto out; 316 + } 317 + 318 + irq = platform_get_irq(pdev, 0); 319 + if (irq < 0) { 320 + err = irq; 321 + goto out; 322 + } 323 + err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0, 324 + dev_name(&pdev->dev), siic); 325 + if (err) 326 + goto out; 327 + 328 + adap->algo = &i2c_sirfsoc_algo; 329 + adap->algo_data = siic; 330 + 331 + adap->dev.parent = &pdev->dev; 332 + adap->nr = pdev->id; 333 + 334 + strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name)); 335 + 336 + platform_set_drvdata(pdev, adap); 337 + init_completion(&siic->done); 338 + 339 + /* Controller Initalisation */ 340 + 341 + writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); 342 + while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) 343 + cpu_relax(); 344 + writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE, 345 + siic->base + SIRFSOC_I2C_CTRL); 346 + 347 + siic->clk = clk; 348 + 349 + err = of_property_read_u32(pdev->dev.of_node, 350 + "clock-frequency", &bitrate); 351 + if (err < 0) 352 + bitrate = SIRFSOC_I2C_DEFAULT_SPEED; 353 + 354 + if (bitrate < 100000) 355 + regval = 356 + (2 * ctrl_speed) / (2 * bitrate * 11); 357 + else 358 + regval = ctrl_speed / (bitrate * 5); 359 + 360 + writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL); 361 + if (regval > 0xFF) 362 + writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY); 363 + else 364 + writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY); 365 + 366 + err = i2c_add_numbered_adapter(adap); 367 + if (err < 0) { 368 + dev_err(&pdev->dev, "Can't add new i2c adapter\n"); 369 + goto out; 370 + } 371 + 372 + clk_disable(clk); 373 + 374 + dev_info(&pdev->dev, " I2C adapter ready to operate\n"); 375 + 376 + return 0; 377 + 378 + out: 379 + clk_disable(clk); 380 + err_clk_en: 381 + clk_unprepare(clk); 382 + err_clk_prep: 383 + clk_put(clk); 384 + err_get_clk: 385 + return err; 386 + } 387 + 388 + static int __devexit i2c_sirfsoc_remove(struct platform_device *pdev) 389 + { 390 + struct i2c_adapter *adapter = platform_get_drvdata(pdev); 391 + struct sirfsoc_i2c *siic = adapter->algo_data; 392 + 393 + writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); 394 + i2c_del_adapter(adapter); 395 + clk_unprepare(siic->clk); 396 + clk_put(siic->clk); 397 + return 0; 398 + } 399 + 400 + #ifdef CONFIG_PM 401 + static int i2c_sirfsoc_suspend(struct device *dev) 402 + { 403 + struct platform_device *pdev = to_platform_device(dev); 404 + struct i2c_adapter *adapter = platform_get_drvdata(pdev); 405 + struct sirfsoc_i2c *siic = adapter->algo_data; 406 + 407 + clk_enable(siic->clk); 408 + siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY); 409 + siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL); 410 + clk_disable(siic->clk); 411 + return 0; 412 + } 413 + 414 + static int i2c_sirfsoc_resume(struct device *dev) 415 + { 416 + struct platform_device *pdev = to_platform_device(dev); 417 + struct i2c_adapter *adapter = platform_get_drvdata(pdev); 418 + struct sirfsoc_i2c *siic = adapter->algo_data; 419 + 420 + clk_enable(siic->clk); 421 + writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); 422 + writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE, 423 + siic->base + SIRFSOC_I2C_CTRL); 424 + writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL); 425 + writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY); 426 + clk_disable(siic->clk); 427 + return 0; 428 + } 429 + 430 + static const struct dev_pm_ops i2c_sirfsoc_pm_ops = { 431 + .suspend = i2c_sirfsoc_suspend, 432 + .resume = i2c_sirfsoc_resume, 433 + }; 434 + #endif 435 + 436 + static const struct of_device_id sirfsoc_i2c_of_match[] __devinitconst = { 437 + { .compatible = "sirf,prima2-i2c", }, 438 + {}, 439 + }; 440 + MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match); 441 + 442 + static struct platform_driver i2c_sirfsoc_driver = { 443 + .driver = { 444 + .name = "sirfsoc_i2c", 445 + .owner = THIS_MODULE, 446 + #ifdef CONFIG_PM 447 + .pm = &i2c_sirfsoc_pm_ops, 448 + #endif 449 + .of_match_table = sirfsoc_i2c_of_match, 450 + }, 451 + .probe = i2c_sirfsoc_probe, 452 + .remove = __devexit_p(i2c_sirfsoc_remove), 453 + }; 454 + module_platform_driver(i2c_sirfsoc_driver); 455 + 456 + MODULE_DESCRIPTION("SiRF SoC I2C master controller driver"); 457 + MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, " 458 + "Xiangzhen Ye <Xiangzhen.Ye@csr.com>"); 459 + MODULE_LICENSE("GPL v2");

-1

drivers/i2c/busses/i2c-tegra.c

··· 457 457 int ret; 458 458 459 459 tegra_i2c_flush_fifos(i2c_dev); 460 - i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS); 461 460 462 461 if (msg->len == 0) 463 462 return -EINVAL;

+10

drivers/i2c/busses/i2c-versatile.c

··· 16 16 #include <linux/platform_device.h> 17 17 #include <linux/slab.h> 18 18 #include <linux/io.h> 19 + #include <linux/of_i2c.h> 19 20 20 21 #define I2C_CONTROL 0x00 21 22 #define I2C_CONTROLS 0x00 ··· 100 99 strlcpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name)); 101 100 i2c->adap.algo_data = &i2c->algo; 102 101 i2c->adap.dev.parent = &dev->dev; 102 + i2c->adap.dev.of_node = dev->dev.of_node; 103 103 i2c->algo = i2c_versatile_algo; 104 104 i2c->algo.data = i2c; 105 105 ··· 113 111 ret = i2c_bit_add_bus(&i2c->adap); 114 112 if (ret >= 0) { 115 113 platform_set_drvdata(dev, i2c); 114 + of_i2c_register_devices(&i2c->adap); 116 115 return 0; 117 116 } 118 117 ··· 136 133 return 0; 137 134 } 138 135 136 + static const struct of_device_id i2c_versatile_match[] = { 137 + { .compatible = "arm,versatile-i2c", }, 138 + {}, 139 + }; 140 + MODULE_DEVICE_TABLE(of, i2c_versatile_match); 141 + 139 142 static struct platform_driver i2c_versatile_driver = { 140 143 .probe = i2c_versatile_probe, 141 144 .remove = i2c_versatile_remove, 142 145 .driver = { 143 146 .name = "versatile-i2c", 144 147 .owner = THIS_MODULE, 148 + .of_match_table = i2c_versatile_match, 145 149 }, 146 150 }; 147 151

+278

drivers/i2c/busses/i2c-xlr.c

··· 1 + /* 2 + * Copyright 2011, Netlogic Microsystems Inc. 3 + * Copyright 2004, Matt Porter <mporter@kernel.crashing.org> 4 + * 5 + * This file is licensed under the terms of the GNU General Public 6 + * License version 2. This program is licensed "as is" without any 7 + * warranty of any kind, whether express or implied. 8 + */ 9 + 10 + #include <linux/kernel.h> 11 + #include <linux/module.h> 12 + #include <linux/slab.h> 13 + #include <linux/init.h> 14 + #include <linux/ioport.h> 15 + #include <linux/delay.h> 16 + #include <linux/errno.h> 17 + #include <linux/i2c.h> 18 + #include <linux/io.h> 19 + #include <linux/platform_device.h> 20 + 21 + /* XLR I2C REGISTERS */ 22 + #define XLR_I2C_CFG 0x00 23 + #define XLR_I2C_CLKDIV 0x01 24 + #define XLR_I2C_DEVADDR 0x02 25 + #define XLR_I2C_ADDR 0x03 26 + #define XLR_I2C_DATAOUT 0x04 27 + #define XLR_I2C_DATAIN 0x05 28 + #define XLR_I2C_STATUS 0x06 29 + #define XLR_I2C_STARTXFR 0x07 30 + #define XLR_I2C_BYTECNT 0x08 31 + #define XLR_I2C_HDSTATIM 0x09 32 + 33 + /* XLR I2C REGISTERS FLAGS */ 34 + #define XLR_I2C_BUS_BUSY 0x01 35 + #define XLR_I2C_SDOEMPTY 0x02 36 + #define XLR_I2C_RXRDY 0x04 37 + #define XLR_I2C_ACK_ERR 0x08 38 + #define XLR_I2C_ARB_STARTERR 0x30 39 + 40 + /* Register Values */ 41 + #define XLR_I2C_CFG_ADDR 0xF8 42 + #define XLR_I2C_CFG_NOADDR 0xFA 43 + #define XLR_I2C_STARTXFR_ND 0x02 /* No Data */ 44 + #define XLR_I2C_STARTXFR_RD 0x01 /* Read */ 45 + #define XLR_I2C_STARTXFR_WR 0x00 /* Write */ 46 + 47 + #define XLR_I2C_TIMEOUT 10 /* timeout per byte in msec */ 48 + 49 + /* 50 + * On XLR/XLS, we need to use __raw_ IO to read the I2C registers 51 + * because they are in the big-endian MMIO area on the SoC. 52 + * 53 + * The readl/writel implementation on XLR/XLS byteswaps, because 54 + * those are for its little-endian PCI space (see arch/mips/Kconfig). 55 + */ 56 + static inline void xlr_i2c_wreg(u32 __iomem *base, unsigned int reg, u32 val) 57 + { 58 + __raw_writel(val, base + reg); 59 + } 60 + 61 + static inline u32 xlr_i2c_rdreg(u32 __iomem *base, unsigned int reg) 62 + { 63 + return __raw_readl(base + reg); 64 + } 65 + 66 + struct xlr_i2c_private { 67 + struct i2c_adapter adap; 68 + u32 __iomem *iobase; 69 + }; 70 + 71 + static int xlr_i2c_tx(struct xlr_i2c_private *priv, u16 len, 72 + u8 *buf, u16 addr) 73 + { 74 + struct i2c_adapter *adap = &priv->adap; 75 + unsigned long timeout, stoptime, checktime; 76 + u32 i2c_status; 77 + int pos, timedout; 78 + u8 offset, byte; 79 + 80 + offset = buf[0]; 81 + xlr_i2c_wreg(priv->iobase, XLR_I2C_ADDR, offset); 82 + xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr); 83 + xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG, XLR_I2C_CFG_ADDR); 84 + xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1); 85 + 86 + timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT); 87 + stoptime = jiffies + timeout; 88 + timedout = 0; 89 + pos = 1; 90 + retry: 91 + if (len == 1) { 92 + xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, 93 + XLR_I2C_STARTXFR_ND); 94 + } else { 95 + xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[pos]); 96 + xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, 97 + XLR_I2C_STARTXFR_WR); 98 + } 99 + 100 + while (!timedout) { 101 + checktime = jiffies; 102 + i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS); 103 + 104 + if (i2c_status & XLR_I2C_SDOEMPTY) { 105 + pos++; 106 + /* need to do a empty dataout after the last byte */ 107 + byte = (pos < len) ? buf[pos] : 0; 108 + xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, byte); 109 + 110 + /* reset timeout on successful xmit */ 111 + stoptime = jiffies + timeout; 112 + } 113 + timedout = time_after(checktime, stoptime); 114 + 115 + if (i2c_status & XLR_I2C_ARB_STARTERR) { 116 + if (timedout) 117 + break; 118 + goto retry; 119 + } 120 + 121 + if (i2c_status & XLR_I2C_ACK_ERR) 122 + return -EIO; 123 + 124 + if ((i2c_status & XLR_I2C_BUS_BUSY) == 0 && pos >= len) 125 + return 0; 126 + } 127 + dev_err(&adap->dev, "I2C transmit timeout\n"); 128 + return -ETIMEDOUT; 129 + } 130 + 131 + static int xlr_i2c_rx(struct xlr_i2c_private *priv, u16 len, u8 *buf, u16 addr) 132 + { 133 + struct i2c_adapter *adap = &priv->adap; 134 + u32 i2c_status; 135 + unsigned long timeout, stoptime, checktime; 136 + int nbytes, timedout; 137 + u8 byte; 138 + 139 + xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG, XLR_I2C_CFG_NOADDR); 140 + xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len); 141 + xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr); 142 + 143 + timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT); 144 + stoptime = jiffies + timeout; 145 + timedout = 0; 146 + nbytes = 0; 147 + retry: 148 + xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_RD); 149 + 150 + while (!timedout) { 151 + checktime = jiffies; 152 + i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS); 153 + if (i2c_status & XLR_I2C_RXRDY) { 154 + if (nbytes > len) 155 + return -EIO; /* should not happen */ 156 + 157 + /* we need to do a dummy datain when nbytes == len */ 158 + byte = xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN); 159 + if (nbytes < len) 160 + buf[nbytes] = byte; 161 + nbytes++; 162 + 163 + /* reset timeout on successful read */ 164 + stoptime = jiffies + timeout; 165 + } 166 + 167 + timedout = time_after(checktime, stoptime); 168 + if (i2c_status & XLR_I2C_ARB_STARTERR) { 169 + if (timedout) 170 + break; 171 + goto retry; 172 + } 173 + 174 + if (i2c_status & XLR_I2C_ACK_ERR) 175 + return -EIO; 176 + 177 + if ((i2c_status & XLR_I2C_BUS_BUSY) == 0) 178 + return 0; 179 + } 180 + 181 + dev_err(&adap->dev, "I2C receive timeout\n"); 182 + return -ETIMEDOUT; 183 + } 184 + 185 + static int xlr_i2c_xfer(struct i2c_adapter *adap, 186 + struct i2c_msg *msgs, int num) 187 + { 188 + struct i2c_msg *msg; 189 + int i; 190 + int ret = 0; 191 + struct xlr_i2c_private *priv = i2c_get_adapdata(adap); 192 + 193 + for (i = 0; ret == 0 && i < num; i++) { 194 + msg = &msgs[i]; 195 + if (msg->flags & I2C_M_RD) 196 + ret = xlr_i2c_rx(priv, msg->len, &msg->buf[0], 197 + msg->addr); 198 + else 199 + ret = xlr_i2c_tx(priv, msg->len, &msg->buf[0], 200 + msg->addr); 201 + } 202 + 203 + return (ret != 0) ? ret : num; 204 + } 205 + 206 + static u32 xlr_func(struct i2c_adapter *adap) 207 + { 208 + /* Emulate SMBUS over I2C */ 209 + return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C; 210 + } 211 + 212 + static struct i2c_algorithm xlr_i2c_algo = { 213 + .master_xfer = xlr_i2c_xfer, 214 + .functionality = xlr_func, 215 + }; 216 + 217 + static int __devinit xlr_i2c_probe(struct platform_device *pdev) 218 + { 219 + struct xlr_i2c_private *priv; 220 + struct resource *res; 221 + int ret; 222 + 223 + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 224 + if (!priv) 225 + return -ENOMEM; 226 + 227 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 228 + priv->iobase = devm_request_and_ioremap(&pdev->dev, res); 229 + if (!priv->iobase) { 230 + dev_err(&pdev->dev, "devm_request_and_ioremap failed\n"); 231 + return -EBUSY; 232 + } 233 + 234 + priv->adap.dev.parent = &pdev->dev; 235 + priv->adap.owner = THIS_MODULE; 236 + priv->adap.algo_data = priv; 237 + priv->adap.algo = &xlr_i2c_algo; 238 + priv->adap.nr = pdev->id; 239 + priv->adap.class = I2C_CLASS_HWMON; 240 + snprintf(priv->adap.name, sizeof(priv->adap.name), "xlr-i2c"); 241 + 242 + i2c_set_adapdata(&priv->adap, priv); 243 + ret = i2c_add_numbered_adapter(&priv->adap); 244 + if (ret < 0) { 245 + dev_err(&priv->adap.dev, "Failed to add i2c bus.\n"); 246 + return ret; 247 + } 248 + 249 + platform_set_drvdata(pdev, priv); 250 + dev_info(&priv->adap.dev, "Added I2C Bus.\n"); 251 + return 0; 252 + } 253 + 254 + static int __devexit xlr_i2c_remove(struct platform_device *pdev) 255 + { 256 + struct xlr_i2c_private *priv; 257 + 258 + priv = platform_get_drvdata(pdev); 259 + i2c_del_adapter(&priv->adap); 260 + platform_set_drvdata(pdev, NULL); 261 + return 0; 262 + } 263 + 264 + static struct platform_driver xlr_i2c_driver = { 265 + .probe = xlr_i2c_probe, 266 + .remove = __devexit_p(xlr_i2c_remove), 267 + .driver = { 268 + .name = "xlr-i2cbus", 269 + .owner = THIS_MODULE, 270 + }, 271 + }; 272 + 273 + module_platform_driver(xlr_i2c_driver); 274 + 275 + MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@netlogicmicro.com>"); 276 + MODULE_DESCRIPTION("XLR/XLS SoC I2C Controller driver"); 277 + MODULE_LICENSE("GPL v2"); 278 + MODULE_ALIAS("platform:xlr-i2cbus");

+29 -6

include/linux/i2c/at24.h

··· 1 + /* 2 + * at24.h - platform_data for the at24 (generic eeprom) driver 3 + * (C) Copyright 2008 by Pengutronix 4 + * (C) Copyright 2012 by Wolfram Sang 5 + * same license as the driver 6 + */ 7 + 1 8 #ifndef _LINUX_AT24_H 2 9 #define _LINUX_AT24_H 3 10 4 11 #include <linux/types.h> 5 12 #include <linux/memory.h> 6 13 7 - /* 8 - * As seen through Linux I2C, differences between the most common types of I2C 9 - * memory include: 10 - * - How much memory is available (usually specified in bit)? 11 - * - What write page size does it support? 12 - * - Special flags (16 bit addresses, read_only, world readable...)? 14 + /** 15 + * struct at24_platform_data - data to set up at24 (generic eeprom) driver 16 + * @byte_len: size of eeprom in byte 17 + * @page_size: number of byte which can be written in one go 18 + * @flags: tunable options, check AT24_FLAG_* defines 19 + * @setup: an optional callback invoked after eeprom is probed; enables kernel 20 + code to access eeprom via memory_accessor, see example 21 + * @context: optional parameter passed to setup() 13 22 * 14 23 * If you set up a custom eeprom type, please double-check the parameters. 15 24 * Especially page_size needs extra care, as you risk data loss if your value 16 25 * is bigger than what the chip actually supports! 26 + * 27 + * An example in pseudo code for a setup() callback: 28 + * 29 + * void get_mac_addr(struct memory_accessor *mem_acc, void *context) 30 + * { 31 + * u8 *mac_addr = ethernet_pdata->mac_addr; 32 + * off_t offset = context; 33 + * 34 + * // Read MAC addr from EEPROM 35 + * if (mem_acc->read(mem_acc, mac_addr, offset, ETH_ALEN) == ETH_ALEN) 36 + * pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr); 37 + * } 38 + * 39 + * This function pointer and context can now be set up in at24_platform_data. 17 40 */ 18 41 19 42 struct at24_platform_data {