tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: qcom-qmp: split PCS_UFS V3 symbols to separate header

Several registers defined in the PCS V3 namespace in reality belong to
the PCS_UFS V3 register space. Move them to the separate header and
rename them to explicitly mention PCS_UFS. While we are at it, correct
one register in the msm8998_usb3_pcs_tbl table to use PCS register name.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-21-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul fc270d13 25ad4a4c

+28 -17
+18
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_ 7 + #define QCOM_PHY_QMP_PCS_UFS_V3_H_ 8 + 9 + #define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c 10 + #define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034 11 + #define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134 12 + #define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138 13 + #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c 14 + #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140 15 + #define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc 16 + #define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4 17 + 18 + #endif
-8
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
··· 14 14 #define QPHY_V3_PCS_TXMGN_V3 0x018 15 15 #define QPHY_V3_PCS_TXMGN_V4 0x01c 16 16 #define QPHY_V3_PCS_TXMGN_LS 0x020 17 - #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 18 - #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 19 17 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 20 18 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 21 19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c ··· 51 53 #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 52 54 #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 53 55 #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 54 - #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 55 - #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 56 - #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 57 - #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 58 56 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 59 57 #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 60 58 #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 61 - #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 62 - #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 63 59 #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 64 60 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 65 61 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+8 -8
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
··· 389 389 }; 390 390 391 391 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { 392 - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), 393 - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), 394 - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), 395 - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), 396 - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), 397 - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), 398 - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), 399 - QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), 392 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), 393 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 394 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 395 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 396 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 397 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), 398 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), 399 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 400 400 }; 401 401 402 402 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
+1 -1
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
··· 634 634 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 635 635 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 636 636 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 637 - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), 637 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 638 638 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 639 639 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 640 640 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
+1
drivers/phy/qualcomm/phy-qcom-qmp.h
··· 26 26 27 27 #include "phy-qcom-qmp-pcs-v3.h" 28 28 #include "phy-qcom-qmp-pcs-misc-v3.h" 29 + #include "phy-qcom-qmp-pcs-ufs-v3.h" 29 30 30 31 #include "phy-qcom-qmp-pcs-v4.h" 31 32 #include "phy-qcom-qmp-pcs-pcie-v4.h"