pinctrl: sunxi: Add I/O bias setting for H6 R-PIO

H6 requires I/O bias configuration on both of its PIO devices.
Previously it was only done for the main PIO.

The setting for Port L is at bit 0, so the bank calculation needs to
account for the pin base. Otherwise the wrong bit is used.

Fixes: cc62383fcebe ("pinctrl: sunxi: Support I/O bias voltage setting on H6")
Reviewed-by: Jernej Skrabec <[e-mail]>
Tested-by: Heiko Stuebner <[e-mail]>
Signed-off-by: Samuel Holland <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Linus Walleij <[e-mail]>

drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c

···
 	.npins = ARRAY_SIZE(sun50i_h6_r_pins),
 	.pin_base = PL_BASE,
 	.irq_banks = 2,
+	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
 };
 
 static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev)

drivers/pinctrl/sunxi/pinctrl-sunxi.c

···
 					 unsigned pin,
 					 struct regulator *supply)
 {
-	unsigned short bank = pin / PINS_PER_BANK;
+	unsigned short bank;
 	unsigned long flags;
 	u32 val, reg;
 	int uV;
···
 	/* Might be dummy regulator with no voltage set */
 	if (uV == 0)
 		return 0;
+
+	pin -= pctl->desc->pin_base;
+	bank = pin / PINS_PER_BANK;
 
 	switch (pctl->desc->io_bias_cfg_variant) {
 	case BIAS_VOLTAGE_GRP_CONFIG:
···
 			val = 0xA; /* 3.0V */
 		else
 			val = 0xD; /* 3.3V */
-
-		pin -= pctl->desc->pin_base;
 
 		reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
 		reg &= ~IO_BIAS_MASK;