Merge tag 'samsung-pinctrl-5.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

+52

Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank 8 + 9 + maintainers: 10 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 11 + - Sylwester Nawrocki <s.nawrocki@samsung.com> 12 + - Tomasz Figa <tomasz.figa@gmail.com> 13 + 14 + description: | 15 + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin 16 + controller. 17 + 18 + GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller. 19 + 20 + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for 21 + additional information and example. 22 + 23 + properties: 24 + '#gpio-cells': 25 + const: 2 26 + 27 + gpio-controller: true 28 + 29 + '#interrupt-cells': 30 + description: 31 + For GPIO banks supporting external GPIO interrupts or external wake-up 32 + interrupts. 33 + const: 2 34 + 35 + interrupt-controller: 36 + description: 37 + For GPIO banks supporting external GPIO interrupts or external wake-up 38 + interrupts. 39 + 40 + interrupts: 41 + description: 42 + For GPIO banks supporting direct external wake-up interrupts (without 43 + multiplexing). Number of interrupts must match number of wake-up capable 44 + pins of this bank. 45 + minItems: 1 46 + maxItems: 8 47 + 48 + required: 49 + - '#gpio-cells' 50 + - gpio-controller 51 + 52 + additionalProperties: false

+81

Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration 8 + 9 + maintainers: 10 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 11 + - Sylwester Nawrocki <s.nawrocki@samsung.com> 12 + - Tomasz Figa <tomasz.figa@gmail.com> 13 + 14 + description: | 15 + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin 16 + controller. 17 + 18 + Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller. 19 + 20 + The values used for config properties should be derived from the hardware 21 + manual and these values are programmed as-is into the pin pull up/down and 22 + driver strength register of the pin-controller. 23 + See also include/dt-bindings/pinctrl/samsung.h with useful constants. 24 + 25 + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for 26 + additional information and example. 27 + 28 + properties: 29 + samsung,pins: 30 + description: | 31 + List of pins to configure. For initial and sleep states, the maximum 32 + number is one pin. In other cases there is no upper limit. 33 + 34 + The pins should use lowercase names matching hardware manual, e.g. for 35 + GPA0 bank: gpa0-0, gpa0-1, gpa0-2. 36 + $ref: /schemas/types.yaml#/definitions/string-array 37 + 38 + samsung,pin-function: 39 + description: | 40 + The pin function selection that should be applied on the pins listed in the 41 + child node is specified using the "samsung,pin-function" property. The value 42 + of this property that should be applied to each of the pins listed in the 43 + "samsung,pins" property should be picked from the hardware manual of the SoC 44 + for the specified pin group. This property is optional in the child node if 45 + no specific function selection is desired for the pins listed in the child 46 + node. The value of this property is used as-is to program the pin-controller 47 + function selector register of the pin-bank. 48 + $ref: /schemas/types.yaml#/definitions/uint32 49 + minimum: 0 50 + maximum: 15 51 + 52 + samsung,pin-drv: 53 + description: Drive strength configuration. 54 + $ref: /schemas/types.yaml#/definitions/uint32 55 + minimum: 0 56 + maximum: 15 57 + 58 + samsung,pin-pud: 59 + description: Pull up/down configuration. 60 + $ref: /schemas/types.yaml#/definitions/uint32 61 + enum: [0, 1, 2, 3] 62 + 63 + samsung,pin-val: 64 + description: Initial value of pin output buffer. 65 + $ref: /schemas/types.yaml#/definitions/uint32 66 + enum: [0, 1] 67 + 68 + samsung,pin-con-pdn: 69 + description: Function in power down mode. 70 + $ref: /schemas/types.yaml#/definitions/uint32 71 + enum: [0, 1, 2, 3] 72 + 73 + samsung,pin-pud-pdn: 74 + description: Pull up/down configuration in power down mode. 75 + $ref: /schemas/types.yaml#/definitions/uint32 76 + enum: [0, 1, 2, 3] 77 + 78 + required: 79 + - samsung,pins 80 + 81 + additionalProperties: false

+106

Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung S3C/S5P/Exynos SoC pin controller - wake-up interrupt controller 8 + 9 + maintainers: 10 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 11 + - Sylwester Nawrocki <s.nawrocki@samsung.com> 12 + - Tomasz Figa <tomasz.figa@gmail.com> 13 + 14 + description: | 15 + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin 16 + controller. 17 + 18 + External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller. 19 + For S3C24xx, S3C64xx, S5PV210 and Exynos4210 compatible wake-up interrupt 20 + controllers, only one pin-controller device node can include external wake-up 21 + interrupts child node (in other words, only one External wake-up interrupts 22 + pin-controller is supported). 23 + For newer controllers, multiple pin-controller device node can include 24 + external wake-up interrupts child node. 25 + 26 + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for 27 + additional information and example. 28 + 29 + properties: 30 + compatible: 31 + enum: 32 + - samsung,s3c2410-wakeup-eint 33 + - samsung,s3c2412-wakeup-eint 34 + - samsung,s3c64xx-wakeup-eint 35 + - samsung,s5pv210-wakeup-eint 36 + - samsung,exynos4210-wakeup-eint 37 + - samsung,exynos7-wakeup-eint 38 + - samsung,exynos850-wakeup-eint 39 + - samsung,exynosautov9-wakeup-eint 40 + 41 + interrupts: 42 + description: 43 + Interrupt used by multiplexed external wake-up interrupts. 44 + minItems: 1 45 + maxItems: 6 46 + 47 + required: 48 + - compatible 49 + 50 + allOf: 51 + - if: 52 + properties: 53 + compatible: 54 + contains: 55 + enum: 56 + - samsung,s3c2410-wakeup-eint 57 + - samsung,s3c2412-wakeup-eint 58 + then: 59 + properties: 60 + interrupts: 61 + minItems: 6 62 + maxItems: 6 63 + required: 64 + - interrupts 65 + 66 + - if: 67 + properties: 68 + compatible: 69 + contains: 70 + const: samsung,s3c64xx-wakeup-eint 71 + then: 72 + properties: 73 + interrupts: 74 + minItems: 4 75 + maxItems: 4 76 + required: 77 + - interrupts 78 + 79 + - if: 80 + properties: 81 + compatible: 82 + contains: 83 + enum: 84 + - samsung,s5pv210-wakeup-eint 85 + - samsung,exynos4210-wakeup-eint 86 + - samsung,exynos7-wakeup-eint 87 + then: 88 + properties: 89 + interrupts: 90 + minItems: 1 91 + maxItems: 1 92 + required: 93 + - interrupts 94 + 95 + - if: 96 + properties: 97 + compatible: 98 + contains: 99 + enum: 100 + - samsung,exynos850-wakeup-eint 101 + - samsung,exynosautov9-wakeup-eint 102 + then: 103 + properties: 104 + interrupts: false 105 + 106 + additionalProperties: false

+393

Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung S3C/S5P/Exynos SoC pin controller 8 + 9 + maintainers: 10 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 11 + - Sylwester Nawrocki <s.nawrocki@samsung.com> 12 + - Tomasz Figa <tomasz.figa@gmail.com> 13 + 14 + description: | 15 + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin 16 + controller. 17 + 18 + Pin group settings (like drive strength, pull up/down) are available as 19 + macros in include/dt-bindings/pinctrl/samsung.h. 20 + 21 + All the pin controller nodes should be represented in the aliases node using 22 + the following format 'pinctrl{n}' where n is a unique number for the alias. 23 + 24 + The controller supports three types of interrupts:: 25 + - External GPIO interrupts (see interrupts property in pin controller node); 26 + 27 + - External wake-up interrupts - multiplexed (capable of waking up the system 28 + see interrupts property in external wake-up interrupt controller node - 29 + samsung,pinctrl-wakeup-interrupt.yaml); 30 + 31 + - External wake-up interrupts - direct (capable of waking up the system, see 32 + interrupts property in every bank of pin controller with external wake-up 33 + interrupt controller - samsung,pinctrl-gpio-bank.yaml). 34 + 35 + properties: 36 + $nodename: 37 + pattern: "^pinctrl(@.*)?" 38 + 39 + compatible: 40 + enum: 41 + - samsung,s3c2412-pinctrl 42 + - samsung,s3c2416-pinctrl 43 + - samsung,s3c2440-pinctrl 44 + - samsung,s3c2450-pinctrl 45 + - samsung,s3c64xx-pinctrl 46 + - samsung,s5pv210-pinctrl 47 + - samsung,exynos3250-pinctrl 48 + - samsung,exynos4210-pinctrl 49 + - samsung,exynos4x12-pinctrl 50 + - samsung,exynos5250-pinctrl 51 + - samsung,exynos5260-pinctrl 52 + - samsung,exynos5410-pinctrl 53 + - samsung,exynos5420-pinctrl 54 + - samsung,exynos5433-pinctrl 55 + - samsung,exynos7-pinctrl 56 + - samsung,exynos7885-pinctrl 57 + - samsung,exynos850-pinctrl 58 + - samsung,exynosautov9-pinctrl 59 + - tesla,fsd-pinctrl 60 + 61 + interrupts: 62 + description: 63 + Required for GPIO banks supporting external GPIO interrupts. 64 + maxItems: 1 65 + 66 + power-domains: 67 + maxItems: 1 68 + 69 + reg: 70 + description: 71 + Second base address of the pin controller if the specific registers of 72 + the pin controller are separated into the different base address. 73 + Only certain banks of certain pin controller might need it. 74 + minItems: 1 75 + maxItems: 2 76 + 77 + wakeup-interrupt-controller: 78 + $ref: samsung,pinctrl-wakeup-interrupt.yaml 79 + 80 + patternProperties: 81 + "^[a-z]+[0-9]*-gpio-bank$": 82 + description: 83 + Pin banks of the controller are represented by child nodes of the 84 + controller node. Bank name is taken from name of the node. 85 + $ref: samsung,pinctrl-gpio-bank.yaml 86 + 87 + "^[a-z0-9-]+-pins$": 88 + oneOf: 89 + - $ref: samsung,pinctrl-pins-cfg.yaml 90 + required: 91 + - samsung,pins 92 + - type: object 93 + patternProperties: 94 + "^[a-z0-9-]+-pins$": 95 + $ref: samsung,pinctrl-pins-cfg.yaml 96 + 97 + additionalProperties: false 98 + 99 + "^(initial|sleep)-state$": 100 + patternProperties: 101 + "^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$": 102 + $ref: samsung,pinctrl-pins-cfg.yaml 103 + 104 + properties: 105 + samsung,pins: 106 + description: See samsung,pinctrl-pins-cfg.yaml 107 + $ref: /schemas/types.yaml#/definitions/string-array 108 + maxItems: 1 109 + 110 + required: 111 + - samsung,pins 112 + 113 + unevaluatedProperties: false 114 + 115 + required: 116 + - compatible 117 + - reg 118 + 119 + allOf: 120 + - $ref: "pinctrl.yaml#" 121 + - if: 122 + properties: 123 + compatible: 124 + contains: 125 + const: samsung,exynos5433-pinctrl 126 + then: 127 + properties: 128 + reg: 129 + minItems: 1 130 + maxItems: 2 131 + else: 132 + properties: 133 + reg: 134 + minItems: 1 135 + maxItems: 1 136 + 137 + additionalProperties: false 138 + 139 + examples: 140 + - | 141 + #include <dt-bindings/pinctrl/samsung.h> 142 + 143 + pinctrl@7f008000 { 144 + compatible = "samsung,s3c64xx-pinctrl"; 145 + reg = <0x7f008000 0x1000>; 146 + interrupt-parent = <&vic1>; 147 + interrupts = <21>; 148 + 149 + wakeup-interrupt-controller { 150 + compatible = "samsung,s3c64xx-wakeup-eint"; 151 + interrupts-extended = <&vic0 0>, 152 + <&vic0 1>, 153 + <&vic1 0>, 154 + <&vic1 1>; 155 + }; 156 + 157 + /* Pin bank with external GPIO or muxed external wake-up interrupts */ 158 + gpa-gpio-bank { 159 + gpio-controller; 160 + #gpio-cells = <2>; 161 + interrupt-controller; 162 + #interrupt-cells = <2>; 163 + }; 164 + 165 + // ... 166 + 167 + uart0-data-pins { 168 + samsung,pins = "gpa-0", "gpa-1"; 169 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 170 + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; 171 + }; 172 + 173 + // ... 174 + }; 175 + 176 + - | 177 + #include <dt-bindings/interrupt-controller/arm-gic.h> 178 + #include <dt-bindings/pinctrl/samsung.h> 179 + 180 + pinctrl@11400000 { 181 + compatible = "samsung,exynos4210-pinctrl"; 182 + reg = <0x11400000 0x1000>; 183 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 184 + 185 + pinctrl-names = "default"; 186 + pinctrl-0 = <&sleep0>; 187 + 188 + /* Pin bank with external GPIO or muxed external wake-up interrupts */ 189 + gpa0-gpio-bank { 190 + gpio-controller; 191 + #gpio-cells = <2>; 192 + interrupt-controller; 193 + #interrupt-cells = <2>; 194 + }; 195 + 196 + // ... 197 + 198 + uart0-data-pins { 199 + samsung,pins = "gpa0-0", "gpa0-1"; 200 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 201 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 202 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 203 + }; 204 + 205 + // ... 206 + 207 + sleep0: sleep-state { 208 + gpa0-0-pin { 209 + samsung,pins = "gpa0-0"; 210 + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>; 211 + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; 212 + }; 213 + 214 + gpa0-1-pin { 215 + samsung,pins = "gpa0-1"; 216 + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT0>; 217 + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; 218 + }; 219 + 220 + // ... 221 + }; 222 + }; 223 + 224 + - | 225 + #include <dt-bindings/interrupt-controller/arm-gic.h> 226 + #include <dt-bindings/pinctrl/samsung.h> 227 + 228 + pinctrl@11000000 { 229 + compatible = "samsung,exynos4210-pinctrl"; 230 + reg = <0x11000000 0x1000>; 231 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 232 + 233 + wakeup-interrupt-controller { 234 + compatible = "samsung,exynos4210-wakeup-eint"; 235 + interrupt-parent = <&gic>; 236 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 237 + }; 238 + 239 + /* Pin bank with external GPIO or muxed external wake-up interrupts */ 240 + gpj0-gpio-bank { 241 + gpio-controller; 242 + #gpio-cells = <2>; 243 + interrupt-controller; 244 + #interrupt-cells = <2>; 245 + }; 246 + 247 + /* Pin bank without external interrupts */ 248 + gpy0-gpio-bank { 249 + gpio-controller; 250 + #gpio-cells = <2>; 251 + }; 252 + 253 + /* Pin bank with external direct wake-up interrupts */ 254 + gpx0-gpio-bank { 255 + gpio-controller; 256 + #gpio-cells = <2>; 257 + 258 + interrupt-controller; 259 + interrupt-parent = <&gic>; 260 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 261 + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 262 + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 263 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 264 + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 265 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 266 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 267 + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 268 + #interrupt-cells = <2>; 269 + }; 270 + 271 + // ... 272 + 273 + sd0-clk-pins { 274 + samsung,pins = "gpk0-0"; 275 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 276 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 277 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 278 + }; 279 + 280 + sd4-bus-width8-pins { 281 + part-1-pins { 282 + samsung,pins = "gpk0-3", "gpk0-4", 283 + "gpk0-5", "gpk0-6"; 284 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 285 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 286 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 287 + }; 288 + 289 + part-2-pins { 290 + samsung,pins = "gpk1-3", "gpk1-4", 291 + "gpk1-5", "gpk1-6"; 292 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 293 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 294 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 295 + }; 296 + }; 297 + 298 + // ... 299 + 300 + otg-gp-pins { 301 + samsung,pins = "gpx3-3"; 302 + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; 303 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 304 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 305 + samsung,pin-val = <0>; 306 + }; 307 + }; 308 + 309 + - | 310 + #include <dt-bindings/interrupt-controller/arm-gic.h> 311 + #include <dt-bindings/pinctrl/samsung.h> 312 + 313 + pinctrl@10580000 { 314 + compatible = "samsung,exynos5433-pinctrl"; 315 + reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 316 + 317 + pinctrl-names = "default"; 318 + pinctrl-0 = <&initial_alive>; 319 + 320 + wakeup-interrupt-controller { 321 + compatible = "samsung,exynos7-wakeup-eint"; 322 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 323 + }; 324 + 325 + /* Pin bank with external direct wake-up interrupts */ 326 + gpa0-gpio-bank { 327 + gpio-controller; 328 + #gpio-cells = <2>; 329 + 330 + interrupt-controller; 331 + interrupt-parent = <&gic>; 332 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 333 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 334 + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 335 + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 336 + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 337 + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 338 + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 339 + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 340 + #interrupt-cells = <2>; 341 + }; 342 + 343 + // ... 344 + 345 + te-irq-pins { 346 + samsung,pins = "gpf1-3"; 347 + samsung,pin-function = <0xf>; 348 + }; 349 + 350 + // .. 351 + 352 + initial_alive: initial-state { 353 + gpa0-0-pin { 354 + samsung,pins = "gpa0-0"; 355 + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 356 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 357 + samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>; 358 + }; 359 + 360 + // ... 361 + }; 362 + }; 363 + 364 + - | 365 + #include <dt-bindings/interrupt-controller/arm-gic.h> 366 + #include <dt-bindings/pinctrl/samsung.h> 367 + 368 + pinctrl@114b0000 { 369 + compatible = "samsung,exynos5433-pinctrl"; 370 + reg = <0x114b0000 0x1000>; 371 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 372 + power-domains = <&pd_aud>; 373 + 374 + /* Pin bank with external GPIO or muxed external wake-up interrupts */ 375 + gpz0-gpio-bank { 376 + gpio-controller; 377 + #gpio-cells = <2>; 378 + interrupt-controller; 379 + #interrupt-cells = <2>; 380 + }; 381 + 382 + // ... 383 + 384 + i2s0-bus-pins { 385 + samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", 386 + "gpz0-4", "gpz0-5", "gpz0-6"; 387 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 388 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 389 + samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>; 390 + }; 391 + 392 + // ... 393 + };

-383

Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt

··· 1 - Samsung GPIO and Pin Mux/Config controller 2 - 3 - Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware 4 - controller. It controls the input/output settings on the available pads/pins 5 - and also provides ability to multiplex and configure the output of various 6 - on-chip controllers onto these pads. 7 - 8 - Required Properties: 9 - - compatible: should be one of the following. 10 - - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller, 11 - - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller, 12 - - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller, 13 - - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, 14 - - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, 15 - - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, 16 - - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller. 17 - - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. 18 - - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. 19 - - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. 20 - - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. 21 - - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. 22 - - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. 23 - - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. 24 - - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. 25 - - "samsung,exynos7885-pinctrl": for Exynos7885 compatible pin-controller. 26 - - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. 27 - - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller. 28 - 29 - - reg: Base address of the pin controller hardware module and length of 30 - the address space it occupies. 31 - 32 - - reg: Second base address of the pin controller if the specific registers 33 - of the pin controller are separated into the different base address. 34 - 35 - Eg: GPF[1-5] of Exynos5433 are separated into the two base address. 36 - - First base address is for GPAx and GPF[1-5] external interrupt 37 - registers. 38 - - Second base address is for GPF[1-5] pinctrl registers. 39 - 40 - pinctrl_0: pinctrl@10580000 { 41 - compatible = "samsung,exynos5433-pinctrl"; 42 - reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 43 - 44 - wakeup-interrupt-controller { 45 - compatible = "samsung,exynos7-wakeup-eint"; 46 - interrupts = <0 16 0>; 47 - }; 48 - }; 49 - 50 - - Pin banks as child nodes: Pin banks of the controller are represented by child 51 - nodes of the controller node. Bank name is taken from name of the node. Each 52 - bank node must contain following properties: 53 - 54 - - gpio-controller: identifies the node as a gpio controller and pin bank. 55 - - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO 56 - binding is used, the amount of cells must be specified as 2. See the below 57 - mentioned gpio binding representation for description of particular cells. 58 - 59 - Eg: <&gpx2 6 0> 60 - <[phandle of the gpio controller node] 61 - [pin number within the gpio controller] 62 - [flags]> 63 - 64 - Values for gpio specifier: 65 - - Pin number: is a value between 0 to 7. 66 - - Flags: 0 - Active High 67 - 1 - Active Low 68 - 69 - - Pin mux/config groups as child nodes: The pin mux (selecting pin function 70 - mode) and pin config (pull up/down, driver strength) settings are represented 71 - as child nodes of the pin-controller node. There should be at least one 72 - child node and there is no limit on the count of these child nodes. It is 73 - also possible for a child node to consist of several further child nodes 74 - to allow grouping multiple pinctrl groups into one. The format of second 75 - level child nodes is exactly the same as for first level ones and is 76 - described below. 77 - 78 - The child node should contain a list of pin(s) on which a particular pin 79 - function selection or pin configuration (or both) have to applied. This 80 - list of pins is specified using the property name "samsung,pins". There 81 - should be at least one pin specified for this property and there is no upper 82 - limit on the count of pins that can be specified. The pins are specified 83 - using pin names which are derived from the hardware manual of the SoC. As 84 - an example, the pins in GPA0 bank of the pin controller can be represented 85 - as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case. 86 - The format of the pin names should be (as per the hardware manual) 87 - "[pin bank name]-[pin number within the bank]". 88 - 89 - The pin function selection that should be applied on the pins listed in the 90 - child node is specified using the "samsung,pin-function" property. The value 91 - of this property that should be applied to each of the pins listed in the 92 - "samsung,pins" property should be picked from the hardware manual of the SoC 93 - for the specified pin group. This property is optional in the child node if 94 - no specific function selection is desired for the pins listed in the child 95 - node. The value of this property is used as-is to program the pin-controller 96 - function selector register of the pin-bank. 97 - 98 - The child node can also optionally specify one or more of the pin 99 - configuration that should be applied on all the pins listed in the 100 - "samsung,pins" property of the child node. The following pin configuration 101 - properties are supported. 102 - 103 - - samsung,pin-val: Initial value of pin output buffer. 104 - - samsung,pin-pud: Pull up/down configuration. 105 - - samsung,pin-drv: Drive strength configuration. 106 - - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. 107 - - samsung,pin-drv-pdn: Drive strength configuration in power down mode. 108 - 109 - The values specified by these config properties should be derived from the 110 - hardware manual and these values are programmed as-is into the pin 111 - pull up/down and driver strength register of the pin-controller. 112 - 113 - Note: A child should include at least a pin function selection property or 114 - pin configuration property (one or more) or both. 115 - 116 - The client nodes that require a particular pin function selection and/or 117 - pin configuration should use the bindings listed in the "pinctrl-bindings.txt" 118 - file. 119 - 120 - External GPIO and Wakeup Interrupts: 121 - 122 - The controller supports two types of external interrupts over gpio. The first 123 - is the external gpio interrupt and second is the external wakeup interrupts. 124 - The difference between the two is that the external wakeup interrupts can be 125 - used as system wakeup events. 126 - 127 - A. External GPIO Interrupts: For supporting external gpio interrupts, the 128 - following properties should be specified in the pin-controller device node. 129 - 130 - - interrupts: interrupt specifier for the controller. The format and value of 131 - the interrupt specifier depends on the interrupt parent for the controller. 132 - 133 - In addition, following properties must be present in node of every bank 134 - of pins supporting GPIO interrupts: 135 - 136 - - interrupt-controller: identifies the controller node as interrupt-parent. 137 - - #interrupt-cells: the value of this property should be 2. 138 - - First Cell: represents the external gpio interrupt number local to the 139 - external gpio interrupt space of the controller. 140 - - Second Cell: flags to identify the type of the interrupt 141 - - 1 = rising edge triggered 142 - - 2 = falling edge triggered 143 - - 3 = rising and falling edge triggered 144 - - 4 = high level triggered 145 - - 8 = low level triggered 146 - 147 - B. External Wakeup Interrupts: For supporting external wakeup interrupts, a 148 - child node representing the external wakeup interrupt controller should be 149 - included in the pin-controller device node. 150 - 151 - Only one pin-controller device node can include external wakeup interrupts 152 - child node (in other words, only one External Wakeup Interrupts 153 - pin-controller is supported). 154 - 155 - This child node should include following properties: 156 - 157 - - compatible: identifies the type of the external wakeup interrupt controller 158 - The possible values are: 159 - - samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller 160 - found on Samsung S3C24xx SoCs except S3C2412 and S3C2413, 161 - - samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller 162 - found on Samsung S3C2412 and S3C2413 SoCs, 163 - - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller 164 - found on Samsung S3C64xx SoCs, 165 - - samsung,s5pv210-wakeup-eint: represents wakeup interrupt controller 166 - found on Samsung S5Pv210 SoCs, 167 - - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller 168 - found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. 169 - - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller 170 - found on Samsung Exynos7 SoC. 171 - - interrupts: interrupt used by multiplexed wakeup interrupts. 172 - 173 - In addition, following properties must be present in node of every bank 174 - of pins supporting wake-up interrupts: 175 - 176 - - interrupt-controller: identifies the node as interrupt-parent. 177 - - #interrupt-cells: the value of this property should be 2 178 - - First Cell: represents the external wakeup interrupt number local to 179 - the external wakeup interrupt space of the controller. 180 - - Second Cell: flags to identify the type of the interrupt 181 - - 1 = rising edge triggered 182 - - 2 = falling edge triggered 183 - - 3 = rising and falling edge triggered 184 - - 4 = high level triggered 185 - - 8 = low level triggered 186 - 187 - Node of every bank of pins supporting direct wake-up interrupts (without 188 - multiplexing) must contain following properties: 189 - 190 - - interrupts: interrupts of the interrupt parent which are used for external 191 - wakeup interrupts from pins of the bank, must contain interrupts for all 192 - pins of the bank. 193 - 194 - Aliases: 195 - 196 - All the pin controller nodes should be represented in the aliases node using 197 - the following format 'pinctrl{n}' where n is a unique number for the alias. 198 - 199 - Aliases for controllers compatible with "samsung,exynos7-pinctrl": 200 - - pinctrl0: pin controller of ALIVE block, 201 - - pinctrl1: pin controller of BUS0 block, 202 - - pinctrl2: pin controller of NFC block, 203 - - pinctrl3: pin controller of TOUCH block, 204 - - pinctrl4: pin controller of FF block, 205 - - pinctrl5: pin controller of ESE block, 206 - - pinctrl6: pin controller of FSYS0 block, 207 - - pinctrl7: pin controller of FSYS1 block, 208 - - pinctrl8: pin controller of BUS1 block, 209 - - pinctrl9: pin controller of AUDIO block, 210 - 211 - Example: A pin-controller node with pin banks: 212 - 213 - pinctrl_0: pinctrl@11400000 { 214 - compatible = "samsung,exynos4210-pinctrl"; 215 - reg = <0x11400000 0x1000>; 216 - interrupts = <0 47 0>; 217 - 218 - /* ... */ 219 - 220 - /* Pin bank without external interrupts */ 221 - gpy0: gpy0 { 222 - gpio-controller; 223 - #gpio-cells = <2>; 224 - }; 225 - 226 - /* ... */ 227 - 228 - /* Pin bank with external GPIO or muxed wake-up interrupts */ 229 - gpj0: gpj0 { 230 - gpio-controller; 231 - #gpio-cells = <2>; 232 - 233 - interrupt-controller; 234 - #interrupt-cells = <2>; 235 - }; 236 - 237 - /* ... */ 238 - 239 - /* Pin bank with external direct wake-up interrupts */ 240 - gpx0: gpx0 { 241 - gpio-controller; 242 - #gpio-cells = <2>; 243 - 244 - interrupt-controller; 245 - interrupt-parent = <&gic>; 246 - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, 247 - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; 248 - #interrupt-cells = <2>; 249 - }; 250 - 251 - /* ... */ 252 - }; 253 - 254 - Example 1: A pin-controller node with pin groups. 255 - 256 - #include <dt-bindings/pinctrl/samsung.h> 257 - 258 - pinctrl_0: pinctrl@11400000 { 259 - compatible = "samsung,exynos4210-pinctrl"; 260 - reg = <0x11400000 0x1000>; 261 - interrupts = <0 47 0>; 262 - 263 - /* ... */ 264 - 265 - uart0_data: uart0-data { 266 - samsung,pins = "gpa0-0", "gpa0-1"; 267 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 268 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 269 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 270 - }; 271 - 272 - uart0_fctl: uart0-fctl { 273 - samsung,pins = "gpa0-2", "gpa0-3"; 274 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 275 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 276 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 277 - }; 278 - 279 - uart1_data: uart1-data { 280 - samsung,pins = "gpa0-4", "gpa0-5"; 281 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 282 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 283 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 284 - }; 285 - 286 - uart1_fctl: uart1-fctl { 287 - samsung,pins = "gpa0-6", "gpa0-7"; 288 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 289 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 290 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 291 - }; 292 - 293 - i2c2_bus: i2c2-bus { 294 - samsung,pins = "gpa0-6", "gpa0-7"; 295 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 296 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 297 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 298 - }; 299 - 300 - sd4_bus8: sd4-bus-width8 { 301 - part-1 { 302 - samsung,pins = "gpk0-3", "gpk0-4", 303 - "gpk0-5", "gpk0-6"; 304 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 305 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 306 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 307 - }; 308 - part-2 { 309 - samsung,pins = "gpk1-3", "gpk1-4", 310 - "gpk1-5", "gpk1-6"; 311 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 312 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 313 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 314 - }; 315 - }; 316 - }; 317 - 318 - Example 2: A pin-controller node with external wakeup interrupt controller node. 319 - 320 - pinctrl_1: pinctrl@11000000 { 321 - compatible = "samsung,exynos4210-pinctrl"; 322 - reg = <0x11000000 0x1000>; 323 - interrupts = <0 46 0> 324 - 325 - /* ... */ 326 - 327 - wakeup-interrupt-controller { 328 - compatible = "samsung,exynos4210-wakeup-eint"; 329 - interrupt-parent = <&gic>; 330 - interrupts = <0 32 0>; 331 - }; 332 - }; 333 - 334 - Example 3: A uart client node that supports 'default' and 'flow-control' states. 335 - 336 - uart@13800000 { 337 - compatible = "samsung,exynos4210-uart"; 338 - reg = <0x13800000 0x100>; 339 - interrupts = <0 52 0>; 340 - pinctrl-names = "default", "flow-control; 341 - pinctrl-0 = <&uart0_data>; 342 - pinctrl-1 = <&uart0_data>, <&uart0_fctl>; 343 - }; 344 - 345 - Example 4: Set up the default pin state for uart controller. 346 - 347 - static int s3c24xx_serial_probe(struct platform_device *pdev) { 348 - struct pinctrl *pinctrl; 349 - 350 - /* ... */ 351 - 352 - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 353 - } 354 - 355 - Example 5: A display port client node that supports 'default' pinctrl state 356 - and gpio binding. 357 - 358 - display-port-controller { 359 - /* ... */ 360 - 361 - samsung,hpd-gpio = <&gpx2 6 0>; 362 - pinctrl-names = "default"; 363 - pinctrl-0 = <&dp_hpd>; 364 - }; 365 - 366 - Example 6: Request the gpio for display port controller 367 - 368 - static int exynos_dp_probe(struct platform_device *pdev) 369 - { 370 - int hpd_gpio, ret; 371 - struct device *dev = &pdev->dev; 372 - struct device_node *dp_node = dev->of_node; 373 - 374 - /* ... */ 375 - 376 - hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0); 377 - 378 - /* ... */ 379 - 380 - ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN, 381 - "hpd_gpio"); 382 - /* ... */ 383 - }

+1 -1

MAINTAINERS

··· 15293 15293 S: Maintained 15294 15294 Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/ 15295 15295 T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git 15296 - F: Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt 15296 + F: Documentation/devicetree/bindings/pinctrl/samsung,pinctrl*yaml 15297 15297 F: drivers/pinctrl/samsung/ 15298 15298 F: include/dt-bindings/pinctrl/samsung.h 15299 15299

+71 -2

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

··· 585 585 /* pin-controller instance 0 ALIVE data */ 586 586 .pin_banks = exynos850_pin_banks0, 587 587 .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), 588 - .eint_gpio_init = exynos_eint_gpio_init, 589 588 .eint_wkup_init = exynos_eint_wkup_init, 590 589 }, { 591 590 /* pin-controller instance 1 CMGP data */ 592 591 .pin_banks = exynos850_pin_banks1, 593 592 .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), 594 - .eint_gpio_init = exynos_eint_gpio_init, 595 593 .eint_wkup_init = exynos_eint_wkup_init, 596 594 }, { 597 595 /* pin-controller instance 2 AUD data */ ··· 724 726 const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { 725 727 .ctrl = exynosautov9_pin_ctrl, 726 728 .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl), 729 + }; 730 + 731 + /* 732 + * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three 733 + * gpio/pin-mux/pinconfig controllers. 734 + */ 735 + 736 + /* pin banks of FSD pin-controller 0 (FSYS) */ 737 + static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { 738 + EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00), 739 + EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04), 740 + EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08), 741 + EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c), 742 + EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10), 743 + }; 744 + 745 + /* pin banks of FSD pin-controller 1 (PERIC) */ 746 + static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { 747 + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00), 748 + EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04), 749 + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08), 750 + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c), 751 + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10), 752 + EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14), 753 + EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18), 754 + EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c), 755 + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20), 756 + EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24), 757 + EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28), 758 + EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), 759 + EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30), 760 + EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34), 761 + EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38), 762 + EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c), 763 + EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 764 + EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44), 765 + EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48), 766 + EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c), 767 + EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50), 768 + }; 769 + 770 + /* pin banks of FSD pin-controller 2 (PMU) */ 771 + static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { 772 + EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"), 773 + }; 774 + 775 + const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { 776 + { 777 + /* pin-controller instance 0 FSYS0 data */ 778 + .pin_banks = fsd_pin_banks0, 779 + .nr_banks = ARRAY_SIZE(fsd_pin_banks0), 780 + .eint_gpio_init = exynos_eint_gpio_init, 781 + .suspend = exynos_pinctrl_suspend, 782 + .resume = exynos_pinctrl_resume, 783 + }, { 784 + /* pin-controller instance 1 PERIC data */ 785 + .pin_banks = fsd_pin_banks1, 786 + .nr_banks = ARRAY_SIZE(fsd_pin_banks1), 787 + .eint_gpio_init = exynos_eint_gpio_init, 788 + .suspend = exynos_pinctrl_suspend, 789 + .resume = exynos_pinctrl_resume, 790 + }, { 791 + /* pin-controller instance 2 PMU data */ 792 + .pin_banks = fsd_pin_banks2, 793 + .nr_banks = ARRAY_SIZE(fsd_pin_banks2), 794 + }, 795 + }; 796 + 797 + const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { 798 + .ctrl = fsd_pin_ctrl, 799 + .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), 727 800 };

+6 -1

drivers/pinctrl/samsung/pinctrl-exynos.c

··· 344 344 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 345 345 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); 346 346 347 - pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); 347 + pr_info("wake %s for irq %u (%s-%lu)\n", on ? "enabled" : "disabled", 348 + irqd->irq, bank->name, irqd->hwirq); 348 349 349 350 if (!on) 350 351 *our_chip->eint_wake_mask_value |= bit; ··· 465 464 { .compatible = "samsung,exynos4210-wakeup-eint", 466 465 .data = &exynos4210_wkup_irq_chip }, 467 466 { .compatible = "samsung,exynos7-wakeup-eint", 467 + .data = &exynos7_wkup_irq_chip }, 468 + { .compatible = "samsung,exynos850-wakeup-eint", 469 + .data = &exynos7_wkup_irq_chip }, 470 + { .compatible = "samsung,exynosautov9-wakeup-eint", 468 471 .data = &exynos7_wkup_irq_chip }, 469 472 { } 470 473 };

+70 -19

drivers/pinctrl/samsung/pinctrl-samsung.c

··· 1002 1002 return &(of_data->ctrl[id]); 1003 1003 } 1004 1004 1005 + static void samsung_banks_of_node_put(struct samsung_pinctrl_drv_data *d) 1006 + { 1007 + struct samsung_pin_bank *bank; 1008 + unsigned int i; 1009 + 1010 + bank = d->pin_banks; 1011 + for (i = 0; i < d->nr_banks; ++i, ++bank) 1012 + of_node_put(bank->of_node); 1013 + } 1014 + 1015 + /* 1016 + * Iterate over all driver pin banks to find one matching the name of node, 1017 + * skipping optional "-gpio" node suffix. When found, assign node to the bank. 1018 + */ 1019 + static void samsung_banks_of_node_get(struct device *dev, 1020 + struct samsung_pinctrl_drv_data *d, 1021 + struct device_node *node) 1022 + { 1023 + const char *suffix = "-gpio-bank"; 1024 + struct samsung_pin_bank *bank; 1025 + struct device_node *child; 1026 + /* Pin bank names are up to 4 characters */ 1027 + char node_name[20]; 1028 + unsigned int i; 1029 + size_t len; 1030 + 1031 + bank = d->pin_banks; 1032 + for (i = 0; i < d->nr_banks; ++i, ++bank) { 1033 + strscpy(node_name, bank->name, sizeof(node_name)); 1034 + len = strlcat(node_name, suffix, sizeof(node_name)); 1035 + if (len >= sizeof(node_name)) { 1036 + dev_err(dev, "Too long pin bank name '%s', ignoring\n", 1037 + bank->name); 1038 + continue; 1039 + } 1040 + 1041 + for_each_child_of_node(node, child) { 1042 + if (!of_find_property(child, "gpio-controller", NULL)) 1043 + continue; 1044 + if (of_node_name_eq(child, node_name)) 1045 + break; 1046 + else if (of_node_name_eq(child, bank->name)) 1047 + break; 1048 + } 1049 + 1050 + if (child) 1051 + bank->of_node = child; 1052 + else 1053 + dev_warn(dev, "Missing node for bank %s - invalid DTB\n", 1054 + bank->name); 1055 + /* child reference dropped in samsung_drop_banks_of_node() */ 1056 + } 1057 + } 1058 + 1005 1059 /* retrieve the soc specific data */ 1006 1060 static const struct samsung_pin_ctrl * 1007 1061 samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, 1008 1062 struct platform_device *pdev) 1009 1063 { 1010 1064 struct device_node *node = pdev->dev.of_node; 1011 - struct device_node *np; 1012 1065 const struct samsung_pin_bank_data *bdata; 1013 1066 const struct samsung_pin_ctrl *ctrl; 1014 1067 struct samsung_pin_bank *bank; ··· 1125 1072 */ 1126 1073 d->virt_base = virt_base[0]; 1127 1074 1128 - for_each_child_of_node(node, np) { 1129 - if (!of_find_property(np, "gpio-controller", NULL)) 1130 - continue; 1131 - bank = d->pin_banks; 1132 - for (i = 0; i < d->nr_banks; ++i, ++bank) { 1133 - if (of_node_name_eq(np, bank->name)) { 1134 - bank->of_node = np; 1135 - break; 1136 - } 1137 - } 1138 - } 1075 + samsung_banks_of_node_get(&pdev->dev, d, node); 1139 1076 1140 1077 d->pin_base = pin_base; 1141 1078 pin_base += d->nr_pins; ··· 1160 1117 if (ctrl->retention_data) { 1161 1118 drvdata->retention_ctrl = ctrl->retention_data->init(drvdata, 1162 1119 ctrl->retention_data); 1163 - if (IS_ERR(drvdata->retention_ctrl)) 1164 - return PTR_ERR(drvdata->retention_ctrl); 1120 + if (IS_ERR(drvdata->retention_ctrl)) { 1121 + ret = PTR_ERR(drvdata->retention_ctrl); 1122 + goto err_put_banks; 1123 + } 1165 1124 } 1166 1125 1167 1126 ret = samsung_pinctrl_register(pdev, drvdata); 1168 1127 if (ret) 1169 - return ret; 1128 + goto err_put_banks; 1170 1129 1171 1130 ret = samsung_gpiolib_register(pdev, drvdata); 1172 - if (ret) { 1173 - samsung_pinctrl_unregister(pdev, drvdata); 1174 - return ret; 1175 - } 1131 + if (ret) 1132 + goto err_unregister; 1176 1133 1177 1134 if (ctrl->eint_gpio_init) 1178 1135 ctrl->eint_gpio_init(drvdata); ··· 1182 1139 platform_set_drvdata(pdev, drvdata); 1183 1140 1184 1141 return 0; 1142 + 1143 + err_unregister: 1144 + samsung_pinctrl_unregister(pdev, drvdata); 1145 + err_put_banks: 1146 + samsung_banks_of_node_put(drvdata); 1147 + return ret; 1185 1148 } 1186 1149 1187 1150 /* ··· 1320 1271 .data = &exynos850_of_data }, 1321 1272 { .compatible = "samsung,exynosautov9-pinctrl", 1322 1273 .data = &exynosautov9_of_data }, 1274 + { .compatible = "tesla,fsd-pinctrl", 1275 + .data = &fsd_of_data }, 1323 1276 #endif 1324 1277 #ifdef CONFIG_PINCTRL_S3C64XX 1325 1278 { .compatible = "samsung,s3c64xx-pinctrl",

+1

drivers/pinctrl/samsung/pinctrl-samsung.h

··· 342 342 extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; 343 343 extern const struct samsung_pinctrl_of_match_data exynos850_of_data; 344 344 extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; 345 + extern const struct samsung_pinctrl_of_match_data fsd_of_data; 345 346 extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; 346 347 extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; 347 348 extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;