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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/tegra: hdmi - Add Tegra124 support
Tegra124 is mostly backwards-compatible with Tegra114. However, Tegra124
supports a few more features (e.g. interlacing, ...). Introduce a new
compatible string and TMDS tables to cope with these differences.
Signed-off-by: Thierry Reding <treding@nvidia.com>
+89
+1
drivers/gpu/drm/tegra/drm.c
+1
drivers/gpu/drm/tegra/drm.c
+88
drivers/gpu/drm/tegra/hdmi.c
+88
drivers/gpu/drm/tegra/hdmi.c
···
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},
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};
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+
static const struct tmds_config tegra124_tmds_config[] = {
322
+
{ /* 480p/576p / 25.2MHz/27MHz modes */
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+
.pclk = 27000000,
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+
.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
325
+
SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
326
+
.pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
327
+
.pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
328
+
PE_CURRENT1(PE_CURRENT_0_mA_T114) |
329
+
PE_CURRENT2(PE_CURRENT_0_mA_T114) |
330
+
PE_CURRENT3(PE_CURRENT_0_mA_T114),
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+
.drive_current =
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+
DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
333
+
DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
334
+
DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
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+
DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
336
+
.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
337
+
PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
338
+
PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
339
+
PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
340
+
}, { /* 720p / 74.25MHz modes */
341
+
.pclk = 74250000,
342
+
.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
343
+
SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
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+
.pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
345
+
SOR_PLL_TMDS_TERMADJ(0),
346
+
.pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
347
+
PE_CURRENT1(PE_CURRENT_15_mA_T114) |
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+
PE_CURRENT2(PE_CURRENT_15_mA_T114) |
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+
PE_CURRENT3(PE_CURRENT_15_mA_T114),
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+
.drive_current =
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+
DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
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+
DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
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+
DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
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+
DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
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+
.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
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+
PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
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+
PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
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+
PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
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+
}, { /* 1080p / 148.5MHz modes */
360
+
.pclk = 148500000,
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+
.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
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+
SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
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+
.pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
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+
SOR_PLL_TMDS_TERMADJ(0),
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+
.pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
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+
PE_CURRENT1(PE_CURRENT_10_mA_T114) |
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+
PE_CURRENT2(PE_CURRENT_10_mA_T114) |
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+
PE_CURRENT3(PE_CURRENT_10_mA_T114),
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+
.drive_current =
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+
DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
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+
DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
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+
DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
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+
DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
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+
.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
375
+
PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
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+
PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
377
+
PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
378
+
}, { /* 225/297MHz modes */
379
+
.pclk = UINT_MAX,
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+
.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
381
+
SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
382
+
.pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
383
+
| SOR_PLL_TMDS_TERM_ENABLE,
384
+
.pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
385
+
PE_CURRENT1(PE_CURRENT_0_mA_T114) |
386
+
PE_CURRENT2(PE_CURRENT_0_mA_T114) |
387
+
PE_CURRENT3(PE_CURRENT_0_mA_T114),
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+
.drive_current =
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+
DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
390
+
DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
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+
DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
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+
DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
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+
.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
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+
PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
395
+
PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
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+
PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
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+
},
398
+
};
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+
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400
static const struct tegra_hdmi_audio_config *
322
401
tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
323
402
{
···
1435
1356
.has_sor_io_peak_current = true,
1436
1357
};
1437
1358
1359
+
static const struct tegra_hdmi_config tegra124_hdmi_config = {
1360
+
.tmds = tegra124_tmds_config,
1361
+
.num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1362
+
.fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1363
+
.fuse_override_value = 1 << 31,
1364
+
.has_sor_io_peak_current = true,
1365
+
};
1366
+
1438
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static const struct of_device_id tegra_hdmi_of_match[] = {
1368
+
{ .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
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{ .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
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1370
{ .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1441
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{ .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },