tjh.dev
+1
arch/powerpc/boot/zImage.lds.S
+1
arch/powerpc/boot/zImage.lds.S
+4
arch/powerpc/include/asm/bitops.h
+4
arch/powerpc/include/asm/bitops.h
···
51
51
#define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit))
52
52
#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
53
53
54
+
/* Put a PPC bit into a "normal" bit position */
55
+
#define PPC_BITEXTRACT(bits, ppc_bit, dst_bit) \
56
+
((((bits) >> PPC_BITLSHIFT(ppc_bit)) & 1) << (dst_bit))
57
+
54
58
#include <asm/barrier.h>
55
59
56
60
/* Macro for generating the ***_bits() functions */
+107
-1
arch/powerpc/include/asm/mce.h
+107
-1
arch/powerpc/include/asm/mce.h
···
66
66
67
67
#define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS | \
68
68
P8_DSISR_MC_ERAT_MULTIHIT_SEC)
69
+
70
+
/*
71
+
* Machine Check bits on power9
72
+
*/
73
+
#define P9_SRR1_MC_LOADSTORE(srr1) (((srr1) >> PPC_BITLSHIFT(42)) & 1)
74
+
75
+
#define P9_SRR1_MC_IFETCH(srr1) ( \
76
+
PPC_BITEXTRACT(srr1, 45, 0) | \
77
+
PPC_BITEXTRACT(srr1, 44, 1) | \
78
+
PPC_BITEXTRACT(srr1, 43, 2) | \
79
+
PPC_BITEXTRACT(srr1, 36, 3) )
80
+
81
+
/* 0 is reserved */
82
+
#define P9_SRR1_MC_IFETCH_UE 1
83
+
#define P9_SRR1_MC_IFETCH_SLB_PARITY 2
84
+
#define P9_SRR1_MC_IFETCH_SLB_MULTIHIT 3
85
+
#define P9_SRR1_MC_IFETCH_ERAT_MULTIHIT 4
86
+
#define P9_SRR1_MC_IFETCH_TLB_MULTIHIT 5
87
+
#define P9_SRR1_MC_IFETCH_UE_TLB_RELOAD 6
88
+
/* 7 is reserved */
89
+
#define P9_SRR1_MC_IFETCH_LINK_TIMEOUT 8
90
+
#define P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT 9
91
+
/* 10 ? */
92
+
#define P9_SRR1_MC_IFETCH_RA 11
93
+
#define P9_SRR1_MC_IFETCH_RA_TABLEWALK 12
94
+
#define P9_SRR1_MC_IFETCH_RA_ASYNC_STORE 13
95
+
#define P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT 14
96
+
#define P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN 15
97
+
98
+
/* DSISR bits for machine check (On Power9) */
99
+
#define P9_DSISR_MC_UE (PPC_BIT(48))
100
+
#define P9_DSISR_MC_UE_TABLEWALK (PPC_BIT(49))
101
+
#define P9_DSISR_MC_LINK_LOAD_TIMEOUT (PPC_BIT(50))
102
+
#define P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT (PPC_BIT(51))
103
+
#define P9_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52))
104
+
#define P9_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53))
105
+
#define P9_DSISR_MC_USER_TLBIE (PPC_BIT(54))
106
+
#define P9_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55))
107
+
#define P9_DSISR_MC_SLB_MULTIHIT_MFSLB (PPC_BIT(56))
108
+
#define P9_DSISR_MC_RA_LOAD (PPC_BIT(57))
109
+
#define P9_DSISR_MC_RA_TABLEWALK (PPC_BIT(58))
110
+
#define P9_DSISR_MC_RA_TABLEWALK_FOREIGN (PPC_BIT(59))
111
+
#define P9_DSISR_MC_RA_FOREIGN (PPC_BIT(60))
112
+
113
+
/* SLB error bits */
114
+
#define P9_DSISR_MC_SLB_ERRORS (P9_DSISR_MC_ERAT_MULTIHIT | \
115
+
P9_DSISR_MC_SLB_PARITY_MFSLB | \
116
+
P9_DSISR_MC_SLB_MULTIHIT_MFSLB)
117
+
69
118
enum MCE_Version {
70
119
MCE_V1 = 1,
71
120
};
···
142
93
MCE_ERROR_TYPE_SLB = 2,
143
94
MCE_ERROR_TYPE_ERAT = 3,
144
95
MCE_ERROR_TYPE_TLB = 4,
96
+
MCE_ERROR_TYPE_USER = 5,
97
+
MCE_ERROR_TYPE_RA = 6,
98
+
MCE_ERROR_TYPE_LINK = 7,
145
99
};
146
100
147
101
enum MCE_UeErrorType {
···
171
119
MCE_TLB_ERROR_INDETERMINATE = 0,
172
120
MCE_TLB_ERROR_PARITY = 1,
173
121
MCE_TLB_ERROR_MULTIHIT = 2,
122
+
};
123
+
124
+
enum MCE_UserErrorType {
125
+
MCE_USER_ERROR_INDETERMINATE = 0,
126
+
MCE_USER_ERROR_TLBIE = 1,
127
+
};
128
+
129
+
enum MCE_RaErrorType {
130
+
MCE_RA_ERROR_INDETERMINATE = 0,
131
+
MCE_RA_ERROR_IFETCH = 1,
132
+
MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
133
+
MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN = 3,
134
+
MCE_RA_ERROR_LOAD = 4,
135
+
MCE_RA_ERROR_STORE = 5,
136
+
MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 6,
137
+
MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN = 7,
138
+
MCE_RA_ERROR_LOAD_STORE_FOREIGN = 8,
139
+
};
140
+
141
+
enum MCE_LinkErrorType {
142
+
MCE_LINK_ERROR_INDETERMINATE = 0,
143
+
MCE_LINK_ERROR_IFETCH_TIMEOUT = 1,
144
+
MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT = 2,
145
+
MCE_LINK_ERROR_LOAD_TIMEOUT = 3,
146
+
MCE_LINK_ERROR_STORE_TIMEOUT = 4,
147
+
MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT = 5,
174
148
};
175
149
176
150
struct machine_check_event {
···
244
166
uint64_t effective_address;
245
167
uint8_t reserved_2[16];
246
168
} tlb_error;
169
+
170
+
struct {
171
+
enum MCE_UserErrorType user_error_type:8;
172
+
uint8_t effective_address_provided;
173
+
uint8_t reserved_1[6];
174
+
uint64_t effective_address;
175
+
uint8_t reserved_2[16];
176
+
} user_error;
177
+
178
+
struct {
179
+
enum MCE_RaErrorType ra_error_type:8;
180
+
uint8_t effective_address_provided;
181
+
uint8_t reserved_1[6];
182
+
uint64_t effective_address;
183
+
uint8_t reserved_2[16];
184
+
} ra_error;
185
+
186
+
struct {
187
+
enum MCE_LinkErrorType link_error_type:8;
188
+
uint8_t effective_address_provided;
189
+
uint8_t reserved_1[6];
190
+
uint64_t effective_address;
191
+
uint8_t reserved_2[16];
192
+
} link_error;
247
193
} u;
248
194
};
249
195
···
278
176
enum MCE_SlbErrorType slb_error_type:8;
279
177
enum MCE_EratErrorType erat_error_type:8;
280
178
enum MCE_TlbErrorType tlb_error_type:8;
179
+
enum MCE_UserErrorType user_error_type:8;
180
+
enum MCE_RaErrorType ra_error_type:8;
181
+
enum MCE_LinkErrorType link_error_type:8;
281
182
} u;
282
-
uint8_t reserved[2];
183
+
enum MCE_Severity severity:8;
184
+
enum MCE_Initiator initiator:8;
283
185
};
284
186
285
187
#define MAX_MC_EVT 100
+3
arch/powerpc/kernel/cputable.c
+3
arch/powerpc/kernel/cputable.c
···
77
77
extern void __flush_tlb_power9(unsigned int action);
78
78
extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
79
79
extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
80
+
extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
80
81
#endif /* CONFIG_PPC64 */
81
82
#if defined(CONFIG_E500)
82
83
extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
···
541
540
.cpu_setup = __setup_cpu_power9,
542
541
.cpu_restore = __restore_cpu_power9,
543
542
.flush_tlb = __flush_tlb_power9,
543
+
.machine_check_early = __machine_check_early_realmode_p9,
544
544
.platform = "power9",
545
545
},
546
546
{ /* Power9 */
···
561
559
.cpu_setup = __setup_cpu_power9,
562
560
.cpu_restore = __restore_cpu_power9,
563
561
.flush_tlb = __flush_tlb_power9,
562
+
.machine_check_early = __machine_check_early_realmode_p9,
564
563
.platform = "power9",
565
564
},
566
565
{ /* Cell Broadband Engine */
+86
-2
arch/powerpc/kernel/mce.c
+86
-2
arch/powerpc/kernel/mce.c
···
58
58
case MCE_ERROR_TYPE_TLB:
59
59
mce->u.tlb_error.tlb_error_type = mce_err->u.tlb_error_type;
60
60
break;
61
+
case MCE_ERROR_TYPE_USER:
62
+
mce->u.user_error.user_error_type = mce_err->u.user_error_type;
63
+
break;
64
+
case MCE_ERROR_TYPE_RA:
65
+
mce->u.ra_error.ra_error_type = mce_err->u.ra_error_type;
66
+
break;
67
+
case MCE_ERROR_TYPE_LINK:
68
+
mce->u.link_error.link_error_type = mce_err->u.link_error_type;
69
+
break;
61
70
case MCE_ERROR_TYPE_UNKNOWN:
62
71
default:
63
72
break;
···
99
90
mce->gpr3 = regs->gpr[3];
100
91
mce->in_use = 1;
101
92
102
-
mce->initiator = MCE_INITIATOR_CPU;
103
93
/* Mark it recovered if we have handled it and MSR(RI=1). */
104
94
if (handled && (regs->msr & MSR_RI))
105
95
mce->disposition = MCE_DISPOSITION_RECOVERED;
106
96
else
107
97
mce->disposition = MCE_DISPOSITION_NOT_RECOVERED;
108
-
mce->severity = MCE_SEV_ERROR_SYNC;
98
+
99
+
mce->initiator = mce_err->initiator;
100
+
mce->severity = mce_err->severity;
109
101
110
102
/*
111
103
* Populate the mce error_type and type-specific error_type.
···
125
115
} else if (mce->error_type == MCE_ERROR_TYPE_ERAT) {
126
116
mce->u.erat_error.effective_address_provided = true;
127
117
mce->u.erat_error.effective_address = addr;
118
+
} else if (mce->error_type == MCE_ERROR_TYPE_USER) {
119
+
mce->u.user_error.effective_address_provided = true;
120
+
mce->u.user_error.effective_address = addr;
121
+
} else if (mce->error_type == MCE_ERROR_TYPE_RA) {
122
+
mce->u.ra_error.effective_address_provided = true;
123
+
mce->u.ra_error.effective_address = addr;
124
+
} else if (mce->error_type == MCE_ERROR_TYPE_LINK) {
125
+
mce->u.link_error.effective_address_provided = true;
126
+
mce->u.link_error.effective_address = addr;
128
127
} else if (mce->error_type == MCE_ERROR_TYPE_UE) {
129
128
mce->u.ue_error.effective_address_provided = true;
130
129
mce->u.ue_error.effective_address = addr;
···
258
239
"Parity",
259
240
"Multihit",
260
241
};
242
+
static const char *mc_user_types[] = {
243
+
"Indeterminate",
244
+
"tlbie(l) invalid",
245
+
};
246
+
static const char *mc_ra_types[] = {
247
+
"Indeterminate",
248
+
"Instruction fetch (bad)",
249
+
"Page table walk ifetch (bad)",
250
+
"Page table walk ifetch (foreign)",
251
+
"Load (bad)",
252
+
"Store (bad)",
253
+
"Page table walk Load/Store (bad)",
254
+
"Page table walk Load/Store (foreign)",
255
+
"Load/Store (foreign)",
256
+
};
257
+
static const char *mc_link_types[] = {
258
+
"Indeterminate",
259
+
"Instruction fetch (timeout)",
260
+
"Page table walk ifetch (timeout)",
261
+
"Load (timeout)",
262
+
"Store (timeout)",
263
+
"Page table walk Load/Store (timeout)",
264
+
};
261
265
262
266
/* Print things out */
263
267
if (evt->version != MCE_V1) {
···
357
315
printk("%s Effective address: %016llx\n",
358
316
level, evt->u.tlb_error.effective_address);
359
317
break;
318
+
case MCE_ERROR_TYPE_USER:
319
+
subtype = evt->u.user_error.user_error_type <
320
+
ARRAY_SIZE(mc_user_types) ?
321
+
mc_user_types[evt->u.user_error.user_error_type]
322
+
: "Unknown";
323
+
printk("%s Error type: User [%s]\n", level, subtype);
324
+
if (evt->u.user_error.effective_address_provided)
325
+
printk("%s Effective address: %016llx\n",
326
+
level, evt->u.user_error.effective_address);
327
+
break;
328
+
case MCE_ERROR_TYPE_RA:
329
+
subtype = evt->u.ra_error.ra_error_type <
330
+
ARRAY_SIZE(mc_ra_types) ?
331
+
mc_ra_types[evt->u.ra_error.ra_error_type]
332
+
: "Unknown";
333
+
printk("%s Error type: Real address [%s]\n", level, subtype);
334
+
if (evt->u.ra_error.effective_address_provided)
335
+
printk("%s Effective address: %016llx\n",
336
+
level, evt->u.ra_error.effective_address);
337
+
break;
338
+
case MCE_ERROR_TYPE_LINK:
339
+
subtype = evt->u.link_error.link_error_type <
340
+
ARRAY_SIZE(mc_link_types) ?
341
+
mc_link_types[evt->u.link_error.link_error_type]
342
+
: "Unknown";
343
+
printk("%s Error type: Link [%s]\n", level, subtype);
344
+
if (evt->u.link_error.effective_address_provided)
345
+
printk("%s Effective address: %016llx\n",
346
+
level, evt->u.link_error.effective_address);
347
+
break;
360
348
default:
361
349
case MCE_ERROR_TYPE_UNKNOWN:
362
350
printk("%s Error type: Unknown\n", level);
···
412
340
case MCE_ERROR_TYPE_TLB:
413
341
if (evt->u.tlb_error.effective_address_provided)
414
342
return evt->u.tlb_error.effective_address;
343
+
break;
344
+
case MCE_ERROR_TYPE_USER:
345
+
if (evt->u.user_error.effective_address_provided)
346
+
return evt->u.user_error.effective_address;
347
+
break;
348
+
case MCE_ERROR_TYPE_RA:
349
+
if (evt->u.ra_error.effective_address_provided)
350
+
return evt->u.ra_error.effective_address;
351
+
break;
352
+
case MCE_ERROR_TYPE_LINK:
353
+
if (evt->u.link_error.effective_address_provided)
354
+
return evt->u.link_error.effective_address;
415
355
break;
416
356
default:
417
357
case MCE_ERROR_TYPE_UNKNOWN:
+237
arch/powerpc/kernel/mce_power.c
+237
arch/powerpc/kernel/mce_power.c
···
116
116
}
117
117
#endif
118
118
119
+
static void flush_erat(void)
120
+
{
121
+
asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
122
+
}
123
+
124
+
#define MCE_FLUSH_SLB 1
125
+
#define MCE_FLUSH_TLB 2
126
+
#define MCE_FLUSH_ERAT 3
127
+
128
+
static int mce_flush(int what)
129
+
{
130
+
#ifdef CONFIG_PPC_STD_MMU_64
131
+
if (what == MCE_FLUSH_SLB) {
132
+
flush_and_reload_slb();
133
+
return 1;
134
+
}
135
+
#endif
136
+
if (what == MCE_FLUSH_ERAT) {
137
+
flush_erat();
138
+
return 1;
139
+
}
140
+
if (what == MCE_FLUSH_TLB) {
141
+
if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
142
+
cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL);
143
+
return 1;
144
+
}
145
+
}
146
+
147
+
return 0;
148
+
}
149
+
150
+
static int mce_handle_flush_derrors(uint64_t dsisr, uint64_t slb, uint64_t tlb, uint64_t erat)
151
+
{
152
+
if ((dsisr & slb) && mce_flush(MCE_FLUSH_SLB))
153
+
dsisr &= ~slb;
154
+
if ((dsisr & erat) && mce_flush(MCE_FLUSH_ERAT))
155
+
dsisr &= ~erat;
156
+
if ((dsisr & tlb) && mce_flush(MCE_FLUSH_TLB))
157
+
dsisr &= ~tlb;
158
+
/* Any other errors we don't understand? */
159
+
if (dsisr)
160
+
return 0;
161
+
return 1;
162
+
}
163
+
119
164
static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
120
165
{
121
166
long handled = 1;
···
326
281
long handled = 1;
327
282
struct mce_error_info mce_error_info = { 0 };
328
283
284
+
mce_error_info.severity = MCE_SEV_ERROR_SYNC;
285
+
mce_error_info.initiator = MCE_INITIATOR_CPU;
286
+
329
287
srr1 = regs->msr;
330
288
nip = regs->nip;
331
289
···
400
352
long handled = 1;
401
353
struct mce_error_info mce_error_info = { 0 };
402
354
355
+
mce_error_info.severity = MCE_SEV_ERROR_SYNC;
356
+
mce_error_info.initiator = MCE_INITIATOR_CPU;
357
+
403
358
srr1 = regs->msr;
404
359
nip = regs->nip;
405
360
···
414
363
handled = mce_handle_ierror_p8(srr1);
415
364
mce_get_ierror_p8(&mce_error_info, srr1);
416
365
addr = regs->nip;
366
+
}
367
+
368
+
/* Handle UE error. */
369
+
if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
370
+
handled = mce_handle_ue_error(regs);
371
+
372
+
save_mce_event(regs, handled, &mce_error_info, nip, addr);
373
+
return handled;
374
+
}
375
+
376
+
static int mce_handle_derror_p9(struct pt_regs *regs)
377
+
{
378
+
uint64_t dsisr = regs->dsisr;
379
+
380
+
return mce_handle_flush_derrors(dsisr,
381
+
P9_DSISR_MC_SLB_PARITY_MFSLB |
382
+
P9_DSISR_MC_SLB_MULTIHIT_MFSLB,
383
+
384
+
P9_DSISR_MC_TLB_MULTIHIT_MFTLB,
385
+
386
+
P9_DSISR_MC_ERAT_MULTIHIT);
387
+
}
388
+
389
+
static int mce_handle_ierror_p9(struct pt_regs *regs)
390
+
{
391
+
uint64_t srr1 = regs->msr;
392
+
393
+
switch (P9_SRR1_MC_IFETCH(srr1)) {
394
+
case P9_SRR1_MC_IFETCH_SLB_PARITY:
395
+
case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
396
+
return mce_flush(MCE_FLUSH_SLB);
397
+
case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
398
+
return mce_flush(MCE_FLUSH_TLB);
399
+
case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
400
+
return mce_flush(MCE_FLUSH_ERAT);
401
+
default:
402
+
return 0;
403
+
}
404
+
}
405
+
406
+
static void mce_get_derror_p9(struct pt_regs *regs,
407
+
struct mce_error_info *mce_err, uint64_t *addr)
408
+
{
409
+
uint64_t dsisr = regs->dsisr;
410
+
411
+
mce_err->severity = MCE_SEV_ERROR_SYNC;
412
+
mce_err->initiator = MCE_INITIATOR_CPU;
413
+
414
+
if (dsisr & P9_DSISR_MC_USER_TLBIE)
415
+
*addr = regs->nip;
416
+
else
417
+
*addr = regs->dar;
418
+
419
+
if (dsisr & P9_DSISR_MC_UE) {
420
+
mce_err->error_type = MCE_ERROR_TYPE_UE;
421
+
mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE;
422
+
} else if (dsisr & P9_DSISR_MC_UE_TABLEWALK) {
423
+
mce_err->error_type = MCE_ERROR_TYPE_UE;
424
+
mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
425
+
} else if (dsisr & P9_DSISR_MC_LINK_LOAD_TIMEOUT) {
426
+
mce_err->error_type = MCE_ERROR_TYPE_LINK;
427
+
mce_err->u.link_error_type = MCE_LINK_ERROR_LOAD_TIMEOUT;
428
+
} else if (dsisr & P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT) {
429
+
mce_err->error_type = MCE_ERROR_TYPE_LINK;
430
+
mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT;
431
+
} else if (dsisr & P9_DSISR_MC_ERAT_MULTIHIT) {
432
+
mce_err->error_type = MCE_ERROR_TYPE_ERAT;
433
+
mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
434
+
} else if (dsisr & P9_DSISR_MC_TLB_MULTIHIT_MFTLB) {
435
+
mce_err->error_type = MCE_ERROR_TYPE_TLB;
436
+
mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
437
+
} else if (dsisr & P9_DSISR_MC_USER_TLBIE) {
438
+
mce_err->error_type = MCE_ERROR_TYPE_USER;
439
+
mce_err->u.user_error_type = MCE_USER_ERROR_TLBIE;
440
+
} else if (dsisr & P9_DSISR_MC_SLB_PARITY_MFSLB) {
441
+
mce_err->error_type = MCE_ERROR_TYPE_SLB;
442
+
mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
443
+
} else if (dsisr & P9_DSISR_MC_SLB_MULTIHIT_MFSLB) {
444
+
mce_err->error_type = MCE_ERROR_TYPE_SLB;
445
+
mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
446
+
} else if (dsisr & P9_DSISR_MC_RA_LOAD) {
447
+
mce_err->error_type = MCE_ERROR_TYPE_RA;
448
+
mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD;
449
+
} else if (dsisr & P9_DSISR_MC_RA_TABLEWALK) {
450
+
mce_err->error_type = MCE_ERROR_TYPE_RA;
451
+
mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
452
+
} else if (dsisr & P9_DSISR_MC_RA_TABLEWALK_FOREIGN) {
453
+
mce_err->error_type = MCE_ERROR_TYPE_RA;
454
+
mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN;
455
+
} else if (dsisr & P9_DSISR_MC_RA_FOREIGN) {
456
+
mce_err->error_type = MCE_ERROR_TYPE_RA;
457
+
mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD_STORE_FOREIGN;
458
+
}
459
+
}
460
+
461
+
static void mce_get_ierror_p9(struct pt_regs *regs,
462
+
struct mce_error_info *mce_err, uint64_t *addr)
463
+
{
464
+
uint64_t srr1 = regs->msr;
465
+
466
+
switch (P9_SRR1_MC_IFETCH(srr1)) {
467
+
case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
468
+
case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
469
+
mce_err->severity = MCE_SEV_FATAL;
470
+
break;
471
+
default:
472
+
mce_err->severity = MCE_SEV_ERROR_SYNC;
473
+
break;
474
+
}
475
+
476
+
mce_err->initiator = MCE_INITIATOR_CPU;
477
+
478
+
*addr = regs->nip;
479
+
480
+
switch (P9_SRR1_MC_IFETCH(srr1)) {
481
+
case P9_SRR1_MC_IFETCH_UE:
482
+
mce_err->error_type = MCE_ERROR_TYPE_UE;
483
+
mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH;
484
+
break;
485
+
case P9_SRR1_MC_IFETCH_SLB_PARITY:
486
+
mce_err->error_type = MCE_ERROR_TYPE_SLB;
487
+
mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
488
+
break;
489
+
case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
490
+
mce_err->error_type = MCE_ERROR_TYPE_SLB;
491
+
mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
492
+
break;
493
+
case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
494
+
mce_err->error_type = MCE_ERROR_TYPE_ERAT;
495
+
mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
496
+
break;
497
+
case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
498
+
mce_err->error_type = MCE_ERROR_TYPE_TLB;
499
+
mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
500
+
break;
501
+
case P9_SRR1_MC_IFETCH_UE_TLB_RELOAD:
502
+
mce_err->error_type = MCE_ERROR_TYPE_UE;
503
+
mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH;
504
+
break;
505
+
case P9_SRR1_MC_IFETCH_LINK_TIMEOUT:
506
+
mce_err->error_type = MCE_ERROR_TYPE_LINK;
507
+
mce_err->u.link_error_type = MCE_LINK_ERROR_IFETCH_TIMEOUT;
508
+
break;
509
+
case P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT:
510
+
mce_err->error_type = MCE_ERROR_TYPE_LINK;
511
+
mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT;
512
+
break;
513
+
case P9_SRR1_MC_IFETCH_RA:
514
+
mce_err->error_type = MCE_ERROR_TYPE_RA;
515
+
mce_err->u.ra_error_type = MCE_RA_ERROR_IFETCH;
516
+
break;
517
+
case P9_SRR1_MC_IFETCH_RA_TABLEWALK:
518
+
mce_err->error_type = MCE_ERROR_TYPE_RA;
519
+
mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH;
520
+
break;
521
+
case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
522
+
mce_err->error_type = MCE_ERROR_TYPE_RA;
523
+
mce_err->u.ra_error_type = MCE_RA_ERROR_STORE;
524
+
break;
525
+
case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
526
+
mce_err->error_type = MCE_ERROR_TYPE_LINK;
527
+
mce_err->u.link_error_type = MCE_LINK_ERROR_STORE_TIMEOUT;
528
+
break;
529
+
case P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN:
530
+
mce_err->error_type = MCE_ERROR_TYPE_RA;
531
+
mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN;
532
+
break;
533
+
default:
534
+
break;
535
+
}
536
+
}
537
+
538
+
long __machine_check_early_realmode_p9(struct pt_regs *regs)
539
+
{
540
+
uint64_t nip, addr;
541
+
long handled;
542
+
struct mce_error_info mce_error_info = { 0 };
543
+
544
+
nip = regs->nip;
545
+
546
+
if (P9_SRR1_MC_LOADSTORE(regs->msr)) {
547
+
handled = mce_handle_derror_p9(regs);
548
+
mce_get_derror_p9(regs, &mce_error_info, &addr);
549
+
} else {
550
+
handled = mce_handle_ierror_p9(regs);
551
+
mce_get_ierror_p9(regs, &mce_error_info, &addr);
417
552
}
418
553
419
554
/* Handle UE error. */
+2
arch/powerpc/perf/core-book3s.c
+2
arch/powerpc/perf/core-book3s.c
+36
-7
arch/powerpc/perf/isa207-common.c
+36
-7
arch/powerpc/perf/isa207-common.c
···
65
65
return !(event & ~valid_mask);
66
66
}
67
67
68
-
static u64 mmcra_sdar_mode(u64 event)
68
+
static inline bool is_event_marked(u64 event)
69
69
{
70
-
if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1))
71
-
return p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
70
+
if (event & EVENT_IS_MARKED)
71
+
return true;
72
72
73
-
return MMCRA_SDAR_MODE_TLB;
73
+
return false;
74
+
}
75
+
76
+
static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
77
+
{
78
+
/*
79
+
* MMCRA[SDAR_MODE] specifices how the SDAR should be updated in
80
+
* continous sampling mode.
81
+
*
82
+
* Incase of Power8:
83
+
* MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling
84
+
* mode and will be un-changed when setting MMCRA[63] (Marked events).
85
+
*
86
+
* Incase of Power9:
87
+
* Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'),
88
+
* or if group already have any marked events.
89
+
* Non-Marked events (for DD1):
90
+
* MMCRA[SDAR_MODE] will be set to 0b01
91
+
* For rest
92
+
* MMCRA[SDAR_MODE] will be set from event code.
93
+
*/
94
+
if (cpu_has_feature(CPU_FTR_ARCH_300)) {
95
+
if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
96
+
*mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
97
+
else if (!cpu_has_feature(CPU_FTR_POWER9_DD1))
98
+
*mmcra |= p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
99
+
else if (cpu_has_feature(CPU_FTR_POWER9_DD1))
100
+
*mmcra |= MMCRA_SDAR_MODE_TLB;
101
+
} else
102
+
*mmcra |= MMCRA_SDAR_MODE_TLB;
74
103
}
75
104
76
105
static u64 thresh_cmp_val(u64 value)
···
209
180
value |= CNST_L1_QUAL_VAL(cache);
210
181
}
211
182
212
-
if (event & EVENT_IS_MARKED) {
183
+
if (is_event_marked(event)) {
213
184
mask |= CNST_SAMPLE_MASK;
214
185
value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
215
186
}
···
305
276
}
306
277
307
278
/* In continuous sampling mode, update SDAR on TLB miss */
308
-
mmcra |= mmcra_sdar_mode(event[i]);
279
+
mmcra_sdar_mode(event[i], &mmcra);
309
280
310
281
if (event[i] & EVENT_IS_L1) {
311
282
cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
···
314
285
mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT;
315
286
}
316
287
317
-
if (event[i] & EVENT_IS_MARKED) {
288
+
if (is_event_marked(event[i])) {
318
289
mmcra |= MMCRA_SAMPLE_ENABLE;
319
290
320
291
val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
+1
arch/powerpc/perf/isa207-common.h
+1
arch/powerpc/perf/isa207-common.h
···
246
246
#define MMCRA_THR_CMP_SHIFT 32
247
247
#define MMCRA_SDAR_MODE_SHIFT 42
248
248
#define MMCRA_SDAR_MODE_TLB (1ull << MMCRA_SDAR_MODE_SHIFT)
249
+
#define MMCRA_SDAR_MODE_NO_UPDATES ~(0x3ull << MMCRA_SDAR_MODE_SHIFT)
249
250
#define MMCRA_IFM_SHIFT 30
250
251
251
252
/* MMCR1 Threshold Compare bit constant for power9 */
+6
-15
arch/powerpc/platforms/powernv/opal.c
+6
-15
arch/powerpc/platforms/powernv/opal.c
···
395
395
struct machine_check_event *evt)
396
396
{
397
397
int recovered = 0;
398
-
uint64_t ea = get_mce_fault_addr(evt);
399
398
400
399
if (!(regs->msr & MSR_RI)) {
401
400
/* If MSR_RI isn't set, we cannot recover */
···
403
404
} else if (evt->disposition == MCE_DISPOSITION_RECOVERED) {
404
405
/* Platform corrected itself */
405
406
recovered = 1;
406
-
} else if (ea && !is_kernel_addr(ea)) {
407
+
} else if (evt->severity == MCE_SEV_FATAL) {
408
+
/* Fatal machine check */
409
+
pr_err("Machine check interrupt is fatal\n");
410
+
recovered = 0;
411
+
} else if ((evt->severity == MCE_SEV_ERROR_SYNC) &&
412
+
(user_mode(regs) && !is_global_init(current))) {
407
413
/*
408
-
* Faulting address is not in kernel text. We should be fine.
409
-
* We need to find which process uses this address.
410
414
* For now, kill the task if we have received exception when
411
415
* in userspace.
412
416
*
413
417
* TODO: Queue up this address for hwpoisioning later.
414
-
*/
415
-
if (user_mode(regs) && !is_global_init(current)) {
416
-
_exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
417
-
recovered = 1;
418
-
} else
419
-
recovered = 0;
420
-
} else if (user_mode(regs) && !is_global_init(current) &&
421
-
evt->severity == MCE_SEV_ERROR_SYNC) {
422
-
/*
423
-
* If we have received a synchronous error when in userspace
424
-
* kill the task.
425
418
*/
426
419
_exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
427
420
recovered = 1;
+15
-5
arch/powerpc/platforms/powernv/pci-ioda.c
+15
-5
arch/powerpc/platforms/powernv/pci-ioda.c
···
1775
1775
}
1776
1776
1777
1777
static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1778
-
struct pci_bus *bus)
1778
+
struct pci_bus *bus,
1779
+
bool add_to_group)
1779
1780
{
1780
1781
struct pci_dev *dev;
1781
1782
1782
1783
list_for_each_entry(dev, &bus->devices, bus_list) {
1783
1784
set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1784
1785
set_dma_offset(&dev->dev, pe->tce_bypass_base);
1785
-
iommu_add_device(&dev->dev);
1786
+
if (add_to_group)
1787
+
iommu_add_device(&dev->dev);
1786
1788
1787
1789
if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1788
-
pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1790
+
pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1791
+
add_to_group);
1789
1792
}
1790
1793
}
1791
1794
···
2194
2191
set_iommu_table_base(&pe->pdev->dev, tbl);
2195
2192
iommu_add_device(&pe->pdev->dev);
2196
2193
} else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2197
-
pnv_ioda_setup_bus_dma(pe, pe->pbus);
2194
+
pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2198
2195
2199
2196
return;
2200
2197
fail:
···
2429
2426
2430
2427
pnv_pci_ioda2_set_bypass(pe, false);
2431
2428
pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2429
+
if (pe->pbus)
2430
+
pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2432
2431
pnv_ioda2_table_free(tbl);
2433
2432
}
2434
2433
···
2440
2435
table_group);
2441
2436
2442
2437
pnv_pci_ioda2_setup_default_config(pe);
2438
+
if (pe->pbus)
2439
+
pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2443
2440
}
2444
2441
2445
2442
static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
···
2631
2624
level_shift = entries_shift + 3;
2632
2625
level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2633
2626
2627
+
if ((level_shift - 3) * levels + page_shift >= 60)
2628
+
return -EINVAL;
2629
+
2634
2630
/* Allocate TCE table */
2635
2631
addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2636
2632
levels, tce_table_size, &offset, &total_allocated);
···
2738
2728
if (pe->flags & PNV_IODA_PE_DEV)
2739
2729
iommu_add_device(&pe->pdev->dev);
2740
2730
else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2741
-
pnv_ioda_setup_bus_dma(pe, pe->pbus);
2731
+
pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2742
2732
}
2743
2733
2744
2734
#ifdef CONFIG_PCI_MSI
+1
drivers/macintosh/macio_asic.c
+1
drivers/macintosh/macio_asic.c
+24
-24
tools/testing/selftests/powerpc/include/vsx_asm.h
+24
-24
tools/testing/selftests/powerpc/include/vsx_asm.h
···
16
16
*/
17
17
FUNC_START(load_vsx)
18
18
li r5,0
19
-
lxvx vs20,r5,r3
19
+
lxvd2x vs20,r5,r3
20
20
addi r5,r5,16
21
-
lxvx vs21,r5,r3
21
+
lxvd2x vs21,r5,r3
22
22
addi r5,r5,16
23
-
lxvx vs22,r5,r3
23
+
lxvd2x vs22,r5,r3
24
24
addi r5,r5,16
25
-
lxvx vs23,r5,r3
25
+
lxvd2x vs23,r5,r3
26
26
addi r5,r5,16
27
-
lxvx vs24,r5,r3
27
+
lxvd2x vs24,r5,r3
28
28
addi r5,r5,16
29
-
lxvx vs25,r5,r3
29
+
lxvd2x vs25,r5,r3
30
30
addi r5,r5,16
31
-
lxvx vs26,r5,r3
31
+
lxvd2x vs26,r5,r3
32
32
addi r5,r5,16
33
-
lxvx vs27,r5,r3
33
+
lxvd2x vs27,r5,r3
34
34
addi r5,r5,16
35
-
lxvx vs28,r5,r3
35
+
lxvd2x vs28,r5,r3
36
36
addi r5,r5,16
37
-
lxvx vs29,r5,r3
37
+
lxvd2x vs29,r5,r3
38
38
addi r5,r5,16
39
-
lxvx vs30,r5,r3
39
+
lxvd2x vs30,r5,r3
40
40
addi r5,r5,16
41
-
lxvx vs31,r5,r3
41
+
lxvd2x vs31,r5,r3
42
42
blr
43
43
FUNC_END(load_vsx)
44
44
45
45
FUNC_START(store_vsx)
46
46
li r5,0
47
-
stxvx vs20,r5,r3
47
+
stxvd2x vs20,r5,r3
48
48
addi r5,r5,16
49
-
stxvx vs21,r5,r3
49
+
stxvd2x vs21,r5,r3
50
50
addi r5,r5,16
51
-
stxvx vs22,r5,r3
51
+
stxvd2x vs22,r5,r3
52
52
addi r5,r5,16
53
-
stxvx vs23,r5,r3
53
+
stxvd2x vs23,r5,r3
54
54
addi r5,r5,16
55
-
stxvx vs24,r5,r3
55
+
stxvd2x vs24,r5,r3
56
56
addi r5,r5,16
57
-
stxvx vs25,r5,r3
57
+
stxvd2x vs25,r5,r3
58
58
addi r5,r5,16
59
-
stxvx vs26,r5,r3
59
+
stxvd2x vs26,r5,r3
60
60
addi r5,r5,16
61
-
stxvx vs27,r5,r3
61
+
stxvd2x vs27,r5,r3
62
62
addi r5,r5,16
63
-
stxvx vs28,r5,r3
63
+
stxvd2x vs28,r5,r3
64
64
addi r5,r5,16
65
-
stxvx vs29,r5,r3
65
+
stxvd2x vs29,r5,r3
66
66
addi r5,r5,16
67
-
stxvx vs30,r5,r3
67
+
stxvd2x vs30,r5,r3
68
68
addi r5,r5,16
69
-
stxvx vs31,r5,r3
69
+
stxvd2x vs31,r5,r3
70
70
blr
71
71
FUNC_END(store_vsx)