tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: sunxi-ng: r40: Allow setting parent rate to display related clocks

Display related peripherals need precise clocks to operate correctly.

Allow DE2, TCONs and HDMI to set parent clock.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

authored by

Jernej Skrabec and committed by
Maxime Ripard fb4aa0f6 24a95f75

+8 -4
+8 -4
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
··· 656 656 657 657 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; 658 658 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 659 - 0x104, 0, 4, 24, 3, BIT(31), 0); 659 + 0x104, 0, 4, 24, 3, BIT(31), 660 + CLK_SET_RATE_PARENT); 660 661 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents, 661 662 0x108, 0, 4, 24, 3, BIT(31), 0); 662 663 ··· 669 668 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents, 670 669 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT); 671 670 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents, 672 - 0x118, 0, 4, 24, 3, BIT(31), 0); 671 + 0x118, 0, 4, 24, 3, BIT(31), 672 + CLK_SET_RATE_PARENT); 673 673 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents, 674 - 0x11c, 0, 4, 24, 3, BIT(31), 0); 674 + 0x11c, 0, 4, 24, 3, BIT(31), 675 + CLK_SET_RATE_PARENT); 675 676 676 677 static const char * const deinterlace_parents[] = { "pll-periph0", 677 678 "pll-periph1" }; ··· 703 700 704 701 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; 705 702 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 706 - 0x150, 0, 4, 24, 2, BIT(31), 0); 703 + 0x150, 0, 4, 24, 2, BIT(31), 704 + CLK_SET_RATE_PARENT); 707 705 708 706 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 709 707 0x154, BIT(31), 0);