tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

pinctrl: sunxi: v3s: introduce support for V3

Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Link: https://lore.kernel.org/r/20190728031227.49140-2-icenowy@aosc.io
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Icenowy Zheng and committed by
Linus Walleij fb18f188 6161dc03

+262 -5
+260 -5
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
··· 1 1 /* 2 - * Allwinner V3s SoCs pinctrl driver. 2 + * Allwinner V3/V3s SoCs pinctrl driver. 3 3 * 4 4 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> 5 5 * ··· 77 77 SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ 78 78 SUNXI_FUNCTION(0x3, "uart0"), /* RX */ 79 79 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ 80 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 10), 81 + PINCTRL_SUN8I_V3, 82 + SUNXI_FUNCTION(0x0, "gpio_in"), 83 + SUNXI_FUNCTION(0x1, "gpio_out"), 84 + SUNXI_FUNCTION(0x2, "jtag"), /* MS */ 85 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */ 86 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11), 87 + PINCTRL_SUN8I_V3, 88 + SUNXI_FUNCTION(0x0, "gpio_in"), 89 + SUNXI_FUNCTION(0x1, "gpio_out"), 90 + SUNXI_FUNCTION(0x2, "jtag"), /* CK */ 91 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PB_EINT11 */ 92 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12), 93 + PINCTRL_SUN8I_V3, 94 + SUNXI_FUNCTION(0x0, "gpio_in"), 95 + SUNXI_FUNCTION(0x1, "gpio_out"), 96 + SUNXI_FUNCTION(0x2, "jtag"), /* DO */ 97 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PB_EINT12 */ 98 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13), 99 + PINCTRL_SUN8I_V3, 100 + SUNXI_FUNCTION(0x0, "gpio_in"), 101 + SUNXI_FUNCTION(0x1, "gpio_out"), 102 + SUNXI_FUNCTION(0x2, "jtag"), /* DI */ 103 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PB_EINT13 */ 80 104 /* Hole */ 81 105 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 82 106 SUNXI_FUNCTION(0x0, "gpio_in"), ··· 122 98 SUNXI_FUNCTION(0x1, "gpio_out"), 123 99 SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */ 124 100 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 101 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 4), 102 + PINCTRL_SUN8I_V3, 103 + SUNXI_FUNCTION(0x0, "gpio_in"), 104 + SUNXI_FUNCTION(0x1, "gpio_out"), 105 + SUNXI_FUNCTION(0x2, "mmc2")), /* D1 */ 106 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 5), 107 + PINCTRL_SUN8I_V3, 108 + SUNXI_FUNCTION(0x0, "gpio_in"), 109 + SUNXI_FUNCTION(0x1, "gpio_out"), 110 + SUNXI_FUNCTION(0x2, "mmc2")), /* D2 */ 111 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6), 112 + PINCTRL_SUN8I_V3, 113 + SUNXI_FUNCTION(0x0, "gpio_in"), 114 + SUNXI_FUNCTION(0x1, "gpio_out"), 115 + SUNXI_FUNCTION(0x2, "mmc2")), /* D3 */ 116 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7), 117 + PINCTRL_SUN8I_V3, 118 + SUNXI_FUNCTION(0x0, "gpio_in"), 119 + SUNXI_FUNCTION(0x1, "gpio_out"), 120 + SUNXI_FUNCTION(0x2, "mmc2")), /* D4 */ 121 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8), 122 + PINCTRL_SUN8I_V3, 123 + SUNXI_FUNCTION(0x0, "gpio_in"), 124 + SUNXI_FUNCTION(0x1, "gpio_out"), 125 + SUNXI_FUNCTION(0x2, "mmc2")), /* D5 */ 126 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9), 127 + PINCTRL_SUN8I_V3, 128 + SUNXI_FUNCTION(0x0, "gpio_in"), 129 + SUNXI_FUNCTION(0x1, "gpio_out"), 130 + SUNXI_FUNCTION(0x2, "mmc2")), /* D6 */ 131 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10), 132 + PINCTRL_SUN8I_V3, 133 + SUNXI_FUNCTION(0x0, "gpio_in"), 134 + SUNXI_FUNCTION(0x1, "gpio_out"), 135 + SUNXI_FUNCTION(0x2, "mmc2")), /* D7 */ 136 + /* Hole */ 137 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0), 138 + PINCTRL_SUN8I_V3, 139 + SUNXI_FUNCTION(0x0, "gpio_in"), 140 + SUNXI_FUNCTION(0x1, "gpio_out"), 141 + SUNXI_FUNCTION(0x2, "lcd"), /* D2 */ 142 + SUNXI_FUNCTION(0x4, "emac")), /* RXD3 */ 143 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1), 144 + PINCTRL_SUN8I_V3, 145 + SUNXI_FUNCTION(0x0, "gpio_in"), 146 + SUNXI_FUNCTION(0x1, "gpio_out"), 147 + SUNXI_FUNCTION(0x2, "lcd"), /* D3 */ 148 + SUNXI_FUNCTION(0x4, "emac")), /* RXD2 */ 149 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 2), 150 + PINCTRL_SUN8I_V3, 151 + SUNXI_FUNCTION(0x0, "gpio_in"), 152 + SUNXI_FUNCTION(0x1, "gpio_out"), 153 + SUNXI_FUNCTION(0x2, "lcd"), /* D4 */ 154 + SUNXI_FUNCTION(0x4, "emac")), /* RXD1 */ 155 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 3), 156 + PINCTRL_SUN8I_V3, 157 + SUNXI_FUNCTION(0x0, "gpio_in"), 158 + SUNXI_FUNCTION(0x1, "gpio_out"), 159 + SUNXI_FUNCTION(0x2, "lcd"), /* D5 */ 160 + SUNXI_FUNCTION(0x4, "emac")), /* RXD0 */ 161 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 4), 162 + PINCTRL_SUN8I_V3, 163 + SUNXI_FUNCTION(0x0, "gpio_in"), 164 + SUNXI_FUNCTION(0x1, "gpio_out"), 165 + SUNXI_FUNCTION(0x2, "lcd"), /* D6 */ 166 + SUNXI_FUNCTION(0x4, "emac")), /* RXCK */ 167 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 5), 168 + PINCTRL_SUN8I_V3, 169 + SUNXI_FUNCTION(0x0, "gpio_in"), 170 + SUNXI_FUNCTION(0x1, "gpio_out"), 171 + SUNXI_FUNCTION(0x2, "lcd"), /* D7 */ 172 + SUNXI_FUNCTION(0x4, "emac")), /* RXCTL/RXDV */ 173 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 6), 174 + PINCTRL_SUN8I_V3, 175 + SUNXI_FUNCTION(0x0, "gpio_in"), 176 + SUNXI_FUNCTION(0x1, "gpio_out"), 177 + SUNXI_FUNCTION(0x2, "lcd"), /* D10 */ 178 + SUNXI_FUNCTION(0x4, "emac")), /* RXERR */ 179 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 7), 180 + PINCTRL_SUN8I_V3, 181 + SUNXI_FUNCTION(0x0, "gpio_in"), 182 + SUNXI_FUNCTION(0x1, "gpio_out"), 183 + SUNXI_FUNCTION(0x2, "lcd"), /* D11 */ 184 + SUNXI_FUNCTION(0x4, "emac")), /* TXD3 */ 185 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8), 186 + PINCTRL_SUN8I_V3, 187 + SUNXI_FUNCTION(0x0, "gpio_in"), 188 + SUNXI_FUNCTION(0x1, "gpio_out"), 189 + SUNXI_FUNCTION(0x2, "lcd"), /* D12 */ 190 + SUNXI_FUNCTION(0x4, "emac")), /* TXD2 */ 191 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9), 192 + PINCTRL_SUN8I_V3, 193 + SUNXI_FUNCTION(0x0, "gpio_in"), 194 + SUNXI_FUNCTION(0x1, "gpio_out"), 195 + SUNXI_FUNCTION(0x2, "lcd"), /* D13 */ 196 + SUNXI_FUNCTION(0x4, "emac")), /* TXD1 */ 197 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 10), 198 + PINCTRL_SUN8I_V3, 199 + SUNXI_FUNCTION(0x0, "gpio_in"), 200 + SUNXI_FUNCTION(0x1, "gpio_out"), 201 + SUNXI_FUNCTION(0x2, "lcd"), /* D14 */ 202 + SUNXI_FUNCTION(0x4, "emac")), /* TXD0 */ 203 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 11), 204 + PINCTRL_SUN8I_V3, 205 + SUNXI_FUNCTION(0x0, "gpio_in"), 206 + SUNXI_FUNCTION(0x1, "gpio_out"), 207 + SUNXI_FUNCTION(0x2, "lcd"), /* D15 */ 208 + SUNXI_FUNCTION(0x4, "emac")), /* CRS */ 209 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 12), 210 + PINCTRL_SUN8I_V3, 211 + SUNXI_FUNCTION(0x0, "gpio_in"), 212 + SUNXI_FUNCTION(0x1, "gpio_out"), 213 + SUNXI_FUNCTION(0x2, "lcd"), /* D18 */ 214 + SUNXI_FUNCTION(0x3, "lvds"), /* VP0 */ 215 + SUNXI_FUNCTION(0x4, "emac")), /* TXCK */ 216 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 13), 217 + PINCTRL_SUN8I_V3, 218 + SUNXI_FUNCTION(0x0, "gpio_in"), 219 + SUNXI_FUNCTION(0x1, "gpio_out"), 220 + SUNXI_FUNCTION(0x2, "lcd"), /* D19 */ 221 + SUNXI_FUNCTION(0x3, "lvds"), /* VN0 */ 222 + SUNXI_FUNCTION(0x4, "emac")), /* TXCTL/TXEN */ 223 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 14), 224 + PINCTRL_SUN8I_V3, 225 + SUNXI_FUNCTION(0x0, "gpio_in"), 226 + SUNXI_FUNCTION(0x1, "gpio_out"), 227 + SUNXI_FUNCTION(0x2, "lcd"), /* D20 */ 228 + SUNXI_FUNCTION(0x3, "lvds"), /* VP1 */ 229 + SUNXI_FUNCTION(0x4, "emac")), /* TXERR */ 230 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 15), 231 + PINCTRL_SUN8I_V3, 232 + SUNXI_FUNCTION(0x0, "gpio_in"), 233 + SUNXI_FUNCTION(0x1, "gpio_out"), 234 + SUNXI_FUNCTION(0x2, "lcd"), /* D21 */ 235 + SUNXI_FUNCTION(0x3, "lvds"), /* VN1 */ 236 + SUNXI_FUNCTION(0x4, "emac")), /* CLKIN/COL */ 237 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16), 238 + PINCTRL_SUN8I_V3, 239 + SUNXI_FUNCTION(0x0, "gpio_in"), 240 + SUNXI_FUNCTION(0x1, "gpio_out"), 241 + SUNXI_FUNCTION(0x2, "lcd"), /* D22 */ 242 + SUNXI_FUNCTION(0x3, "lvds"), /* VP2 */ 243 + SUNXI_FUNCTION(0x4, "emac")), /* MDC */ 244 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17), 245 + PINCTRL_SUN8I_V3, 246 + SUNXI_FUNCTION(0x0, "gpio_in"), 247 + SUNXI_FUNCTION(0x1, "gpio_out"), 248 + SUNXI_FUNCTION(0x2, "lcd"), /* D23 */ 249 + SUNXI_FUNCTION(0x3, "lvds"), /* VN2 */ 250 + SUNXI_FUNCTION(0x4, "emac")), /* MDIO */ 251 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 18), 252 + PINCTRL_SUN8I_V3, 253 + SUNXI_FUNCTION(0x0, "gpio_in"), 254 + SUNXI_FUNCTION(0x1, "gpio_out"), 255 + SUNXI_FUNCTION(0x2, "lcd"), /* CLK */ 256 + SUNXI_FUNCTION(0x3, "lvds")), /* VPC */ 257 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 19), 258 + PINCTRL_SUN8I_V3, 259 + SUNXI_FUNCTION(0x0, "gpio_in"), 260 + SUNXI_FUNCTION(0x1, "gpio_out"), 261 + SUNXI_FUNCTION(0x2, "lcd"), /* DE */ 262 + SUNXI_FUNCTION(0x3, "lvds")), /* VNC */ 263 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 20), 264 + PINCTRL_SUN8I_V3, 265 + SUNXI_FUNCTION(0x0, "gpio_in"), 266 + SUNXI_FUNCTION(0x1, "gpio_out"), 267 + SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */ 268 + SUNXI_FUNCTION(0x3, "lvds")), /* VP3 */ 269 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 21), 270 + PINCTRL_SUN8I_V3, 271 + SUNXI_FUNCTION(0x0, "gpio_in"), 272 + SUNXI_FUNCTION(0x1, "gpio_out"), 273 + SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */ 274 + SUNXI_FUNCTION(0x3, "lvds")), /* VN3 */ 125 275 /* Hole */ 126 276 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), 127 277 SUNXI_FUNCTION(0x0, "gpio_in"), ··· 489 291 SUNXI_FUNCTION(0x1, "gpio_out"), 490 292 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 491 293 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ 294 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6), 295 + PINCTRL_SUN8I_V3, 296 + SUNXI_FUNCTION(0x0, "gpio_in"), 297 + SUNXI_FUNCTION(0x1, "gpio_out"), 298 + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ 299 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ 300 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7), 301 + PINCTRL_SUN8I_V3, 302 + SUNXI_FUNCTION(0x0, "gpio_in"), 303 + SUNXI_FUNCTION(0x1, "gpio_out"), 304 + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ 305 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ 306 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8), 307 + PINCTRL_SUN8I_V3, 308 + SUNXI_FUNCTION(0x0, "gpio_in"), 309 + SUNXI_FUNCTION(0x1, "gpio_out"), 310 + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ 311 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ 312 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 9), 313 + PINCTRL_SUN8I_V3, 314 + SUNXI_FUNCTION(0x0, "gpio_in"), 315 + SUNXI_FUNCTION(0x1, "gpio_out"), 316 + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ 317 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ 318 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 10), 319 + PINCTRL_SUN8I_V3, 320 + SUNXI_FUNCTION(0x0, "gpio_in"), 321 + SUNXI_FUNCTION(0x1, "gpio_out"), 322 + SUNXI_FUNCTION(0x2, "i2s"), /* SYNC */ 323 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ 324 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 11), 325 + PINCTRL_SUN8I_V3, 326 + SUNXI_FUNCTION(0x0, "gpio_in"), 327 + SUNXI_FUNCTION(0x1, "gpio_out"), 328 + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ 329 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ 330 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 12), 331 + PINCTRL_SUN8I_V3, 332 + SUNXI_FUNCTION(0x0, "gpio_in"), 333 + SUNXI_FUNCTION(0x1, "gpio_out"), 334 + SUNXI_FUNCTION(0x2, "i2s"), /* DOUT */ 335 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ 336 + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13), 337 + PINCTRL_SUN8I_V3, 338 + SUNXI_FUNCTION(0x0, "gpio_in"), 339 + SUNXI_FUNCTION(0x1, "gpio_out"), 340 + SUNXI_FUNCTION(0x2, "i2s"), /* DIN */ 341 + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ 492 342 }; 493 343 494 344 static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 }; ··· 551 305 552 306 static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev) 553 307 { 554 - return sunxi_pinctrl_init(pdev, 555 - &sun8i_v3s_pinctrl_data); 308 + unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); 309 + 310 + return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v3s_pinctrl_data, 311 + variant); 556 312 } 557 313 558 314 static const struct of_device_id sun8i_v3s_pinctrl_match[] = { 559 - { .compatible = "allwinner,sun8i-v3s-pinctrl", }, 560 - {} 315 + { 316 + .compatible = "allwinner,sun8i-v3-pinctrl", 317 + .data = (void *)PINCTRL_SUN8I_V3 318 + }, 319 + { 320 + .compatible = "allwinner,sun8i-v3s-pinctrl", 321 + .data = (void *)PINCTRL_SUN8I_V3S 322 + }, 323 + { }, 561 324 }; 562 325 563 326 static struct platform_driver sun8i_v3s_pinctrl_driver = {
+2
drivers/pinctrl/sunxi/pinctrl-sunxi.h
··· 94 94 #define PINCTRL_SUN4I_A10 BIT(6) 95 95 #define PINCTRL_SUN7I_A20 BIT(7) 96 96 #define PINCTRL_SUN8I_R40 BIT(8) 97 + #define PINCTRL_SUN8I_V3 BIT(9) 98 + #define PINCTRL_SUN8I_V3S BIT(10) 97 99 98 100 #define PIO_POW_MOD_SEL_REG 0x340 99 101