ARM: at91: make smc register base soc independent

tjh.dev / kernel

fork atom

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

fork atom

ARM: at91: make smc register base soc independent

now sam9_smc_configure will take as first parameter is the SMC id

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Jean-Christophe PLAGNIOL-VILLARD 14 years ago faee0cc3 4ab0c599

+92 -62

33 changed files

expand all collapse all

arch

arm

mach-at91

at91cap9.c

at91rm9200.c

at91sam9260.c

at91sam9261.c

at91sam9263.c

at91sam9g45.c

at91sam9rl.c

board-cam60.c

board-cap9adk.c

board-cpu9krea.c

board-dt.c

board-neocore926.c

board-pcontrol-g20.c

board-qil-a9260.c

board-sam9-l9260.c

board-sam9260ek.c

board-sam9261ek.c

board-sam9263ek.c

board-sam9g20ek.c

board-sam9m10g45ek.c

board-sam9rlek.c

board-snapper9260.c

board-stamp9g20.c

board-usb-a926x.c

include

mach

at91cap9.h

at91sam9260.h

at91sam9261.h

at91sam9263.h

at91sam9_smc.h

at91sam9g45.h

at91sam9rl.h

sam9_smc.c

sam9_smc.h

arch/arm/mach-at91/at91cap9.c

reviewed

··· 28 28 #include "soc.h" 29 29 #include "generic.h" 30 30 #include "clock.h" 31 31 + #include "sam9_smc.h" 31 32 32 33 /* -------------------------------------------------------------------- 33 34 * Clocks ··· 337 336 static void __init at91cap9_ioremap_registers(void) 338 337 { 339 338 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); 339 339 + at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); 340 340 } 341 341 342 342 static void __init at91cap9_initialize(void)

arch/arm/mach-at91/at91rm9200.c

reviewed

··· 23 23 #include "soc.h" 24 24 #include "generic.h" 25 25 #include "clock.h" 26 26 + #include "sam9_smc.h" 26 27 27 28 static struct map_desc at91rm9200_io_desc[] __initdata = { 28 29 {

arch/arm/mach-at91/at91sam9260.c

reviewed

··· 26 26 #include "soc.h" 27 27 #include "generic.h" 28 28 #include "clock.h" 29 29 + #include "sam9_smc.h" 29 30 30 31 /* -------------------------------------------------------------------- 31 32 * Clocks ··· 329 328 static void __init at91sam9260_ioremap_registers(void) 330 329 { 331 330 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); 331 331 + at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); 332 332 } 333 333 334 334 static void __init at91sam9260_initialize(void)

arch/arm/mach-at91/at91sam9261.c

reviewed

··· 25 25 #include "soc.h" 26 26 #include "generic.h" 27 27 #include "clock.h" 28 28 + #include "sam9_smc.h" 28 29 29 30 /* -------------------------------------------------------------------- 30 31 * Clocks ··· 289 288 static void __init at91sam9261_ioremap_registers(void) 290 289 { 291 290 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); 291 291 + at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); 292 292 } 293 293 294 294 static void __init at91sam9261_initialize(void)

arch/arm/mach-at91/at91sam9263.c

reviewed

··· 24 24 #include "soc.h" 25 25 #include "generic.h" 26 26 #include "clock.h" 27 27 + #include "sam9_smc.h" 27 28 28 29 /* -------------------------------------------------------------------- 29 30 * Clocks ··· 307 306 static void __init at91sam9263_ioremap_registers(void) 308 307 { 309 308 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); 309 309 + at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); 310 310 + at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); 310 311 } 311 312 312 313 static void __init at91sam9263_initialize(void)

arch/arm/mach-at91/at91sam9g45.c

reviewed

··· 26 26 #include "soc.h" 27 27 #include "generic.h" 28 28 #include "clock.h" 29 29 + #include "sam9_smc.h" 29 30 30 31 /* -------------------------------------------------------------------- 31 32 * Clocks ··· 342 341 static void __init at91sam9g45_ioremap_registers(void) 343 342 { 344 343 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); 344 344 + at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); 345 345 } 346 346 347 347 static void __init at91sam9g45_initialize(void)

arch/arm/mach-at91/at91sam9rl.c

reviewed

··· 25 25 #include "soc.h" 26 26 #include "generic.h" 27 27 #include "clock.h" 28 28 + #include "sam9_smc.h" 28 29 29 30 /* -------------------------------------------------------------------- 30 31 * Clocks ··· 294 293 static void __init at91sam9rl_ioremap_registers(void) 295 294 { 296 295 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); 296 296 + at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); 297 297 } 298 298 299 299 static void __init at91sam9rl_initialize(void)

+1 -1

arch/arm/mach-at91/board-cam60.c

reviewed

··· 163 163 static void __init cam60_add_device_nand(void) 164 164 { 165 165 /* configure chip-select 3 (NAND) */ 166 166 - sam9_smc_configure(3, &cam60_nand_smc_config); 166 166 + sam9_smc_configure(0, 3, &cam60_nand_smc_config); 167 167 168 168 at91_add_device_nand(&cam60_nand_data); 169 169 }

+2 -2

arch/arm/mach-at91/board-cap9adk.c

reviewed

··· 212 212 cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8; 213 213 214 214 /* configure chip-select 3 (NAND) */ 215 215 - sam9_smc_configure(3, &cap9adk_nand_smc_config); 215 215 + sam9_smc_configure(0, 3, &cap9adk_nand_smc_config); 216 216 217 217 at91_add_device_nand(&cap9adk_nand_data); 218 218 } ··· 282 282 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V); 283 283 284 284 /* configure chip-select 0 (NOR) */ 285 285 - sam9_smc_configure(0, &cap9adk_nor_smc_config); 285 285 + sam9_smc_configure(0, 0, &cap9adk_nor_smc_config); 286 286 287 287 platform_device_register(&cap9adk_nor_flash); 288 288 }

+2 -2

arch/arm/mach-at91/board-cpu9krea.c

reviewed

··· 156 156 157 157 static void __init cpu9krea_add_device_nand(void) 158 158 { 159 159 - sam9_smc_configure(3, &cpu9krea_nand_smc_config); 159 159 + sam9_smc_configure(0, 3, &cpu9krea_nand_smc_config); 160 160 at91_add_device_nand(&cpu9krea_nand_data); 161 161 } 162 162 ··· 238 238 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V); 239 239 240 240 /* configure chip-select 0 (NOR) */ 241 241 - sam9_smc_configure(0, &cpu9krea_nor_smc_config); 241 241 + sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config); 242 242 243 243 platform_device_register(&cpu9krea_nor_flash); 244 244 }

+1 -1

arch/arm/mach-at91/board-dt.c

reviewed

··· 82 82 ek_nand_smc_config.mode |= AT91_SMC_DBW_8; 83 83 84 84 /* configure chip-select 3 (NAND) */ 85 85 - sam9_smc_configure(3, &ek_nand_smc_config); 85 85 + sam9_smc_configure(0, 3, &ek_nand_smc_config); 86 86 87 87 at91_add_device_nand(&ek_nand_data); 88 88 }

+1 -1

arch/arm/mach-at91/board-neocore926.c

reviewed

··· 213 213 static void __init neocore926_add_device_nand(void) 214 214 { 215 215 /* configure chip-select 3 (NAND) */ 216 216 - sam9_smc_configure(3, &neocore926_nand_smc_config); 216 216 + sam9_smc_configure(0, 3, &neocore926_nand_smc_config); 217 217 218 218 at91_add_device_nand(&neocore926_nand_data); 219 219 }

+2 -2

arch/arm/mach-at91/board-pcontrol-g20.c

reviewed

··· 96 96 static void __init add_device_pcontrol(void) 97 97 { 98 98 /* configure chip-select 4 (IO compatible to 8051 X4 ) */ 99 99 - sam9_smc_configure(4, &pcontrol_smc_config[0]); 99 99 + sam9_smc_configure(0, 4, &pcontrol_smc_config[0]); 100 100 /* configure chip-select 7 (FerroRAM 256KiBx16bit MR2A16A D4 ) */ 101 101 - sam9_smc_configure(7, &pcontrol_smc_config[1]); 101 101 + sam9_smc_configure(0, 7, &pcontrol_smc_config[1]); 102 102 } 103 103 104 104

+1 -1

arch/arm/mach-at91/board-qil-a9260.c

reviewed

··· 161 161 static void __init ek_add_device_nand(void) 162 162 { 163 163 /* configure chip-select 3 (NAND) */ 164 164 - sam9_smc_configure(3, &ek_nand_smc_config); 164 164 + sam9_smc_configure(0, 3, &ek_nand_smc_config); 165 165 166 166 at91_add_device_nand(&ek_nand_data); 167 167 }

+1 -1

arch/arm/mach-at91/board-sam9-l9260.c

reviewed

··· 162 162 static void __init ek_add_device_nand(void) 163 163 { 164 164 /* configure chip-select 3 (NAND) */ 165 165 - sam9_smc_configure(3, &ek_nand_smc_config); 165 165 + sam9_smc_configure(0, 3, &ek_nand_smc_config); 166 166 167 167 at91_add_device_nand(&ek_nand_data); 168 168 }

+1 -1

arch/arm/mach-at91/board-sam9260ek.c

reviewed

··· 211 211 ek_nand_smc_config.mode |= AT91_SMC_DBW_8; 212 212 213 213 /* configure chip-select 3 (NAND) */ 214 214 - sam9_smc_configure(3, &ek_nand_smc_config); 214 214 + sam9_smc_configure(0, 3, &ek_nand_smc_config); 215 215 216 216 at91_add_device_nand(&ek_nand_data); 217 217 }

+2 -2

arch/arm/mach-at91/board-sam9261ek.c

reviewed

··· 131 131 static void __init ek_add_device_dm9000(void) 132 132 { 133 133 /* Configure chip-select 2 (DM9000) */ 134 134 - sam9_smc_configure(2, &dm9000_smc_config); 134 134 + sam9_smc_configure(0, 2, &dm9000_smc_config); 135 135 136 136 /* Configure Reset signal as output */ 137 137 at91_set_gpio_output(AT91_PIN_PC10, 0); ··· 217 217 ek_nand_smc_config.mode |= AT91_SMC_DBW_8; 218 218 219 219 /* configure chip-select 3 (NAND) */ 220 220 - sam9_smc_configure(3, &ek_nand_smc_config); 220 220 + sam9_smc_configure(0, 3, &ek_nand_smc_config); 221 221 222 222 at91_add_device_nand(&ek_nand_data); 223 223 }

+1 -1

arch/arm/mach-at91/board-sam9263ek.c

reviewed

··· 218 218 ek_nand_smc_config.mode |= AT91_SMC_DBW_8; 219 219 220 220 /* configure chip-select 3 (NAND) */ 221 221 - sam9_smc_configure(3, &ek_nand_smc_config); 221 221 + sam9_smc_configure(0, 3, &ek_nand_smc_config); 222 222 223 223 at91_add_device_nand(&ek_nand_data); 224 224 }

+1 -1

arch/arm/mach-at91/board-sam9g20ek.c

reviewed

··· 195 195 ek_nand_smc_config.mode |= AT91_SMC_DBW_8; 196 196 197 197 /* configure chip-select 3 (NAND) */ 198 198 - sam9_smc_configure(3, &ek_nand_smc_config); 198 198 + sam9_smc_configure(0, 3, &ek_nand_smc_config); 199 199 200 200 at91_add_device_nand(&ek_nand_data); 201 201 }

+1 -1

arch/arm/mach-at91/board-sam9m10g45ek.c

reviewed

··· 175 175 ek_nand_smc_config.mode |= AT91_SMC_DBW_8; 176 176 177 177 /* configure chip-select 3 (NAND) */ 178 178 - sam9_smc_configure(3, &ek_nand_smc_config); 178 178 + sam9_smc_configure(0, 3, &ek_nand_smc_config); 179 179 180 180 at91_add_device_nand(&ek_nand_data); 181 181 }

+1 -1

arch/arm/mach-at91/board-sam9rlek.c

reviewed

··· 119 119 static void __init ek_add_device_nand(void) 120 120 { 121 121 /* configure chip-select 3 (NAND) */ 122 122 - sam9_smc_configure(3, &ek_nand_smc_config); 122 122 + sam9_smc_configure(0, 3, &ek_nand_smc_config); 123 123 124 124 at91_add_device_nand(&ek_nand_data); 125 125 }

+1 -1

arch/arm/mach-at91/board-snapper9260.c

reviewed

··· 149 149 static void __init snapper9260_add_device_nand(void) 150 150 { 151 151 at91_set_A_periph(AT91_PIN_PC14, 0); 152 152 - sam9_smc_configure(3, &snapper9260_nand_smc_config); 152 152 + sam9_smc_configure(0, 3, &snapper9260_nand_smc_config); 153 153 at91_add_device_nand(&snapper9260_nand_data); 154 154 } 155 155

+1 -1

arch/arm/mach-at91/board-stamp9g20.c

reviewed

··· 108 108 static void __init add_device_nand(void) 109 109 { 110 110 /* configure chip-select 3 (NAND) */ 111 111 - sam9_smc_configure(3, &nand_smc_config); 111 111 + sam9_smc_configure(0, 3, &nand_smc_config); 112 112 113 113 at91_add_device_nand(&nand_data); 114 114 }

+2 -2

arch/arm/mach-at91/board-usb-a926x.c

reviewed

··· 245 245 246 246 /* configure chip-select 3 (NAND) */ 247 247 if (machine_is_usb_a9g20()) 248 248 - sam9_smc_configure(3, &usb_a9g20_nand_smc_config); 248 248 + sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config); 249 249 else 250 250 - sam9_smc_configure(3, &usb_a9260_nand_smc_config); 250 250 + sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config); 251 251 252 252 at91_add_device_nand(&ek_nand_data); 253 253 }

+1 -1

arch/arm/mach-at91/include/mach/at91cap9.h

reviewed

··· 81 81 */ 82 82 #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) 83 83 #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 84 84 - #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) 85 84 #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 86 85 #define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) 87 86 #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) ··· 95 96 96 97 #define AT91CAP9_BASE_ECC 0xffffe200 97 98 #define AT91CAP9_BASE_DMA 0xffffec00 99 99 + #define AT91CAP9_BASE_SMC 0xffffe800 98 100 #define AT91CAP9_BASE_PIOA 0xfffff200 99 101 #define AT91CAP9_BASE_PIOB 0xfffff400 100 102 #define AT91CAP9_BASE_PIOC 0xfffff600

+1 -1

arch/arm/mach-at91/include/mach/at91sam9260.h

reviewed

··· 81 81 * System Peripherals (offset from AT91_BASE_SYS) 82 82 */ 83 83 #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 84 84 - #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 85 84 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 86 85 #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 87 86 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) ··· 92 93 #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 93 94 94 95 #define AT91SAM9260_BASE_ECC 0xffffe800 96 96 + #define AT91SAM9260_BASE_SMC 0xffffec00 95 97 #define AT91SAM9260_BASE_PIOA 0xfffff400 96 98 #define AT91SAM9260_BASE_PIOB 0xfffff600 97 99 #define AT91SAM9260_BASE_PIOC 0xfffff800

+1 -1

arch/arm/mach-at91/include/mach/at91sam9261.h

reviewed

··· 66 66 * System Peripherals (offset from AT91_BASE_SYS) 67 67 */ 68 68 #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 69 69 - #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 70 69 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 71 70 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 72 71 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) ··· 75 76 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 76 77 #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 77 78 79 79 + #define AT91SAM9261_BASE_SMC 0xffffec00 78 80 #define AT91SAM9261_BASE_PIOA 0xfffff400 79 81 #define AT91SAM9261_BASE_PIOB 0xfffff600 80 82 #define AT91SAM9261_BASE_PIOC 0xfffff800

+2 -2

arch/arm/mach-at91/include/mach/at91sam9263.h

reviewed

··· 75 75 * System Peripherals (offset from AT91_BASE_SYS) 76 76 */ 77 77 #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) 78 78 - #define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) 79 78 #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) 80 80 - #define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) 81 79 #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) 82 80 #define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) 83 81 #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) ··· 87 89 #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 88 90 89 91 #define AT91SAM9263_BASE_ECC0 0xffffe000 92 92 + #define AT91SAM9263_BASE_SMC0 0xffffe400 90 93 #define AT91SAM9263_BASE_ECC1 0xffffe600 94 94 + #define AT91SAM9263_BASE_SMC1 0xffffea00 91 95 #define AT91SAM9263_BASE_PIOA 0xfffff200 92 96 #define AT91SAM9263_BASE_PIOB 0xfffff400 93 97 #define AT91SAM9263_BASE_PIOC 0xfffff600

+6 -11

arch/arm/mach-at91/include/mach/at91sam9_smc.h

reviewed

··· 16 16 #ifndef AT91SAM9_SMC_H 17 17 #define AT91SAM9_SMC_H 18 18 19 19 - #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ 19 19 + #include <mach/cpu.h> 20 20 + 21 21 + #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ 20 22 #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ 21 23 #define AT91_SMC_NWESETUP_(x) ((x) << 0) 22 24 #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ ··· 28 26 #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ 29 27 #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) 30 28 31 31 - #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ 29 29 + #define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */ 32 30 #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ 33 31 #define AT91_SMC_NWEPULSE_(x) ((x) << 0) 34 32 #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ ··· 38 36 #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ 39 37 #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) 40 38 41 41 - #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ 39 39 + #define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */ 42 40 #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ 43 41 #define AT91_SMC_NWECYCLE_(x) ((x) << 0) 44 42 #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ 45 43 #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) 46 44 47 47 - #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ 45 45 + #define AT91_SMC_MODE 0x0c /* Mode Register for CS n */ 48 46 #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ 49 47 #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ 50 48 #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ ··· 67 65 #define AT91_SMC_PS_8 (1 << 28) 68 66 #define AT91_SMC_PS_16 (2 << 28) 69 67 #define AT91_SMC_PS_32 (3 << 28) 70 70 - 71 71 - #if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ 72 72 - #define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ 73 73 - #define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ 74 74 - #define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ 75 75 - #define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ 76 76 - #endif 77 68 78 69 #endif

+1 -1

arch/arm/mach-at91/include/mach/at91sam9g45.h

reviewed

··· 88 88 */ 89 89 #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) 90 90 #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 91 91 - #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) 92 91 #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 93 92 #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) 94 93 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) ··· 100 101 101 102 #define AT91SAM9G45_BASE_ECC 0xffffe200 102 103 #define AT91SAM9G45_BASE_DMA 0xffffec00 104 104 + #define AT91SAM9G45_BASE_SMC 0xffffe800 103 105 #define AT91SAM9G45_BASE_PIOA 0xfffff200 104 106 #define AT91SAM9G45_BASE_PIOB 0xfffff400 105 107 #define AT91SAM9G45_BASE_PIOC 0xfffff600

+1 -1

arch/arm/mach-at91/include/mach/at91sam9rl.h

reviewed

··· 70 70 * System Peripherals (offset from AT91_BASE_SYS) 71 71 */ 72 72 #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 73 73 - #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 74 73 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 75 74 #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 76 75 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) ··· 84 85 85 86 #define AT91SAM9RL_BASE_DMA 0xffffe600 86 87 #define AT91SAM9RL_BASE_ECC 0xffffe800 88 88 + #define AT91SAM9RL_BASE_SMC 0xffffec00 87 89 #define AT91SAM9RL_BASE_PIOA 0xfffff400 88 90 #define AT91SAM9RL_BASE_PIOB 0xfffff600 89 91 #define AT91SAM9RL_BASE_PIOC 0xfffff800

+41 -21

arch/arm/mach-at91/sam9_smc.c

reviewed

··· 10 10 11 11 #include <linux/module.h> 12 12 #include <linux/io.h> 13 13 + #include <linux/of.h> 14 14 + #include <linux/of_address.h> 13 15 14 16 #include <mach/at91sam9_smc.h> 15 17 16 18 #include "sam9_smc.h" 17 19 18 18 - void __init sam9_smc_configure(int cs, struct sam9_smc_config* config) 20 20 + 21 21 + #define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10)) 22 22 + 23 23 + static void __iomem *smc_base_addr[2]; 24 24 + 25 25 + static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config) 19 26 { 27 27 + 20 28 /* Setup register */ 21 21 - at91_sys_write(AT91_SMC_SETUP(cs), 22 22 - AT91_SMC_NWESETUP_(config->nwe_setup) 23 23 - | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) 24 24 - | AT91_SMC_NRDSETUP_(config->nrd_setup) 25 25 - | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup) 26 26 - ); 29 29 + __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup) 30 30 + | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) 31 31 + | AT91_SMC_NRDSETUP_(config->nrd_setup) 32 32 + | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup), 33 33 + base + AT91_SMC_SETUP); 27 34 28 35 /* Pulse register */ 29 29 - at91_sys_write(AT91_SMC_PULSE(cs), 30 30 - AT91_SMC_NWEPULSE_(config->nwe_pulse) 31 31 - | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) 32 32 - | AT91_SMC_NRDPULSE_(config->nrd_pulse) 33 33 - | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse) 34 34 - ); 36 36 + __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse) 37 37 + | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) 38 38 + | AT91_SMC_NRDPULSE_(config->nrd_pulse) 39 39 + | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse), 40 40 + base + AT91_SMC_PULSE); 35 41 36 42 /* Cycle register */ 37 37 - at91_sys_write(AT91_SMC_CYCLE(cs), 38 38 - AT91_SMC_NWECYCLE_(config->write_cycle) 39 39 - | AT91_SMC_NRDCYCLE_(config->read_cycle) 40 40 - ); 43 43 + __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle) 44 44 + | AT91_SMC_NRDCYCLE_(config->read_cycle), 45 45 + base + AT91_SMC_CYCLE); 41 46 42 47 /* Mode register */ 43 43 - at91_sys_write(AT91_SMC_MODE(cs), 44 44 - config->mode 45 45 - | AT91_SMC_TDF_(config->tdf_cycles) 46 46 - ); 48 48 + __raw_writel(config->mode 49 49 + | AT91_SMC_TDF_(config->tdf_cycles), 50 50 + base + AT91_SMC_MODE); 51 51 + } 52 52 + 53 53 + void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config) 54 54 + { 55 55 + sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); 56 56 + } 57 57 + 58 58 + void __init at91sam9_ioremap_smc(int id, u32 addr) 59 59 + { 60 60 + if (id > 1) { 61 61 + pr_warn("%s: id > 2\n", __func__); 62 62 + return; 63 63 + } 64 64 + smc_base_addr[id] = ioremap(addr, 512); 65 65 + if (!smc_base_addr[id]) 66 66 + pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr); 47 67 }

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arch/arm/mach-at91/sam9_smc.h

reviewed

··· 30 30 u8 tdf_cycles:4; 31 31 }; 32 32 33 33 - extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config); 33 33 + extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config); 34 34 + extern void __init at91sam9_ioremap_smc(int id, u32 addr);