drm/radeon: don't actually enable the IRQ regs until irq is enabled

vblank can try and enable the IRQ registers before we've set the interrupt
handler up.

Signed-off-by: Dave Airlie <airlied@redhat.com>

+4 -5
-1
drivers/gpu/drm/radeon/radeon_drv.h
··· 299 atomic_t swi_emitted; 300 int vblank_crtc; 301 uint32_t irq_enable_reg; 302 - int irq_enabled; 303 uint32_t r500_disp_irq_reg; 304 305 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
··· 299 atomic_t swi_emitted; 300 int vblank_crtc; 301 uint32_t irq_enable_reg; 302 uint32_t r500_disp_irq_reg; 303 304 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
+4 -4
drivers/gpu/drm/radeon/radeon_irq.c
··· 44 else 45 dev_priv->irq_enable_reg &= ~mask; 46 47 - RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 48 } 49 50 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state) ··· 57 else 58 dev_priv->r500_disp_irq_reg &= ~mask; 59 60 - RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 61 } 62 63 int radeon_enable_vblank(struct drm_device *dev, int crtc) ··· 356 (drm_radeon_private_t *) dev->dev_private; 357 if (!dev_priv) 358 return; 359 - 360 - dev_priv->irq_enabled = 0; 361 362 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) 363 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
··· 44 else 45 dev_priv->irq_enable_reg &= ~mask; 46 47 + if (!dev->irq_enabled) 48 + RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 49 } 50 51 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state) ··· 56 else 57 dev_priv->r500_disp_irq_reg &= ~mask; 58 59 + if (!dev->irq_enabled) 60 + RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 61 } 62 63 int radeon_enable_vblank(struct drm_device *dev, int crtc) ··· 354 (drm_radeon_private_t *) dev->dev_private; 355 if (!dev_priv) 356 return; 357 358 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) 359 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);