tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ath9k: Fix register definitions for QCA956x

Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

authored by

Miaoqing Pan and committed by
Kalle Valo fa5b8c8a e3faa866

+15 -10
+15 -10
drivers/net/wireless/ath/ath9k/ar9003_phy.h
··· 455 455 #define AR_PHY_MODE (AR_SM_BASE + 0x8) 456 456 #define AR_PHY_ACTIVE (AR_SM_BASE + 0xc) 457 457 #define AR_PHY_SPUR_MASK_A (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x18 : 0x20)) 458 - #define AR_PHY_SPUR_MASK_B (AR_SM_BASE + 0x24) 458 + #define AR_PHY_SPUR_MASK_B (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x1c : 0x24)) 459 459 #define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28) 460 460 #define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c) 461 461 #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30) ··· 495 495 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF 496 496 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0 497 497 498 - #define AR_PHY_TEST (AR_SM_BASE + 0x160) 498 + #define AR_PHY_TEST (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x15c : 0x160)) 499 499 500 500 #define AR_PHY_TEST_BBB_OBS_SEL 0x780000 501 501 #define AR_PHY_TEST_BBB_OBS_SEL_S 19 ··· 521 521 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S 29 522 522 523 523 524 - #define AR_PHY_TSTDAC (AR_SM_BASE + 0x168) 524 + #define AR_PHY_TSTDAC (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x164 : 0x168)) 525 525 526 - #define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c) 526 + #define AR_PHY_CHAN_STATUS (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x168 : 0x16c)) 527 527 528 528 #define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x16c : 0x170)) 529 529 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008 530 530 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3 531 531 532 - #define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174) 533 - #define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178) 534 - #define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c) 535 - #define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + 0x180) 536 - #define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + 0x190) 537 - #define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + 0x194) 532 + #define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x170 : 0x174)) 533 + #define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x174 : 0x178)) 534 + #define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x178 : 0x17c)) 535 + #define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x17c : 0x180)) 536 + #define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x184 : 0x190)) 537 + #define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x188 : 0x194)) 538 538 539 539 #define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x198 : 0x1a4)) 540 540 #define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8) 541 541 #define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac) 542 + #define AR_PHY_HEAVYCLIP_1 (AR_SM_BASE + 0x19c) 543 + #define AR_PHY_HEAVYCLIP_2 (AR_SM_BASE + 0x1a0) 544 + #define AR_PHY_HEAVYCLIP_3 (AR_SM_BASE + 0x1a4) 545 + #define AR_PHY_HEAVYCLIP_4 (AR_SM_BASE + 0x1a8) 546 + #define AR_PHY_HEAVYCLIP_5 (AR_SM_BASE + 0x1ac) 542 547 #define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0) 543 548 544 549 #define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))