tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Paul Burton:
"A light batch this time around but significant improvements for
certain systems:
- Removal of readq & writeq for MIPS32 kernels where they would
simply BUG() anyway, allowing drivers or other code that #ifdefs on
their presence to work properly.
- Improvements for Ingenic JZ4740 systems, including support for the
external memory controller & pinmuxing fixes for qi_lb60/NanoNote
systems.
- Improvements for Lantiq systems, in particular around SMP & IPIs.
- DT updates for ralink/MediaTek MT7628a systems to probe & configure
a bunch more devices.
- Miscellaneous cleanups & build fixes"
* tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits)
MIPS: fix some more fall through errors in arch/mips
MIPS: perf events: handle switch statement falling through warnings
mips/kprobes: Export kprobe_fault_handler()
MAINTAINERS: Add myself as Ingenic SoCs maintainer
MIPS: ralink: mt7628a.dtsi: Add watchdog controller DT node
MIPS: ralink: mt7628a.dtsi: Add SPI controller DT node
MIPS: ralink: mt7628a.dtsi: Add GPIO controller DT node
MIPS: ralink: mt7628a.dtsi: Add pinctrl DT properties to the UART nodes
MIPS: ralink: mt7628a.dtsi: Add pinmux DT node
MIPS: ralink: mt7628a.dtsi: Add SPDX GPL-2.0 license identifier
MIPS: lantiq: Add SMP support for lantiq interrupt controller
MIPS: lantiq: Shorten register names, remove unused macros
MIPS: lantiq: Fix bitfield masking
MIPS: lantiq: Remove unused macros
MIPS: lantiq: Fix attributes of of_device_id structure
MIPS: lantiq: Change variables to the same type as the source
MIPS: lantiq: Move macro directly to iomem function
mips: Remove q-accessors from non-64bit platforms
FDDI: defza: Include linux/io-64-nonatomic-lo-hi.h
MIPS: configs: Remove useless UEVENT_HELPER_PATH
...
+412
-192
+27
MAINTAINERS
+27
MAINTAINERS
···
7955
7955
S: Maintained
7956
7956
F: drivers/mtd/nand/raw/ingenic/
7957
7957
7958
+
INGENIC JZ47xx SoCs
7959
+
M: Paul Cercueil <paul@crapouillou.net>
7960
+
S: Maintained
7961
+
F: arch/mips/boot/dts/ingenic/
7962
+
F: arch/mips/include/asm/mach-jz4740/
7963
+
F: arch/mips/jz4740/
7964
+
F: drivers/clk/ingenic/
7965
+
F: drivers/dma/dma-jz4780.c
7966
+
F: drivers/gpu/drm/ingenic/
7967
+
F: drivers/i2c/busses/i2c-jz4780.c
7968
+
F: drivers/iio/adc/ingenic-adc.c
7969
+
F: drivers/irqchip/irq-ingenic.c
7970
+
F: drivers/memory/jz4780-nemc.c
7971
+
F: drivers/mmc/host/jz4740_mmc.c
7972
+
F: drivers/mtd/nand/raw/ingenic/
7973
+
F: drivers/pinctrl/pinctrl-ingenic.c
7974
+
F: drivers/power/supply/ingenic-battery.c
7975
+
F: drivers/pwm/pwm-jz4740.c
7976
+
F: drivers/rtc/rtc-jz4740.c
7977
+
F: drivers/tty/serial/8250/8250_ingenic.c
7978
+
F: drivers/usb/musb/jz4740.c
7979
+
F: drivers/watchdog/jz4740_wdt.c
7980
+
F: include/dt-bindings/iio/adc/ingenic,adc.h
7981
+
F: include/linux/mfd/ingenic-tcu.h
7982
+
F: sound/soc/jz4740/
7983
+
F: sound/soc/codecs/jz47*
7984
+
7958
7985
INOTIFY
7959
7986
M: Jan Kara <jack@suse.cz>
7960
7987
R: Amir Goldstein <amir73il@gmail.com>
+1
arch/mips/ar7/setup.c
+1
arch/mips/ar7/setup.c
+1
-1
arch/mips/ath79/setup.c
+1
-1
arch/mips/ath79/setup.c
+1
arch/mips/bcm63xx/dev-flash.c
+1
arch/mips/bcm63xx/dev-flash.c
+147
-1
arch/mips/boot/dts/ralink/mt7628a.dtsi
+147
-1
arch/mips/boot/dts/ralink/mt7628a.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
1
3
/ {
2
4
#address-cells = <1>;
3
5
#size-cells = <1>;
···
38
36
39
37
sysc: system-controller@0 {
40
38
compatible = "ralink,mt7620a-sysc", "syscon";
41
-
reg = <0x0 0x100>;
39
+
reg = <0x0 0x60>;
40
+
};
41
+
42
+
pinmux: pinmux@60 {
43
+
compatible = "pinctrl-single";
44
+
reg = <0x60 0x8>;
45
+
#address-cells = <1>;
46
+
#size-cells = <0>;
47
+
#pinctrl-cells = <2>;
48
+
pinctrl-single,bit-per-mux;
49
+
pinctrl-single,register-width = <32>;
50
+
pinctrl-single,function-mask = <0x1>;
51
+
52
+
pinmux_gpio_gpio: pinmux_gpio_gpio {
53
+
pinctrl-single,bits = <0x0 0x0 0x3>;
54
+
};
55
+
56
+
pinmux_spi_cs1_cs: pinmux_spi_cs1_cs {
57
+
pinctrl-single,bits = <0x0 0x0 0x30>;
58
+
};
59
+
60
+
pinmux_i2s_gpio: pinmux_i2s_gpio {
61
+
pinctrl-single,bits = <0x0 0x40 0xc0>;
62
+
};
63
+
64
+
pinmux_uart0_uart: pinmux_uart0_uart0 {
65
+
pinctrl-single,bits = <0x0 0x0 0x300>;
66
+
};
67
+
68
+
pinmux_sdmode_sdxc: pinmux_sdmode_sdxc {
69
+
pinctrl-single,bits = <0x0 0x0 0xc00>;
70
+
};
71
+
72
+
pinmux_sdmode_gpio: pinmux_sdmode_gpio {
73
+
pinctrl-single,bits = <0x0 0x400 0xc00>;
74
+
};
75
+
76
+
pinmux_spi_spi: pinmux_spi_spi {
77
+
pinctrl-single,bits = <0x0 0x0 0x1000>;
78
+
};
79
+
80
+
pinmux_refclk_gpio: pinmux_refclk_gpio {
81
+
pinctrl-single,bits = <0x0 0x40000 0x40000>;
82
+
};
83
+
84
+
pinmux_i2c_i2c: pinmux_i2c_i2c {
85
+
pinctrl-single,bits = <0x0 0x0 0x300000>;
86
+
};
87
+
88
+
pinmux_uart1_uart: pinmux_uart1_uart1 {
89
+
pinctrl-single,bits = <0x0 0x0 0x3000000>;
90
+
};
91
+
92
+
pinmux_uart2_uart: pinmux_uart2_uart {
93
+
pinctrl-single,bits = <0x0 0x0 0xc000000>;
94
+
};
95
+
96
+
pinmux_pwm0_pwm: pinmux_pwm0_pwm {
97
+
pinctrl-single,bits = <0x0 0x0 0x30000000>;
98
+
};
99
+
100
+
pinmux_pwm0_gpio: pinmux_pwm0_gpio {
101
+
pinctrl-single,bits = <0x0 0x10000000
102
+
0x30000000>;
103
+
};
104
+
105
+
pinmux_pwm1_pwm: pinmux_pwm1_pwm {
106
+
pinctrl-single,bits = <0x0 0x0 0xc0000000>;
107
+
};
108
+
109
+
pinmux_pwm1_gpio: pinmux_pwm1_gpio {
110
+
pinctrl-single,bits = <0x0 0x40000000
111
+
0xc0000000>;
112
+
};
113
+
114
+
pinmux_p0led_an_gpio: pinmux_p0led_an_gpio {
115
+
pinctrl-single,bits = <0x4 0x4 0xc>;
116
+
};
117
+
118
+
pinmux_p1led_an_gpio: pinmux_p1led_an_gpio {
119
+
pinctrl-single,bits = <0x4 0x10 0x30>;
120
+
};
121
+
122
+
pinmux_p2led_an_gpio: pinmux_p2led_an_gpio {
123
+
pinctrl-single,bits = <0x4 0x40 0xc0>;
124
+
};
125
+
126
+
pinmux_p3led_an_gpio: pinmux_p3led_an_gpio {
127
+
pinctrl-single,bits = <0x4 0x100 0x300>;
128
+
};
129
+
130
+
pinmux_p4led_an_gpio: pinmux_p4led_an_gpio {
131
+
pinctrl-single,bits = <0x4 0x400 0xc00>;
132
+
};
133
+
};
134
+
135
+
watchdog: watchdog@100 {
136
+
compatible = "mediatek,mt7621-wdt";
137
+
reg = <0x100 0x30>;
138
+
139
+
resets = <&resetc 8>;
140
+
reset-names = "wdt";
141
+
142
+
interrupt-parent = <&intc>;
143
+
interrupts = <24>;
144
+
145
+
status = "disabled";
42
146
};
43
147
44
148
intc: interrupt-controller@200 {
···
170
62
reg = <0x300 0x100>;
171
63
};
172
64
65
+
gpio: gpio@600 {
66
+
compatible = "mediatek,mt7621-gpio";
67
+
reg = <0x600 0x100>;
68
+
69
+
gpio-controller;
70
+
interrupt-controller;
71
+
#gpio-cells = <2>;
72
+
#interrupt-cells = <2>;
73
+
74
+
interrupt-parent = <&intc>;
75
+
interrupts = <6>;
76
+
};
77
+
78
+
spi: spi@b00 {
79
+
compatible = "ralink,mt7621-spi";
80
+
reg = <0xb00 0x100>;
81
+
82
+
pinctrl-names = "default";
83
+
pinctrl-0 = <&pinmux_spi_spi>;
84
+
85
+
resets = <&resetc 18>;
86
+
reset-names = "spi";
87
+
88
+
#address-cells = <1>;
89
+
#size-cells = <0>;
90
+
91
+
status = "disabled";
92
+
};
93
+
173
94
uart0: uartlite@c00 {
174
95
compatible = "ns16550a";
175
96
reg = <0xc00 0x100>;
97
+
98
+
pinctrl-names = "default";
99
+
pinctrl-0 = <&pinmux_uart0_uart>;
176
100
177
101
resets = <&resetc 12>;
178
102
reset-names = "uart0";
···
219
79
compatible = "ns16550a";
220
80
reg = <0xd00 0x100>;
221
81
82
+
pinctrl-names = "default";
83
+
pinctrl-0 = <&pinmux_uart1_uart>;
84
+
222
85
resets = <&resetc 19>;
223
86
reset-names = "uart1";
224
87
···
234
91
uart2: uart2@e00 {
235
92
compatible = "ns16550a";
236
93
reg = <0xe00 0x100>;
94
+
95
+
pinctrl-names = "default";
96
+
pinctrl-0 = <&pinmux_uart2_uart>;
237
97
238
98
resets = <&resetc 20>;
239
99
reset-names = "uart2";
+1
-1
arch/mips/cavium-octeon/executive/cvmx-pko.c
+1
-1
arch/mips/cavium-octeon/executive/cvmx-pko.c
···
485
485
config.s.qos_mask = 0xff;
486
486
break;
487
487
case CVMX_PKO_QUEUE_STATIC_PRIORITY:
488
-
/* Pass 1 will fall through to the error case */
489
488
if (!cvmx_octeon_is_pass1()) {
490
489
config.s.qos_mask = 0xff;
491
490
break;
492
491
}
492
+
/* fall through - to the error case, when Pass 1 */
493
493
default:
494
494
cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid "
495
495
"priority %llu\n",
-1
arch/mips/configs/ar7_defconfig
-1
arch/mips/configs/ar7_defconfig
-1
arch/mips/configs/ath25_defconfig
-1
arch/mips/configs/ath25_defconfig
-1
arch/mips/configs/ath79_defconfig
-1
arch/mips/configs/ath79_defconfig
-1
arch/mips/configs/bcm63xx_defconfig
-1
arch/mips/configs/bcm63xx_defconfig
-1
arch/mips/configs/bigsur_defconfig
-1
arch/mips/configs/bigsur_defconfig
-1
arch/mips/configs/bmips_be_defconfig
-1
arch/mips/configs/bmips_be_defconfig
-1
arch/mips/configs/bmips_stb_defconfig
-1
arch/mips/configs/bmips_stb_defconfig
-1
arch/mips/configs/cavium_octeon_defconfig
-1
arch/mips/configs/cavium_octeon_defconfig
-1
arch/mips/configs/ci20_defconfig
-1
arch/mips/configs/ci20_defconfig
-1
arch/mips/configs/cobalt_defconfig
-1
arch/mips/configs/cobalt_defconfig
-1
arch/mips/configs/fuloong2e_defconfig
-1
arch/mips/configs/fuloong2e_defconfig
-1
arch/mips/configs/gpr_defconfig
-1
arch/mips/configs/gpr_defconfig
-1
arch/mips/configs/ip27_defconfig
-1
arch/mips/configs/ip27_defconfig
-1
arch/mips/configs/ip32_defconfig
-1
arch/mips/configs/ip32_defconfig
-2
arch/mips/configs/lemote2f_defconfig
-2
arch/mips/configs/lemote2f_defconfig
···
77
77
CONFIG_MAC80211_LEDS=y
78
78
CONFIG_RFKILL=m
79
79
CONFIG_RFKILL_INPUT=y
80
-
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
81
80
CONFIG_BLK_DEV_LOOP=y
82
81
CONFIG_BLK_DEV_CRYPTOLOOP=m
83
82
CONFIG_BLK_DEV_RAM=y
···
143
144
CONFIG_FB_SIS=y
144
145
CONFIG_FB_SIS_300=y
145
146
CONFIG_FB_SIS_315=y
146
-
CONFIG_BACKLIGHT_LCD_SUPPORT=y
147
147
# CONFIG_LCD_CLASS_DEVICE is not set
148
148
CONFIG_BACKLIGHT_CLASS_DEVICE=y
149
149
CONFIG_BACKLIGHT_GENERIC=m
-1
arch/mips/configs/loongson1b_defconfig
-1
arch/mips/configs/loongson1b_defconfig
-1
arch/mips/configs/loongson1c_defconfig
-1
arch/mips/configs/loongson1c_defconfig
-1
arch/mips/configs/loongson3_defconfig
-1
arch/mips/configs/loongson3_defconfig
-1
arch/mips/configs/malta_defconfig
-1
arch/mips/configs/malta_defconfig
-1
arch/mips/configs/malta_kvm_defconfig
-1
arch/mips/configs/malta_kvm_defconfig
-1
arch/mips/configs/malta_kvm_guest_defconfig
-1
arch/mips/configs/malta_kvm_guest_defconfig
-1
arch/mips/configs/maltaup_xpa_defconfig
-1
arch/mips/configs/maltaup_xpa_defconfig
-1
arch/mips/configs/mips_paravirt_defconfig
-1
arch/mips/configs/mips_paravirt_defconfig
-1
arch/mips/configs/omega2p_defconfig
-1
arch/mips/configs/omega2p_defconfig
-1
arch/mips/configs/pistachio_defconfig
-1
arch/mips/configs/pistachio_defconfig
-1
arch/mips/configs/pnx8335_stb225_defconfig
-1
arch/mips/configs/pnx8335_stb225_defconfig
-2
arch/mips/configs/qi_lb60_defconfig
-2
arch/mips/configs/qi_lb60_defconfig
···
41
41
CONFIG_TCP_CONG_WESTWOOD=y
42
42
# CONFIG_TCP_CONG_HTCP is not set
43
43
# CONFIG_IPV6 is not set
44
-
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45
44
CONFIG_MTD=y
46
45
CONFIG_MTD_BLOCK=y
47
46
CONFIG_MTD_RAW_NAND=y
···
76
77
CONFIG_REGULATOR_FIXED_VOLTAGE=y
77
78
CONFIG_FB=y
78
79
CONFIG_FB_JZ4740=y
79
-
CONFIG_BACKLIGHT_LCD_SUPPORT=y
80
80
CONFIG_LCD_CLASS_DEVICE=y
81
81
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
82
82
# CONFIG_VGA_CONSOLE is not set
-1
arch/mips/configs/rb532_defconfig
-1
arch/mips/configs/rb532_defconfig
-1
arch/mips/configs/rt305x_defconfig
-1
arch/mips/configs/rt305x_defconfig
-1
arch/mips/configs/sb1250_swarm_defconfig
-1
arch/mips/configs/sb1250_swarm_defconfig
-1
arch/mips/configs/tb0219_defconfig
-1
arch/mips/configs/tb0219_defconfig
-1
arch/mips/configs/tb0226_defconfig
-1
arch/mips/configs/tb0226_defconfig
-1
arch/mips/configs/tb0287_defconfig
-1
arch/mips/configs/tb0287_defconfig
-1
arch/mips/configs/vocore2_defconfig
-1
arch/mips/configs/vocore2_defconfig
-1
arch/mips/configs/xway_defconfig
-1
arch/mips/configs/xway_defconfig
+60
-65
arch/mips/include/asm/cpu.h
+60
-65
arch/mips/include/asm/cpu.h
···
9
9
#ifndef _ASM_CPU_H
10
10
#define _ASM_CPU_H
11
11
12
+
#include <linux/bits.h>
13
+
12
14
/*
13
15
As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
14
16
register 15, select 0) is defined in this (backwards compatible) way:
···
355
353
MIPS_CPU_ISA_M64R6)
356
354
357
355
/*
358
-
* Private version of BIT_ULL() to escape include file recursion hell.
359
-
* We soon will have to switch to another mechanism that will work with
360
-
* more than 64 bits anyway.
361
-
*/
362
-
#define MBIT_ULL(bit) (1ULL << (bit))
363
-
364
-
/*
365
356
* CPU Option encodings
366
357
*/
367
-
#define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */
368
-
#define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */
369
-
#define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */
370
-
#define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */
371
-
#define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */
372
-
#define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */
373
-
#define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */
374
-
#define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */
375
-
#define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */
376
-
#define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */
377
-
#define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */
378
-
#define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
379
-
#define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */
380
-
#define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */
381
-
#define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */
382
-
#define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */
383
-
#define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */
384
-
#define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */
385
-
#define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */
386
-
#define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
387
-
#define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
388
-
#define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */
389
-
#define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */
390
-
#define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
391
-
#define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */
392
-
#define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */
393
-
#define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */
394
-
#define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
395
-
#define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */
396
-
#define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
397
-
#define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */
398
-
#define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */
399
-
#define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */
400
-
#define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */
401
-
#define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */
402
-
#define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */
403
-
#define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */
404
-
#define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */
405
-
#define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */
406
-
#define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */
407
-
#define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
408
-
#define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */
409
-
#define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
410
-
#define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */
411
-
#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */
412
-
#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
413
-
#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */
414
-
#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */
415
-
#define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
416
-
#define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */
417
-
#define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */
418
-
#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
419
-
#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
420
-
#define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */
358
+
#define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
359
+
#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
360
+
#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
361
+
#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
362
+
#define MIPS_CPU_TX39_CACHE BIT_ULL( 4) /* TX3900-style caches */
363
+
#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
364
+
#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
365
+
#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
366
+
#define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
367
+
#define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
368
+
#define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
369
+
#define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
370
+
#define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */
371
+
#define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */
372
+
#define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
373
+
#define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
374
+
#define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */
375
+
#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */
376
+
#define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */
377
+
#define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
378
+
#define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
379
+
#define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
380
+
#define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */
381
+
#define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
382
+
#define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */
383
+
#define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */
384
+
#define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */
385
+
#define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
386
+
#define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */
387
+
#define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
388
+
#define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */
389
+
#define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */
390
+
#define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */
391
+
#define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */
392
+
#define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
393
+
#define MIPS_CPU_BP_GHIST BIT_ULL(35) /* R12K+ Branch Prediction Global History */
394
+
#define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */
395
+
#define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
396
+
#define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */
397
+
#define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */
398
+
#define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
399
+
#define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */
400
+
#define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
401
+
#define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
402
+
#define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */
403
+
#define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */
404
+
#define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */
405
+
#define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */
406
+
#define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
407
+
#define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */
408
+
#define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */
409
+
#define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
410
+
#define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
411
+
#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */
421
412
#define MIPS_CPU_SHARED_FTLB_RAM \
422
-
MBIT_ULL(54) /* CPU shares FTLB RAM with another */
413
+
BIT_ULL(54) /* CPU shares FTLB RAM with another */
423
414
#define MIPS_CPU_SHARED_FTLB_ENTRIES \
424
-
MBIT_ULL(55) /* CPU shares FTLB entries with another */
415
+
BIT_ULL(55) /* CPU shares FTLB entries with another */
425
416
#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
426
-
MBIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
427
-
#define MIPS_CPU_MMID MBIT_ULL(57) /* CPU supports MemoryMapIDs */
417
+
BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
418
+
#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
428
419
429
420
/*
430
421
* CPU ASE encodings
+11
arch/mips/include/asm/io.h
+11
arch/mips/include/asm/io.h
···
460
460
BUILDIO_MEM(b, u8)
461
461
BUILDIO_MEM(w, u16)
462
462
BUILDIO_MEM(l, u32)
463
+
#ifdef CONFIG_64BIT
463
464
BUILDIO_MEM(q, u64)
465
+
#else
466
+
__BUILD_MEMORY_PFX(__raw_, q, u64, 0)
467
+
__BUILD_MEMORY_PFX(__mem_, q, u64, 0)
468
+
#endif
464
469
465
470
#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
466
471
__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \
···
491
486
#define readb_relaxed __relaxed_readb
492
487
#define readw_relaxed __relaxed_readw
493
488
#define readl_relaxed __relaxed_readl
489
+
#ifdef CONFIG_64BIT
494
490
#define readq_relaxed __relaxed_readq
491
+
#endif
495
492
496
493
#define writeb_relaxed __relaxed_writeb
497
494
#define writew_relaxed __relaxed_writew
498
495
#define writel_relaxed __relaxed_writel
496
+
#ifdef CONFIG_64BIT
499
497
#define writeq_relaxed __relaxed_writeq
498
+
#endif
500
499
501
500
#define readb_be(addr) \
502
501
__raw_readb((__force unsigned *)(addr))
···
523
514
/*
524
515
* Some code tests for these symbols
525
516
*/
517
+
#ifdef CONFIG_64BIT
526
518
#define readq readq
527
519
#define writeq writeq
520
+
#endif
528
521
529
522
#define __BUILD_MEMORY_STRING(bwlq, type) \
530
523
\
-1
arch/mips/include/asm/mach-ralink/pinmux.h
-1
arch/mips/include/asm/mach-ralink/pinmux.h
+8
-8
arch/mips/jz4740/board-qi_lb60.c
+8
-8
arch/mips/jz4740/board-qi_lb60.c
···
466
466
static struct pinctrl_map pin_map[] __initdata = {
467
467
/* NAND pin configuration */
468
468
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand",
469
-
"10010000.jz4740-pinctrl", "nand", "nand-cs1"),
469
+
"10010000.pin-controller", "nand-cs1", "nand"),
470
470
471
471
/* fbdev pin configuration */
472
472
PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT,
473
-
"10010000.jz4740-pinctrl", "lcd", "lcd-8bit"),
473
+
"10010000.pin-controller", "lcd-8bit", "lcd"),
474
474
PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP,
475
-
"10010000.jz4740-pinctrl", "lcd", "lcd-no-pins"),
475
+
"10010000.pin-controller", "lcd-no-pins", "lcd"),
476
476
477
477
/* MMC pin configuration */
478
478
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
479
-
"10010000.jz4740-pinctrl", "mmc", "mmc-1bit"),
479
+
"10010000.pin-controller", "mmc-1bit", "mmc"),
480
480
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
481
-
"10010000.jz4740-pinctrl", "mmc", "mmc-4bit"),
481
+
"10010000.pin-controller", "mmc-4bit", "mmc"),
482
482
PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
483
-
"10010000.jz4740-pinctrl", "PD0", pin_cfg_bias_disable),
483
+
"10010000.pin-controller", "PD0", pin_cfg_bias_disable),
484
484
PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
485
-
"10010000.jz4740-pinctrl", "PD2", pin_cfg_bias_disable),
485
+
"10010000.pin-controller", "PD2", pin_cfg_bias_disable),
486
486
487
487
/* PWM pin configuration */
488
488
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm",
489
-
"10010000.jz4740-pinctrl", "pwm4", "pwm4"),
489
+
"10010000.pin-controller", "pwm4", "pwm4"),
490
490
};
491
491
492
492
+12
-11
arch/mips/kernel/ftrace.c
+12
-11
arch/mips/kernel/ftrace.c
···
333
333
return;
334
334
335
335
/*
336
-
* "parent_ra_addr" is the stack address saved the return address of
337
-
* the caller of _mcount.
336
+
* "parent_ra_addr" is the stack address where the return address of
337
+
* the caller of _mcount is saved.
338
338
*
339
-
* if the gcc < 4.5, a leaf function does not save the return address
340
-
* in the stack address, so, we "emulate" one in _mcount's stack space,
341
-
* and hijack it directly, but for a non-leaf function, it save the
342
-
* return address to the its own stack space, we can not hijack it
343
-
* directly, but need to find the real stack address,
344
-
* ftrace_get_parent_addr() does it!
339
+
* If gcc < 4.5, a leaf function does not save the return address
340
+
* in the stack address, so we "emulate" one in _mcount's stack space,
341
+
* and hijack it directly.
342
+
* For a non-leaf function, it does save the return address to its own
343
+
* stack space, so we can not hijack it directly, but need to find the
344
+
* real stack address, which is done by ftrace_get_parent_addr().
345
345
*
346
-
* if gcc>= 4.5, with the new -mmcount-ra-address option, for a
346
+
* If gcc >= 4.5, with the new -mmcount-ra-address option, for a
347
347
* non-leaf function, the location of the return address will be saved
348
-
* to $12 for us, and for a leaf function, only put a zero into $12. we
349
-
* do it in ftrace_graph_caller of mcount.S.
348
+
* to $12 for us.
349
+
* For a leaf function, it just puts a zero into $12, so we handle
350
+
* it in ftrace_graph_caller() of mcount.S.
350
351
*/
351
352
352
353
/* old_parent_ra = *parent_ra_addr; */
+15
-15
arch/mips/kernel/perf_event_mipsxx.c
+15
-15
arch/mips/kernel/perf_event_mipsxx.c
···
790
790
case 4:
791
791
mipsxx_pmu_write_control(3, 0);
792
792
mipspmu.write_counter(3, 0);
793
+
/* fall through */
793
794
case 3:
794
795
mipsxx_pmu_write_control(2, 0);
795
796
mipspmu.write_counter(2, 0);
797
+
/* fall through */
796
798
case 2:
797
799
mipsxx_pmu_write_control(1, 0);
798
800
mipspmu.write_counter(1, 0);
801
+
/* fall through */
799
802
case 1:
800
803
mipsxx_pmu_write_control(0, 0);
801
804
mipspmu.write_counter(0, 0);
805
+
/* fall through */
802
806
}
803
807
}
804
808
···
1384
1380
struct perf_sample_data data;
1385
1381
unsigned int counters = mipspmu.num_counters;
1386
1382
u64 counter;
1387
-
int handled = IRQ_NONE;
1383
+
int n, handled = IRQ_NONE;
1388
1384
struct pt_regs *regs;
1389
1385
1390
1386
if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
···
1405
1401
1406
1402
perf_sample_data_init(&data, 0, 0);
1407
1403
1408
-
switch (counters) {
1409
-
#define HANDLE_COUNTER(n) \
1410
-
case n + 1: \
1411
-
if (test_bit(n, cpuc->used_mask)) { \
1412
-
counter = mipspmu.read_counter(n); \
1413
-
if (counter & mipspmu.overflow) { \
1414
-
handle_associated_event(cpuc, n, &data, regs); \
1415
-
handled = IRQ_HANDLED; \
1416
-
} \
1417
-
}
1418
-
HANDLE_COUNTER(3)
1419
-
HANDLE_COUNTER(2)
1420
-
HANDLE_COUNTER(1)
1421
-
HANDLE_COUNTER(0)
1404
+
for (n = counters - 1; n >= 0; n--) {
1405
+
if (!test_bit(n, cpuc->used_mask))
1406
+
continue;
1407
+
1408
+
counter = mipspmu.read_counter(n);
1409
+
if (!(counter & mipspmu.overflow))
1410
+
continue;
1411
+
1412
+
handle_associated_event(cpuc, n, &data, regs);
1413
+
handled = IRQ_HANDLED;
1422
1414
}
1423
1415
1424
1416
#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
+126
-51
arch/mips/lantiq/irq.c
+126
-51
arch/mips/lantiq/irq.c
···
20
20
#include <irq.h>
21
21
22
22
/* register definitions - internal irqs */
23
-
#define LTQ_ICU_IM0_ISR 0x0000
24
-
#define LTQ_ICU_IM0_IER 0x0008
25
-
#define LTQ_ICU_IM0_IOSR 0x0010
26
-
#define LTQ_ICU_IM0_IRSR 0x0018
27
-
#define LTQ_ICU_IM0_IMR 0x0020
28
-
#define LTQ_ICU_IM1_ISR 0x0028
29
-
#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
23
+
#define LTQ_ICU_ISR 0x0000
24
+
#define LTQ_ICU_IER 0x0008
25
+
#define LTQ_ICU_IOSR 0x0010
26
+
#define LTQ_ICU_IRSR 0x0018
27
+
#define LTQ_ICU_IMR 0x0020
28
+
29
+
#define LTQ_ICU_IM_SIZE 0x28
30
30
31
31
/* register definitions - external irqs */
32
32
#define LTQ_EIU_EXIN_C 0x0000
···
46
46
*/
47
47
#define LTQ_ICU_EBU_IRQ 22
48
48
49
-
#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
50
-
#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
49
+
#define ltq_icu_w32(vpe, m, x, y) \
50
+
ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y))
51
+
52
+
#define ltq_icu_r32(vpe, m, x) \
53
+
ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x))
51
54
52
55
#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
53
56
#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
54
-
55
-
/* our 2 ipi interrupts for VSMP */
56
-
#define MIPS_CPU_IPI_RESCHED_IRQ 0
57
-
#define MIPS_CPU_IPI_CALL_IRQ 1
58
57
59
58
/* we have a cascade of 8 irqs */
60
59
#define MIPS_CPU_IRQ_CASCADE 8
61
60
62
61
static int exin_avail;
63
62
static u32 ltq_eiu_irq[MAX_EIU];
64
-
static void __iomem *ltq_icu_membase[MAX_IM];
63
+
static void __iomem *ltq_icu_membase[NR_CPUS];
65
64
static void __iomem *ltq_eiu_membase;
66
65
static struct irq_domain *ltq_domain;
66
+
static DEFINE_SPINLOCK(ltq_eiu_lock);
67
+
static DEFINE_RAW_SPINLOCK(ltq_icu_lock);
67
68
static int ltq_perfcount_irq;
68
69
69
70
int ltq_eiu_get_irq(int exin)
···
76
75
77
76
void ltq_disable_irq(struct irq_data *d)
78
77
{
79
-
u32 ier = LTQ_ICU_IM0_IER;
80
-
int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
81
-
int im = offset / INT_NUM_IM_OFFSET;
78
+
unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
79
+
unsigned long im = offset / INT_NUM_IM_OFFSET;
80
+
unsigned long flags;
81
+
int vpe;
82
82
83
83
offset %= INT_NUM_IM_OFFSET;
84
-
ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
84
+
85
+
raw_spin_lock_irqsave(<q_icu_lock, flags);
86
+
for_each_present_cpu(vpe) {
87
+
ltq_icu_w32(vpe, im,
88
+
ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
89
+
LTQ_ICU_IER);
90
+
}
91
+
raw_spin_unlock_irqrestore(<q_icu_lock, flags);
85
92
}
86
93
87
94
void ltq_mask_and_ack_irq(struct irq_data *d)
88
95
{
89
-
u32 ier = LTQ_ICU_IM0_IER;
90
-
u32 isr = LTQ_ICU_IM0_ISR;
91
-
int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
92
-
int im = offset / INT_NUM_IM_OFFSET;
96
+
unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
97
+
unsigned long im = offset / INT_NUM_IM_OFFSET;
98
+
unsigned long flags;
99
+
int vpe;
93
100
94
101
offset %= INT_NUM_IM_OFFSET;
95
-
ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
96
-
ltq_icu_w32(im, BIT(offset), isr);
102
+
103
+
raw_spin_lock_irqsave(<q_icu_lock, flags);
104
+
for_each_present_cpu(vpe) {
105
+
ltq_icu_w32(vpe, im,
106
+
ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
107
+
LTQ_ICU_IER);
108
+
ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
109
+
}
110
+
raw_spin_unlock_irqrestore(<q_icu_lock, flags);
97
111
}
98
112
99
113
static void ltq_ack_irq(struct irq_data *d)
100
114
{
101
-
u32 isr = LTQ_ICU_IM0_ISR;
102
-
int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
103
-
int im = offset / INT_NUM_IM_OFFSET;
115
+
unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
116
+
unsigned long im = offset / INT_NUM_IM_OFFSET;
117
+
unsigned long flags;
118
+
int vpe;
104
119
105
120
offset %= INT_NUM_IM_OFFSET;
106
-
ltq_icu_w32(im, BIT(offset), isr);
121
+
122
+
raw_spin_lock_irqsave(<q_icu_lock, flags);
123
+
for_each_present_cpu(vpe) {
124
+
ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
125
+
}
126
+
raw_spin_unlock_irqrestore(<q_icu_lock, flags);
107
127
}
108
128
109
129
void ltq_enable_irq(struct irq_data *d)
110
130
{
111
-
u32 ier = LTQ_ICU_IM0_IER;
112
-
int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
113
-
int im = offset / INT_NUM_IM_OFFSET;
131
+
unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
132
+
unsigned long im = offset / INT_NUM_IM_OFFSET;
133
+
unsigned long flags;
134
+
int vpe;
114
135
115
136
offset %= INT_NUM_IM_OFFSET;
116
-
ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
137
+
138
+
vpe = cpumask_first(irq_data_get_effective_affinity_mask(d));
139
+
140
+
/* This shouldn't be even possible, maybe during CPU hotplug spam */
141
+
if (unlikely(vpe >= nr_cpu_ids))
142
+
vpe = smp_processor_id();
143
+
144
+
raw_spin_lock_irqsave(<q_icu_lock, flags);
145
+
146
+
ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) | BIT(offset),
147
+
LTQ_ICU_IER);
148
+
149
+
raw_spin_unlock_irqrestore(<q_icu_lock, flags);
117
150
}
118
151
119
152
static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
120
153
{
121
154
int i;
155
+
unsigned long flags;
122
156
123
157
for (i = 0; i < exin_avail; i++) {
124
158
if (d->hwirq == ltq_eiu_irq[i]) {
···
190
154
if (edge)
191
155
irq_set_handler(d->hwirq, handle_edge_irq);
192
156
193
-
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
194
-
(val << (i * 4)), LTQ_EIU_EXIN_C);
157
+
spin_lock_irqsave(<q_eiu_lock, flags);
158
+
ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
159
+
(~(7 << (i * 4)))) | (val << (i * 4)),
160
+
LTQ_EIU_EXIN_C);
161
+
spin_unlock_irqrestore(<q_eiu_lock, flags);
195
162
}
196
163
}
197
164
···
238
199
}
239
200
}
240
201
202
+
#if defined(CONFIG_SMP)
203
+
static int ltq_icu_irq_set_affinity(struct irq_data *d,
204
+
const struct cpumask *cpumask, bool force)
205
+
{
206
+
struct cpumask tmask;
207
+
208
+
if (!cpumask_and(&tmask, cpumask, cpu_online_mask))
209
+
return -EINVAL;
210
+
211
+
irq_data_update_effective_affinity(d, &tmask);
212
+
213
+
return IRQ_SET_MASK_OK;
214
+
}
215
+
#endif
216
+
241
217
static struct irq_chip ltq_irq_type = {
242
218
.name = "icu",
243
219
.irq_enable = ltq_enable_irq,
···
261
207
.irq_ack = ltq_ack_irq,
262
208
.irq_mask = ltq_disable_irq,
263
209
.irq_mask_ack = ltq_mask_and_ack_irq,
210
+
#if defined(CONFIG_SMP)
211
+
.irq_set_affinity = ltq_icu_irq_set_affinity,
212
+
#endif
264
213
};
265
214
266
215
static struct irq_chip ltq_eiu_type = {
···
277
220
.irq_mask = ltq_disable_irq,
278
221
.irq_mask_ack = ltq_mask_and_ack_irq,
279
222
.irq_set_type = ltq_eiu_settype,
223
+
#if defined(CONFIG_SMP)
224
+
.irq_set_affinity = ltq_icu_irq_set_affinity,
225
+
#endif
280
226
};
281
227
282
228
static void ltq_hw_irq_handler(struct irq_desc *desc)
283
229
{
284
-
int module = irq_desc_get_irq(desc) - 2;
230
+
unsigned int module = irq_desc_get_irq(desc) - 2;
285
231
u32 irq;
286
-
int hwirq;
232
+
irq_hw_number_t hwirq;
233
+
int vpe = smp_processor_id();
287
234
288
-
irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
235
+
irq = ltq_icu_r32(vpe, module, LTQ_ICU_IOSR);
289
236
if (irq == 0)
290
237
return;
291
238
···
310
249
static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
311
250
{
312
251
struct irq_chip *chip = <q_irq_type;
252
+
struct irq_data *data;
313
253
int i;
314
254
315
255
if (hw < MIPS_CPU_IRQ_CASCADE)
···
319
257
for (i = 0; i < exin_avail; i++)
320
258
if (hw == ltq_eiu_irq[i])
321
259
chip = <q_eiu_type;
260
+
261
+
data = irq_get_irq_data(irq);
262
+
263
+
irq_data_update_effective_affinity(data, cpumask_of(0));
322
264
323
265
irq_set_chip_and_handler(irq, chip, handle_level_irq);
324
266
···
338
272
{
339
273
struct device_node *eiu_node;
340
274
struct resource res;
341
-
int i, ret;
275
+
int i, ret, vpe;
342
276
343
-
for (i = 0; i < MAX_IM; i++) {
344
-
if (of_address_to_resource(node, i, &res))
345
-
panic("Failed to get icu memory range");
277
+
/* load register regions of available ICUs */
278
+
for_each_possible_cpu(vpe) {
279
+
if (of_address_to_resource(node, vpe, &res))
280
+
panic("Failed to get icu%i memory range", vpe);
346
281
347
282
if (!request_mem_region(res.start, resource_size(&res),
348
283
res.name))
349
-
pr_err("Failed to request icu memory");
284
+
pr_err("Failed to request icu%i memory\n", vpe);
350
285
351
-
ltq_icu_membase[i] = ioremap_nocache(res.start,
286
+
ltq_icu_membase[vpe] = ioremap_nocache(res.start,
352
287
resource_size(&res));
353
-
if (!ltq_icu_membase[i])
354
-
panic("Failed to remap icu memory");
288
+
289
+
if (!ltq_icu_membase[vpe])
290
+
panic("Failed to remap icu%i memory", vpe);
355
291
}
356
292
357
293
/* turn off all irqs by default */
358
-
for (i = 0; i < MAX_IM; i++) {
359
-
/* make sure all irqs are turned off by default */
360
-
ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
361
-
/* clear all possibly pending interrupts */
362
-
ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
294
+
for_each_possible_cpu(vpe) {
295
+
for (i = 0; i < MAX_IM; i++) {
296
+
/* make sure all irqs are turned off by default */
297
+
ltq_icu_w32(vpe, i, 0, LTQ_ICU_IER);
298
+
299
+
/* clear all possibly pending interrupts */
300
+
ltq_icu_w32(vpe, i, ~0, LTQ_ICU_ISR);
301
+
ltq_icu_w32(vpe, i, ~0, LTQ_ICU_IMR);
302
+
303
+
/* clear resend */
304
+
ltq_icu_w32(vpe, i, 0, LTQ_ICU_IRSR);
305
+
}
363
306
}
364
307
365
308
mips_cpu_irq_init();
···
422
347
return CP0_LEGACY_COMPARE_IRQ;
423
348
}
424
349
425
-
static struct of_device_id __initdata of_irq_ids[] = {
350
+
static const struct of_device_id of_irq_ids[] __initconst = {
426
351
{ .compatible = "lantiq,icu", .data = icu_of_init },
427
352
{},
428
353
};
+1
-1
drivers/memory/jz4780-nemc.c
+1
-1
drivers/memory/jz4780-nemc.c
···
61
61
*
62
62
* Return: The number of unique NEMC banks referred to by the specified NEMC
63
63
* child device. Unique here means that a device that references the same bank
64
-
* multiple times in the its "reg" property will only count once.
64
+
* multiple times in its "reg" property will only count once.
65
65
*/
66
66
unsigned int jz4780_nemc_num_banks(struct device *dev)
67
67
{