Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

MIPS: ath79: Prepare moving the MISC driver to drivers/irqchip

To prepare moving out of the arch directory rework the MISC
implementation to use irq domains instead of hard coded IRQ numbers.
Also remove the uses of the ath79_reset_base global pointer in the IRQ
methods.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Alexander Couzens <lynxis@fe80.eu>
Cc: Joel Porquet <joel@porquet.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11506/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Alban Bedel and committed by
Ralf Baechle
f9a3e047 a797a0cf

+28 -30
+28 -30
arch/mips/ath79/irq.c
··· 26 26 #include "common.h" 27 27 #include "machtypes.h" 28 28 29 + static void __init ath79_misc_intc_domain_init( 30 + struct device_node *node, int irq); 31 + 29 32 static void ath79_misc_irq_handler(struct irq_desc *desc) 30 33 { 31 - void __iomem *base = ath79_reset_base; 34 + struct irq_domain *domain = irq_desc_get_handler_data(desc); 35 + void __iomem *base = domain->host_data; 32 36 u32 pending; 33 37 34 38 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & ··· 46 42 while (pending) { 47 43 int bit = __ffs(pending); 48 44 49 - generic_handle_irq(ATH79_MISC_IRQ(bit)); 45 + generic_handle_irq(irq_linear_revmap(domain, bit)); 50 46 pending &= ~BIT(bit); 51 47 } 52 48 } 53 49 54 50 static void ar71xx_misc_irq_unmask(struct irq_data *d) 55 51 { 56 - unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE; 57 - void __iomem *base = ath79_reset_base; 52 + void __iomem *base = irq_data_get_irq_chip_data(d); 53 + unsigned int irq = d->hwirq; 58 54 u32 t; 59 55 60 56 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); ··· 66 62 67 63 static void ar71xx_misc_irq_mask(struct irq_data *d) 68 64 { 69 - unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE; 70 - void __iomem *base = ath79_reset_base; 65 + void __iomem *base = irq_data_get_irq_chip_data(d); 66 + unsigned int irq = d->hwirq; 71 67 u32 t; 72 68 73 69 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); ··· 79 75 80 76 static void ar724x_misc_irq_ack(struct irq_data *d) 81 77 { 82 - unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE; 83 - void __iomem *base = ath79_reset_base; 78 + void __iomem *base = irq_data_get_irq_chip_data(d); 79 + unsigned int irq = d->hwirq; 84 80 u32 t; 85 81 86 82 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); ··· 98 94 99 95 static void __init ath79_misc_irq_init(void) 100 96 { 101 - void __iomem *base = ath79_reset_base; 102 - int i; 103 - 104 - __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); 105 - __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); 106 - 107 97 if (soc_is_ar71xx() || soc_is_ar913x()) 108 98 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; 109 99 else if (soc_is_ar724x() || ··· 108 110 else 109 111 BUG(); 110 112 111 - for (i = ATH79_MISC_IRQ_BASE; 112 - i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { 113 - irq_set_chip_and_handler(i, &ath79_misc_irq_chip, 114 - handle_level_irq); 115 - } 116 - 117 - irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler); 113 + ath79_misc_intc_domain_init(NULL, ATH79_CPU_IRQ(6)); 118 114 } 119 115 120 116 static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) ··· 251 259 static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 252 260 { 253 261 irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq); 262 + irq_set_chip_data(irq, d->host_data); 254 263 return 0; 255 264 } 256 265 ··· 260 267 .map = misc_map, 261 268 }; 262 269 263 - static int __init ath79_misc_intc_of_init( 264 - struct device_node *node, struct device_node *parent) 270 + static void __init ath79_misc_intc_domain_init( 271 + struct device_node *node, int irq) 265 272 { 266 273 void __iomem *base = ath79_reset_base; 267 274 struct irq_domain *domain; 268 - int irq; 269 - 270 - irq = irq_of_parse_and_map(node, 0); 271 - if (!irq) 272 - panic("Failed to get MISC IRQ"); 273 275 274 276 domain = irq_domain_add_legacy(node, ATH79_MISC_IRQ_COUNT, 275 - ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, NULL); 277 + ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, base); 276 278 if (!domain) 277 279 panic("Failed to add MISC irqdomain"); 278 280 ··· 275 287 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); 276 288 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); 277 289 290 + irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain); 291 + } 278 292 279 - irq_set_chained_handler(irq, ath79_misc_irq_handler); 293 + static int __init ath79_misc_intc_of_init( 294 + struct device_node *node, struct device_node *parent) 295 + { 296 + int irq; 280 297 298 + irq = irq_of_parse_and_map(node, 0); 299 + if (!irq) 300 + panic("Failed to get MISC IRQ"); 301 + 302 + ath79_misc_intc_domain_init(node, irq); 281 303 return 0; 282 304 } 283 305